A wafer test parameter screening method
By testing and storing the results at all reference current levels, combined with the baking process, the problem of complex and time-consuming wafer testing parameter selection is solved, and a fast and simplified selection method is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2023-04-27
- Publication Date
- 2026-06-19
AI Technical Summary
Existing technologies are complex and time-consuming in selecting wafer test parameters, mainly because the reference current level and cell window cannot be quantified, resulting in complex selection methods and high time consumption.
A method for screening wafer test parameters is provided, which includes testing all dies under all reference current ranges, including baking process between test results, storing test results and performing statistics to screen out the optimal reference current range.
By conducting a complete wafer test, a distribution chart of the reference current range and test results is obtained, which intuitively reflects the product characteristics, shortens the testing time, and reduces the complexity of screening.
Smart Images
Figure CN116500406B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit testing, and in particular to a method for screening wafer testing parameters. Background Technology
[0002] As integrated circuits become smaller and smaller, and the peripheral circuits of memory become simpler and simpler, higher requirements are placed on the selection of actual wafer testing parameters.
[0003] In current memory product CP testing (Circuit Probing or Chip Probing, also known as Wafer Sort, Wafer Probing, etc.), it is necessary to select the optimal parameter selection scheme. However, due to the fact that the reference current level is adjustable but cannot be quantized and the cell (memory cell) window cannot be quantized, the current selection method is complicated and time-consuming. Summary of the Invention
[0004] The purpose of this invention is to provide a method for screening wafer test parameters, which can reduce the complexity of screening wafer test parameters and reduce the time spent on screening wafer test parameters.
[0005] To address the above problems, this invention provides a method for screening wafer testing parameters, comprising the following steps:
[0006] A wafer to be tested is provided, the wafer comprising a plurality of dies;
[0007] Perform tests on each test item for all said dies at full reference current range, and store the test results for all said test items for each said die on the wafer; and
[0008] All test results were statistically analyzed to select the optimal reference current level for each test item.
[0009] Optionally, the test results include test pass and test fail.
[0010] Furthermore, a test result that passes is recorded as 1, and a test result that fails is recorded as 0.
[0011] Optionally, "performing each test item on all said dies at the full reference current range, and storing the test results of all said test items for each said die in the wafer" specifically includes:
[0012] At reference current levels 0 to n, each die is tested for the first test item at each reference current level, and all test results are stored in the wafer.
[0013] The wafer to be tested is subjected to a baking process;
[0014] At reference current levels 0 to n, each die is tested for the i-th test item at each reference current level, and all test results are stored in the wafer.
[0015] At reference current levels 0 to n, each die is tested for the (i+1)th test item at each level, and all test results are stored in the wafer; and
[0016] At reference current levels 0 to n, each die is tested for the m-th test item at each reference current level, and all test results are stored in the wafer, where m ≥ i, and m, n and i are all positive integers.
[0017] Furthermore, "under reference current ranges 0 to n, each die is tested for a first test item at each reference current range, and all test results are stored in the wafer" specifically includes:
[0018] At the reference current setting of 0, each of the aforementioned chips is tested using the first test item, and all the test results are stored on the wafer.
[0019] At the reference current level L, each of the aforementioned grains is tested using the first test item, and all the test results are stored in the wafer, where L is a positive integer and greater than 0;
[0020] At the reference current level L+1, each of the aforementioned chips is tested using the first test item, and all test results are stored on the wafer; and
[0021] At the reference current level n, each of the said dies is tested for the first test item, and all the test results are stored in the wafer.
[0022] Furthermore, "under reference current ranges 0 to n, each die is tested for the i-th test item at each reference current range, and all test results are stored in the wafer" specifically includes:
[0023] At the reference current setting of 0, the i-th test item is performed on each of the aforementioned dies, and all the test results are stored on the wafer;
[0024] At the reference current level L, the i-th test item is performed on each of the said dies, and all the test results are stored in the wafer, where L is a positive integer and greater than 0;
[0025] At the reference current level L+1, the i-th test item is performed on each of the aforementioned chips, and all test results are stored on the wafer; and
[0026] At the reference current level n, the i-th test item is performed on each of the said dies, and all the test results are stored in the wafer, where i ≥ 2.
[0027] Furthermore, "under reference current ranges 0 to n, each die is tested for the (i+1)th test item at each range, and all test results are stored in the wafer" specifically includes:
[0028] At the reference current setting of 0, each of the aforementioned dies is tested for the (i+1)th test item, and all the test results are stored on the wafer.
[0029] At the reference current level L, each of the aforementioned chips is tested for the (i+1)th test item, and all the test results are stored in the wafer, where L is a positive integer and greater than 0;
[0030] At the reference current level L+1, each of the aforementioned dies is tested for the (i+1)th test item, and all the test results are stored on the wafer;
[0031] At the reference current level n, each of the said chips is tested for the (i+1)th test item, and all the test results are stored in the wafer, where i ≥ 2.
[0032] Furthermore, "under reference current ranges 0 to n, each die is tested for the m-th test item at each reference current range, and all test results are stored in the wafer" specifically includes:
[0033] At the reference current setting of 0, the m-th test item is performed on each of the aforementioned grains, and all the test results are stored on the wafer;
[0034] At the reference current level L, the m-th test item is performed on each of the aforementioned grains, and all the test results are stored in the wafer, where L is a positive integer and greater than 0;
[0035] At the reference current level L+1, the m-th test item is performed on each of the aforementioned grains, and all the test results are stored on the wafer;
[0036] At the reference current level n, each of the said dies is tested for the m-th test item, and all the test results are stored in the wafer.
[0037] Optionally, all the test results are statistically analyzed to select the optimal reference current range for each test item, specifically including:
[0038] First, all the test results are statistically analyzed, and then a distribution chart of the test results is drawn based on the statistical analysis of all the test results.
[0039] Furthermore, the distribution map includes a discrete map and a histogram.
[0040] Compared with the prior art, the present invention has the following beneficial effects:
[0041] This invention provides a method for screening wafer test parameters, comprising the following steps: providing a wafer to be tested, the wafer comprising multiple dies; performing tests on each of the dies under a full reference current range for each test item, wherein a baking process is included between the first test item and the second test item, and storing the test results of all the test items for each die in the wafer; and statistically analyzing all the test results to screen out the optimal reference current range for each test item. By studying memory products where both the reference current and cell window are not quantifiable, a distribution map of the reference current range and test results can be obtained through a single complete wafer test, thereby intuitively reflecting product characteristics and determining the final CP screening scheme. The screening method of this invention shortens the testing time and reduces the screening time through only one baking process, and also reduces the complexity of screening wafer test parameters. Attached Figure Description
[0042] Figure 1 This is a flowchart illustrating a method for screening wafer testing parameters according to an embodiment of the present invention. Detailed Implementation
[0043] As described in the background section, current methods for selecting wafer testing parameters include:
[0044] First, set the reference current level to 0, perform the first test on each die of the wafer, then perform a bake process on the wafer, and finally perform the second to m-th test on all dies of the wafer.
[0045] Next, the reference current level is set to level 1, and the first test item is performed on each die of the wafer. Then, the wafer is baked. Finally, the second test item to the m-th test item are performed on all the dies of the wafer.
[0046] Next, the reference current range is set to L range in sequence. The first test item is performed on each die of the wafer. Then, the wafer is baked. Finally, the second test item to the m-th test item are performed on all the dies of the wafer.
[0047] Next, the reference current range is set to L+1. The first test item is performed on each die of the wafer. Then, the wafer is baked. Finally, the second test item to the m-th test item is performed on all the dies of the wafer.
[0048] Next, the reference current range is set to n levels in sequence. The first test item is performed on each die of the wafer. Then, the wafer is baked. Finally, the second to m-th test items are performed on all dies of the wafer. Here, n > L, and n and L are both positive integers.
[0049] Next, the test results of all test items for all the aforementioned wafers are statistically analyzed to obtain the optimal method for screening wafer test parameters.
[0050] As can be seen, the above method requires n bake processes, making the current screening method quite complex and time-consuming.
[0051] To address the above problems, this invention provides a method for screening wafer test parameters, comprising the following steps: providing a wafer to be tested, the wafer comprising multiple dies; performing tests on each of the dies for each test item at all reference current levels, wherein a baking process is included between the first test item and the second test item, and storing the test results of all the test items for each die in the wafer; and statistically analyzing all the test results to screen out the optimal reference current level for each test item. By studying memory products where both reference current and cell window are not quantifiable, a distribution map of reference current levels and test results can be obtained through a single complete wafer test, thereby intuitively reflecting product characteristics and determining the final CP screening scheme. This invention's screening method uses only a single baking process, shortening the testing time, reducing the screening time, and also reducing the complexity of screening wafer test parameters.
[0052] The following will provide a more detailed description of a method for screening wafer testing parameters according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0053] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0054] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.
[0055] Figure 1 This is a flowchart illustrating a method for selecting wafer testing parameters provided in this embodiment.
[0056] like Figure 1 As shown, this embodiment provides a method for screening wafer testing parameters, including the following steps:
[0057] Step S1: Provide a wafer to be tested, wherein the wafer to be tested comprises a plurality of dies;
[0058] Step S2: Perform each test item on all the said dies at the full reference current range, and store the test results of all test items for each said die in the wafer, wherein a baking process is included between the first test item and the second test item; and
[0059] Step S3: Statistically analyze all the test results to select the optimal reference current level for each test item.
[0060] The following provides a detailed description of a method for screening wafer testing parameters provided in this embodiment.
[0061] First, step S1 is performed, providing a wafer to be tested, which includes multiple dies.
[0062] In this step, the wafer to be tested is a new memory product that has not undergone actual testing and does not have the optimal wafer testing parameters required for wafer testing.
[0063] Next, step S2 is executed, where all the dies are tested for each test item under the full reference current range, and the test results for all test items for each die are stored in the wafer. A baking process is included between the first and second test items. The test results include test pass and test failure. In this step, a test pass is recorded as 1, and a test failure is recorded as 0.
[0064] This step specifically includes the following steps:
[0065] Step S21: At reference current range 0 to reference current range n, perform the first test item cp1 on each die at each reference current range, and store all the test results in the wafer.
[0066] In detail, firstly, at the reference current level 0, the first test item cp1 is performed on each die, and all test results are stored in the wafer; then, at the reference current level L, the first test item cp1 is performed on each die, and all test results are stored in the wafer, where L is a positive integer greater than 0; then, at the reference current level L+1, the first test item cp1 is performed on each die, and all test results are stored in the wafer; finally, at the reference current level n, the first test item cp1 is performed on each die, and all test results are stored in the wafer. This step can complete the first test item cp1 test for all the dies in the wafer under test in one process.
[0067] Step S22: Perform a baking process on the wafer to be tested to improve the data retention capability of the memory product (die).
[0068] Step S23: At reference current ranges 0 to n, the i-th test item cpi is tested for each die at each reference current range, and all test results are stored in the wafer.
[0069] In detail, firstly, at the reference current level 0, the i-th test item cpi is tested for each die, and all test results are stored in the wafer; then, at the reference current level L, the i-th test item cpi is tested for each die, and all test results are stored in the wafer, where L is a positive integer greater than 0; then, at the reference current level L+1, the i-th test item cpi is tested for each die, and all test results are stored in the wafer; finally, at the reference current level n, the i-th test item cpi is tested for each die, and all test results are stored in the wafer, where i ≥ 2. This step can complete the i-th test item cpi test for all the dies in the wafer under test in one process.
[0070] Step S24: At reference current range 0 to reference current range n, perform the i+1 test item for each die at each range, and store all test results in the wafer.
[0071] In detail, firstly, at the reference current level 0, each die is tested for the (i+1)th test item, and all test results are stored in the wafer. Then, at the reference current level L, each die is tested for the (i+1)th test item, and all test results are stored in the wafer, where L is a positive integer greater than 0. Next, at the reference current level L+1, each die is tested for the (i+1)th test item, and all test results are stored in the wafer. Finally, at the reference current level n, each die is tested for the (i+1)th test item, and all test results are stored in the wafer, where i ≥ 2. This step allows all the dies in the wafer to be tested to complete the (i+1)th test item test in a single process.
[0072] Step S25: At reference current levels 0 to n, perform the m-th test item on each die at each reference current level, and store all the test results in the wafer, where m ≥ i and is a positive integer.
[0073] In detail, firstly, at the reference current level 0, the m-th test item is performed on each die, and all test results are stored in the wafer; then, at the reference current level L, the m-th test item is performed on each die, and all test results are stored in the wafer, where L is a positive integer greater than 0; then, at the reference current level L+1, the i-th test item is performed on each die, and all test results are stored in the wafer; finally, at the reference current level n, the m-th test item is performed on each die, and all test results are stored in the wafer. This step allows all the dies in the wafer to be tested to complete the m-th test item in one process.
[0074] Next, step S3 is executed to statistically analyze all the test results in order to select the optimal reference current level for each test item.
[0075] This step specifically includes:
[0076] First, all the test results are statistically analyzed, and then a distribution chart of the test results is drawn based on the statistical analysis of all the test results.
[0077] This step involves statistically analyzing the test results of all test items for each particle at reference current ranges 0 to n, obtaining a complete distribution chart of reference current ranges and test results, and accumulating the number of tests passed for each test item at reference current ranges 0 to n. The range with the highest number of passed tests is then identified as the optimal reference current range for the corresponding test item.
[0078] The wafer test parameter screening method in this embodiment shortens the testing time and reduces the screening time by using only one baking process, and also reduces the complexity of screening wafer test parameters.
[0079] The following tests were performed on a wafer consisting of P dies, using reference current ranges 0 to 7, for the first test item CP1, the second test item CP2, and the third test item CP3, as shown in the table below:
[0080]
[0081] Table 1
[0082]
[0083] Table 2
[0084] In Table 1, each data point represents the test results of a single chip at each reference current level. Taking the data "00111000" in the first row and first column as an example, these eight digits, from left to right, represent the test results of reference current levels 0 to 7 in the first test item CP1. 0 indicates a test failure and 1 indicates a test pass. Table 2 can be derived from Table 1.
[0085] Each data point in Table 2 represents the cumulative test results for the corresponding test item at the corresponding reference current level. For example, with a reference current level of 3 and the test item being the first test item CP1, the data 75 indicates that 75 chips passed the first test item at a reference current level of 3. This example allows you to directly find the optimal reference current level for each test item using the test results statistically presented in Table 2. Furthermore, you can plot the test result distribution (e.g., discrete graph, histogram, etc.) based on the statistics in Table 2 to easily and intuitively find the optimal reference current level for each test item, thus directly reflecting the product characteristics of the memory product. According to Table 2, in actual testing, the first test item CP1 can be tested at a reference current level of 3, the second test item CP2 at a reference current level of 3, and the third test item CP3 at a reference current level of 4. This ultimately yields the method for selecting wafer test parameters during actual testing.
[0086] In summary, this invention provides a method for screening wafer test parameters. By studying memory products where the reference current and cell window are not quantifiable, a distribution map of the reference current level and test results can be obtained through a single complete wafer test, thus intuitively reflecting the product characteristics and determining the final CP screening scheme. The screening method of this invention only requires a baking process, which shortens the testing time, reduces the screening time, and also reduces the complexity of screening wafer test parameters.
[0087] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0088] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A method for screening wafer testing parameters, characterized in that, Includes the following steps: A wafer to be tested is provided, the wafer comprising a plurality of dies; All said dies are tested for each test item at full reference current range, and the test results for all said dies for each test item are stored in the wafer, wherein a baking process is included between the first test item and the second test item; and All the test results were statistically analyzed to select the optimal reference current level for each test item; Specifically, "performing tests on each test item for all said dies at all reference current levels, and storing the test results for all said test items for each said die in the wafer" includes: At reference current levels 0 to n, each die is tested for the first test item at each reference current level, and all test results are stored in the wafer. The wafer to be tested is subjected to a baking process; At reference current levels 0 to n, each die is tested for the i-th test item at each reference current level, and all test results are stored in the wafer. At reference current levels 0 to n, each die is tested for the (i+1)th test item at each level, and all test results are stored in the wafer; and At reference current levels 0 to n, each die is tested for the m-th test item at each reference current level, and all test results are stored in the wafer, where m ≥ i, i ≥ 2, and m, n, and i are all positive integers.
2. The method for screening wafer testing parameters as described in claim 1, characterized in that, The test results include test pass and test fail.
3. The method for screening wafer testing parameters as described in claim 1, characterized in that, A test result of 1 is recorded as a pass, and a test result of 0 is recorded as a fail.
4. The method for screening wafer testing parameters as described in claim 1, characterized in that, "At reference current levels 0 to n, each die is tested for the first test item at each reference current level, and all test results are stored in the wafer" specifically includes: At the reference current setting of 0, each of the aforementioned chips is tested using the first test item, and all the test results are stored on the wafer. At the reference current level L, each of the aforementioned grains is tested using the first test item, and all the test results are stored in the wafer, where L is a positive integer and greater than 0; At the reference current level L+1, each of the aforementioned chips is tested using the first test item, and all test results are stored on the wafer; and At the reference current level n, each of the said dies is tested for the first test item, and all the test results are stored in the wafer.
5. The method for screening wafer testing parameters as described in claim 1, characterized in that, "At reference current levels 0 to n, each die is tested for the i-th test item at each reference current level, and all test results are stored in the wafer" specifically includes: At the reference current setting of 0, the i-th test item is performed on each of the aforementioned dies, and all the test results are stored on the wafer; At the reference current level L, the i-th test item is performed on each of the said dies, and all the test results are stored in the wafer, where L is a positive integer and greater than 0; At the reference current level L+1, the i-th test item is performed on each of the aforementioned chips, and all test results are stored on the wafer; and At the reference current level n, the i-th test item is performed on each of the said dies, and all the test results are stored in the wafer, where i≥2.
6. The method for screening wafer testing parameters as described in claim 1, characterized in that, "At reference current levels 0 to n, each die is tested for the (i+1)th test item at each level, and all test results are stored in the wafer" specifically includes: At the reference current setting of 0, each of the aforementioned dies is tested for the (i+1)th test item, and all the test results are stored on the wafer; At the reference current level L, each of the aforementioned chips is tested for the (i+1)th test item, and all the test results are stored in the wafer, where L is a positive integer and greater than 0; At the reference current level L+1, each of the aforementioned dies is tested for the (i+1)th test item, and all the test results are stored in the wafer; At the reference current level n, each of the said chips is tested for the (i+1)th test item, and all the test results are stored in the wafer, where i ≥ 2.
7. The method for screening wafer testing parameters as described in claim 1, characterized in that, "At reference current levels 0 to n, each die is tested for the m-th test item at each reference current level, and all test results are stored in the wafer" specifically includes: At the reference current setting of 0, the m-th test item is performed on each of the aforementioned grains, and all the test results are stored on the wafer; At the reference current level L, each of the aforementioned grains is tested for the m-th test item, and all the test results are stored in the wafer, where L is a positive integer and greater than 0; At the reference current level L+1, the m-th test item is performed on each of the aforementioned dies, and all the test results are stored on the wafer; At the reference current level n, each of the said dies is tested for the m-th test item, and all the test results are stored in the wafer.
8. The method for screening wafer testing parameters as described in claim 1, characterized in that, All test results were statistically analyzed to select the optimal reference current range for each test item, specifically including: First, all the test results are statistically analyzed, and then a distribution chart of the test results is drawn based on the statistical analysis of all the test results.
9. The method for screening wafer testing parameters as described in claim 8, characterized in that, The distribution map includes a discrete map and a histogram.
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