A kendall correlation detector based on zynq

Abstract

The application discloses a Kendall correlation detector based on Zynq, which comprises a software end control module at a PS end, a hardware acceleration module at a PL end for acquiring radar signal data from the software end control module at the PS end, and comprises an input counting module, a pulse array module for calculating a Kendall correlation coefficient, an output counting module and an output control module; the pulse array module for calculating the Kendall correlation coefficient is used for rapidly calculating the Kendall correlation coefficient according to the radar signal data and sending the Kendall correlation coefficient to the output control module; the input counting module and the output counting module are respectively used for reading the number of the pulse array module data entering and outputting the Kendall correlation coefficient and sending the number to the output control module. The Kendall correlation coefficient of the radar signal in a radar system is rapidly calculated based on the pulse array of the Zynq, the algorithm is reduced from the square order of time complexity to the constant order, so as to adapt to a high sampling rate signal detection system with strict real-time requirement such as a radar.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a Kendall correlation detector based on Zynq. Background Technology

[0002] Detecting the presence of useful signals against a background of strong noise is a primary and critical challenge for signal processing systems. Parametric optimal detectors theoretically possess optimal detection performance; however, their performance deteriorates drastically when the noise model does not match the actual noise. To address the shortcomings of parametric detectors, Kendall correlation coefficients, based on rank statistics, still exhibit good performance when the noise model does not match the actual noise. However, with the development of digital signal processing technology, the sampling rates of radar systems are becoming increasingly higher, potentially reaching several gigahertz. At such high sampling frequencies, according to the original definition of a Kendall correlation detector, computation using pure software or ordinary hardware requires a time complexity on the order of the square, making it difficult to apply to radar systems with high real-time requirements. Therefore, how to enable Kendall correlation detectors to rapidly calculate the Kendall correlation coefficient, thereby reducing the detector's time complexity, is a pressing problem to be solved in this field. Summary of the Invention

[0003] To address at least one of the aforementioned technical problems, this invention provides a Kendall correlation detector based on Zynq, comprising:

[0004] The system comprises a software control module on the PS side and a hardware acceleration module on the PL side; the hardware acceleration module on the PL side is used to acquire radar signal data from the software control module on the PS side; wherein,

[0005] The hardware acceleration module at the PL end includes an input counting module, a pulsating array module for calculating Kendall correlation coefficients, an output counting module, and an output control module.

[0006] The pulsating array module for calculating the Kendall correlation coefficient is used to calculate the Kendall correlation coefficient based on the radar signal data and send it to the output control module.

[0007] The input counting module and the output counting module are respectively used to read the number of data entering the pulsation array module of the Kendall correlation coefficient and the number of data output from the pulsation array module of the Kendall correlation coefficient, and send them to the output control module respectively.

[0008] In one possible implementation, the Zynq-based Kendall correlation detector further includes a DMA for reading radar signal data from the software control module at the PS end, splitting the data into transmit signal data and receive signal data, and sending them to the hardware acceleration module at the PL end.

[0009] In one possible implementation, the pulsating array module for calculating the Kendall correlation coefficient includes n rows × n columns of operation units, where n is the length of the transmitted signal data; wherein, the operation units in the first n-1 rows are the first operation units, and the operation units in the nth row are the second operation units.

[0010] In one possible implementation, the first arithmetic unit includes an adder, a subtractor, two greater than comparators, a less than comparator, ten two-way selectors, and seven D flip-flops.

[0011] In one possible implementation, the second arithmetic unit includes two adders, one subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops.

[0012] In one possible implementation, the input counting module includes an adder and a D flip-flop.

[0013] In one possible implementation, the output counting module includes an adder and a D flip-flop.

[0014] In one possible implementation, the output control module includes an adder, an equals comparator, a less than or equal to comparator, two AND gates, two D flip-flops, and a synchronously reset D flip-flop.

[0015] In one possible implementation, the software control module of the PS terminal includes a data transmission logic unit and a data reception logic unit.

[0016] In one possible implementation, the transmitting data logic unit is used to take radar transmitted signal data of length n and radar received signal data of length m as low w bits wide data as transmitting signal data; the receiving data logic unit is used to combine the high w bits of the received signal data into a set of data with a bit width of 2w and store it in DDR.

[0017] Compared to existing technologies, the advantages of this application are as follows:

[0018] This invention, based on the original definition of the Kendall correlation detector and a rewritten definition on the Zynq UltraScale+ platform, utilizes the unique ARM+FPGA architecture of the Zynq SoC and the high-speed AXI bus built into Zynq to facilitate data interaction between the software and hardware pulsation array modules. This reduces the time complexity of the existing Kendall correlation coefficient algorithm used in radar systems from the quadratic order of time to the constant order of time, making it suitable for high sampling rate signal detection systems such as radar that have stringent real-time requirements.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0022] Figure 1 A schematic diagram of the structure of a Kendall correlation detector based on Zynq provided for a certain embodiment of this application;

[0023] Figure 2 This application provides a block diagram of a detection circuit for a Kendall correlation detector based on Zynq, according to one embodiment of the present application.

[0024] Figure 3 This is a schematic diagram of the structure of a hardware acceleration module at the PL end according to a certain embodiment of this application;

[0025] Figure 4 for Figure 3 A schematic diagram of the input counting module of the hardware acceleration module in the middle PL terminal;

[0026] Figure 5 for Figure 3 A schematic diagram of the output counting module of the hardware acceleration module in the middle PL terminal;

[0027] Figure 6 for Figure 3 A schematic diagram of the pulsating array module for calculating the Kendall correlation coefficient in the hardware acceleration module of the mid-PL end;

[0028] Figure 7 for Figure 6 A schematic diagram of the structure of the first computational unit in the pulsating array module for calculating the Kendall correlation coefficient;

[0029] Figure 8 for Figure 6 A schematic diagram of the structure of the second computation unit in the pulsating array module for calculating the Kendall correlation coefficient;

[0030] Figure 9 for Figure 3 A schematic diagram of the output control module of the hardware acceleration module at the middle PL end. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0032] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0033] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0034] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0035] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without certain specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order to highlight the spirit of the invention.

[0036] In existing technologies, based on the original definition of the Kendall correlation detector, the computation using pure software or ordinary hardware requires a time complexity on the order of quadratices, making it difficult to apply to radar systems with high real-time requirements. To provide a fast algorithm implemented in hardware to reduce the detector's time complexity, the original definition of the Kendall correlation coefficient first needs to be rewritten.

[0037] Specifically, let n be the length of the transmitted signal. Let represent the received signal and radar transmitted signal sequences of length n, respectively. The original definition of the Kendall correlation coefficient is as follows:

[0038]

[0039] In the formula, T KT x represents the Kendall correlation coefficient. i x j They are respectively The i-th and j-th numbers in the sequence; y i y j They are respectively The i-th and j-th numbers in the sequence; the sign(.) function represents the unit sign function.

[0040] It can be proven that:

[0041]

[0042] Where H(t) is the unit step function and sign(t) is the unit sign function:

[0043]

[0044]

[0045] The proof is as follows: by using the property of the sign function sign(·)=2H(·)-1, we can expand (1) to obtain:

[0046]

[0047] And because it satisfies:

[0048]

[0049] Therefore, we prove that:

[0050]

[0051] Therefore, based on formula (6), i.e. the rewritten definition of Kendall correlation coefficient, a parallel algorithm suitable for pulsating arrays can be developed.

[0052] Please see Figure 1 , Figure 1 A schematic diagram of a Kendall correlation detector based on Zynq is provided. Figure 1 As shown, the Zynq-based Kendall correlation detector includes:

[0053] The system comprises a software control module on the PS side and a hardware acceleration module on the PL side; the hardware acceleration module on the PL side is used to acquire radar signal data from the software control module on the PS side; wherein,

[0054] The hardware acceleration module at the PL end includes an input counting module, a pulsating array module for calculating Kendall correlation coefficients, an output counting module, and an output control module.

[0055] The pulsating array module for calculating the Kendall correlation coefficient is used to calculate the Kendall correlation coefficient based on the radar signal data and send it to the output control module.

[0056] The input counting module and the output counting module are respectively used to read the number of data entering the pulsation array module of the Kendall correlation coefficient and the number of data output from the pulsation array module of the Kendall correlation coefficient, and send them to the output control module respectively.

[0057] In this embodiment, the fast algorithm of the Kendall correlation detector is implemented based on the Zynq UltraScale+ platform. The Zynq SoC consists of an ARM architecture on the PS side and an FPGA part on the PL side. The entire Kendall correlation detector consists of a software control module on the PS side and a hardware acceleration module on the PL side. The hardware acceleration module includes an input counting module, a pulsation array module for calculating the Kendall correlation coefficient, an output counting module, and an output control module. The PS side and the PL side communicate via AXI-DMA.

[0058] As an optional implementation, AXI-DMA is an IP instantiated in the FPGA of Zynq. It can be configured by connecting it in Block Design through Vivado configuration parameters.

[0059] In one specific embodiment, the software control module of the PS terminal includes a software-based data transmission logic unit and a data reception logic unit. The data transmission logic unit is used to transmit radar transmitted signal data of length n and radar received signal data of length m, using data with a low bit width of w.

[0060] Please see Figure 2 , Figure 2 A schematic diagram of the detection circuit in a Kendall correlation detector based on Zynq is provided.

[0061] In this embodiment, the software-side control module includes a software-side data transmission logic unit and a data reception logic unit. Assuming the bit width of the signal data is w, the data transmission part combines radar transmitted signal data of length n and radar received signal data of length m, using the lower w bits as the transmitted signal data and the higher w bits as the received signal data, into a data set with a bit width of 2w and stores it in DDR. The mn data bits that are missing from the received data in the transmitted data can be filled with arbitrary values. Data transmission to the hardware acceleration module is completed by calling functions already encapsulated in the Xilinx SDK. The data reception part stores the data transmitted from the hardware acceleration module in DDR by calling functions already encapsulated in the Xilinx SDK, such as... Figure 2 As shown.

[0062] In one possible implementation, the Zynq-based Kendall correlation detector further includes a DMA for reading radar signal data from the software control module at the PS end, splitting the data into transmit signal data and receive signal data, and sending them to the hardware acceleration module.

[0063] Please see Figure 2 ,Depend on Figure 2 It is known that the Kendall correlation detector based on Zynq also includes DMA, in which the software control module at the PS end and the hardware acceleration module at the PL end (in Figure 2 The hardware pulsating array parallel module (in the middle) interacts with data via DMA.

[0064] Further, please refer to Figure 3 , Figure 3 A schematic diagram of the hardware acceleration module on the PL side is provided. Figure 3 It can be seen that the hardware acceleration module is implemented on the PL end through a hardware circuit built by FPGA. It consists of an input counting module, a pulsating array module for calculating Kendall correlation coefficient, an output counting module, and an output control module. It reads data from the PS end, performs hardware acceleration calculations, and sends the calculation results back to the PS end.

[0065] In one possible implementation, the input counting module includes an adder and a D flip-flop; the input counting module is used to read the number of input data from the AXI-DMA and send it to the output control module. The output counting module includes an adder and a D flip-flop; the output counting module is used to read the number of pulsation array modules used to calculate the Kendall correlation coefficient and send it to the output control module.

[0066] Please see Figure 4-5 , Figure 4 , 5 Schematic diagrams of the input counting module and output counting module in the hardware acceleration module of the PL are provided respectively. Figure 4-5It can be seen that both the input counting module and the output counting module include an adder and a D flip-flop. The output of the D flip-flop serves as the output of count_in and one input of the adder. The other input of the adder is 1, and the output of the adder serves as the input of the D flip-flop. When the reset signal rst_in is 1, count_in and count_out start from 0 and are incremented by one on each rising edge of the clock, thereby realizing the counting of input data.

[0067] In one possible implementation, the pulsating array module for calculating the Kendall correlation coefficient includes n rows × n columns of arithmetic units, where n is the length of the transmitted signal data; wherein the arithmetic units in the first n-1 rows are the first arithmetic units, and the arithmetic units in the nth row are the second arithmetic units.

[0068] Please see Figure 6 , Figure 6 A schematic diagram of the pulsating array module for calculating the Kendall correlation coefficient is provided. Figure 6 As shown, the pulsating array module for calculating the Kendall correlation coefficient consists of n×n processing units (where n is the length of the transmitted signal data). The AXI-DMA reads the integrated data from the software and splits it back into transmitted and received signal data. Then, it calculates the Kendall correlation coefficient between the transmitted and received signal data through hardware acceleration and transmits the calculation results to the output control module and the output counting module.

[0069] Furthermore, the n×n operational units are divided into two types: the operational units in the first n-1 rows are the first operational units (in... Figure 6 The middle row is the operation unit 1), and the operation unit in the nth row is the second operation unit (in... Figure 6 The middle part is the arithmetic unit 2). Among them, the arithmetic unit 1 has a clock input interface clk_in, a clock output interface clk_out, horizontal input data interfaces Xi_in, Yi_in, In, horizontal output data interfaces Xi_out, Yi_out, Out, vertical input data interfaces Xj_in, Yj_in, vertical output data interfaces Xj_in, Yj_out, a reset input interface rst_in, and a reset output interface rst_out. When the reset input signal is 1, it means that the arithmetic unit is started.

[0070] Operation unit 2 has one more horizontal data input In_i than operation unit 1, while the original data input In becomes a vertical data input In_j. Solid arrows in the diagram indicate the direction of data flow, and dashed arrows indicate the direction of the flow of operation results. The reset input rst_in in the first row and first column of the pulse array is the valid output signal read from the AXI-DMA. When the reset input rst_in of the operation unit in the first row and first column is 1, the operation unit is activated.

[0071] The reset input rst_in of the remaining arithmetic units in the first column is the reset output rst_out of the arithmetic unit located in the row above it in the same column of the systolic array. The reset input rst_in of the arithmetic units in other columns is the reset output rst_out of the arithmetic unit located in the left column of the same row in the systolic array. The horizontal data input In of the first row, first column is 0. X_in is the low w bits of data read from AXI-DMA, Yi_in is the high w bits of data read from AXI-DMA, the vertical data input Yj_in is the high w bits of data read from AXI-DMA, and the clock signal input is the clock signal read from AXI-DMA. The vertical data input Yj_in of the other arithmetic units in the first row is the high w bits of data read from AXI-DMA, and the clock input and other horizontal data inputs are the corresponding outputs of the arithmetic units in the left column of the same row. The horizontal data input In of the other operation units in the first column is 0, X_in is the low w bits of data read from AXI-DMA, Yi_in is the high w bits of data read from AXI-DMA, the vertical data input Yj_in is the data output Yj_out of the operation unit above in the same column, and the clock input is the clock output of the operation unit above in the same column. For the remaining operation units, the clock input is the clock output of the operation unit to its left, the horizontal data input is the corresponding data output of the operation unit to its left, and the vertical data input is the data output of the operation unit above it. The final output is from the operation unit in the last row and last column, where Out is the correlation coefficient. The first correlation coefficient requires 2n-1 clock cycles, and each subsequent correlation coefficient can be obtained in just one clock cycle.

[0072] In one possible implementation, the first arithmetic unit includes an adder, a subtractor, two greater than comparators, a less than comparator, ten two-way selectors, and seven D flip-flops.

[0073] Please see Figure 7 , Figure 7 A structural diagram of the first arithmetic unit (arithmetic unit 1) is provided. For example... Figure 7As shown, the operational unit 1 of the pulsating array for calculating the Kendall correlation coefficient consists of an adder, a subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops. Its function is to delay the inputs Xi_in, Xj_in, Yi_in, Yj_in, and rst_in by one clock cycle and output them from the output ports Xi_out, Xj_out, Yi_out, Yj_out, and rst_out. At the same time, it delays the output from the output port Out by one clock cycle and outputs In+H(Xi_in-Xj_in)*sign(Yi_in-Yj_in).

[0074] In one possible implementation, the second arithmetic unit includes two adders, one subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops.

[0075] Please see Figure 8 , Figure 8 A structural diagram of the second arithmetic unit (arithmetic unit 2) is provided. For example... Figure 8 As shown, the operational unit 2 of the pulsating array for calculating the Kendall correlation coefficient consists of two adders, one subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops. Its function is to delay the inputs Xi_in, Xj_in, Yi_in, Yj_in, and rst_in by one clock cycle and output them from the output ports Xi_out, Xj_out, Yi_out, Yj_out, and rst_out. At the same time, it delays the outputs from the output port Out by one clock cycle and outputs In_i+In_j+H(Xi_in-Xj_in)*sign(Yi_in-Yj_in).

[0076] In one possible implementation, the output control module includes an adder, an equals comparator, a less than or equal to comparator, two AND gates, two D flip-flops, and a synchronously reset D flip-flop.

[0077] Please see Figure 9 , Figure 9 A schematic diagram of the output control module is provided. (For example...) Figure 9 As shown, the output control module consists of an adder, an equals comparator, a less than or equal to comparator, two AND gates, two D flip-flops, and a synchronously reset D flip-flop. Its specific function is as follows: when the output count value is less than the input count value -n+1, ​​the valid output bit is set to 1, and the input value In is multiplied by 6 / n (n^2-1) as the output value Out in the next cycle. When the output count value equals the input count value -n+1, ​​the output is set to last, indicating that this is the last valid output.

[0078] To aid understanding, the following concrete example will illustrate the process of accelerating the calculation of the Kendall correlation coefficient using this Zynq-based Kendall correlation detector:

[0079] This invention can be applied to radar systems. Assuming the signal data bit width is w, the radar transmitted signal length is n, and the received signal length is m (m is greater than n), the transmitted and received signal data are stored in the DDR of the PS terminal.

[0080] The software control module combines the transmitted and received signal data into a single data set with a length of m bits and a width of 2w bits (where the lower w bits containing values ​​greater than n can be arbitrary) using the low w bits for transmitted signal data and the high w bits for received signal data. This data is then stored in DDR. After the data enters DDR, the DMA is controlled by the XAxiDma_SimpleTransfer function, which allows DMA to transfer the data from the specified address in DDR to the hardware acceleration module.

[0081] The PL-side hardware acceleration module consists of an input counting module, a pulsating array module for calculating Kendall's correlation coefficient, an output counting module, and an output control module.

[0082] The input counting module is responsible for counting the number of input data read from the AXI-DMA. For example... Figure 3 As shown, the input counting module includes an adder and a D flip-flop. The output of the D flip-flop serves as the output of count_in and one input of the adder. The other input of the adder is 1, and the output of the adder serves as the input of the D flip-flop. When the reset signal rst_in is 1, count_in starts to output from 0 and increments by one on each rising edge of the clock to count the input data. The count value of the input data is then transmitted to the output control module.

[0083] The pulsating array used to calculate the Kendall correlation coefficient reads data from the AXI-DMA, calculates the Kendall correlation coefficient between the transmitted and received signal data, and sends the result to the output control module. This is achieved through methods such as... Figure 6 The method shown combines n*n (n is the length of the transmitted signal) computational units into a pulsating array to calculate the Kendall correlation coefficient. The combination method is described in the above embodiment.

[0084] The operational unit 1 of the pulsating array for calculating the Kendall correlation coefficient consists of an adder, a subtractor, two greater-than comparators, one less-than comparator, ten two-way selectors, and seven D flip-flops, as follows: Figure 7As shown. Its function is to delay the inputs Xi_in, Xj_in, Yi_in, Yj_in and rst_in by one clock cycle and output them from the output ports Xi_out, Xj_out, Yi_out, Yj_out and rst_out, respectively. At the same time, it delays the output from the output port Out by one clock cycle and outputs In+H(Xi_in-Xj_in)*sign(Yi_in-Yj_in).

[0085] The operational unit 2 of the pulsating array for calculating the Kendall correlation coefficient consists of two adders, one subtractor, two greater-than comparators, one less-than comparator, ten two-way selectors, and seven D flip-flops, as follows: Figure 8 As shown, its function is to delay the inputs Xi_in, Xj_in, Yi_in, Yj_in and rst_in by one clock cycle and output them from the output ports Xi_out, Xj_out, Yi_out, Yj_out and rst_out, respectively. At the same time, it delays the output from the output port Out by one clock cycle and outputs In_i+In_j+H(Xi_in-Xj_in)*sign(Yi_in-Yj_in).

[0086] The output control module calculates the number of input data points read from the pulsating array module used to calculate the Kendall correlation coefficient. For example... Figure 7 As shown, the output counting module includes an adder and a D flip-flop. The output of the D flip-flop serves as the output of count_in and one input of the adder. The other input of the adder is 1, and the output of the adder serves as the input of the D flip-flop. When the reset signal rst_in is 1, count_out starts to output from 0 and increments by one on each rising edge of the clock to count the output data. The count value of the output data is then transmitted to the output control module.

[0087] The input counting module and the output counting module count the number of data read from AXI-DMA and the number of data output by the pulsating array module that calculates the Kendall correlation coefficient, respectively, and send them to the output control module.

[0088] like Figure 9As shown, the output control module consists of an adder, an equals comparator, a less than or equal to comparator, two AND gates, two D flip-flops, and a synchronously reset D flip-flop. Its specific function is as follows: when the output count value is less than the input count value -n+1, ​​the valid output bit is output as 1, and the input value In is multiplied by 6 / n (n^2-1) as the output value Out in the next cycle. When the output count value equals the input count value -n+1, ​​the output is "last" (output as 1), indicating that this is the last valid output. The output control module sends the calculation result back to the software module via AXI-DMA. The software module controls the DMA through the XAxiDma_SimpleTransfer function, and the DMA stores the data in DDR. AXI-DMA is an IP instantiated in the Zynq FPGA, and its configuration can be completed by connecting it in the Block Design through Vivado configuration parameters. Finally, the calculation result in DDR is analyzed to determine whether the received signal contains the signal of interest.

[0089] It should be noted that this invention is based on Zynq, but the core lies in using the pulse array of the FPGA on the PL side of Zynq to achieve hardware acceleration. Therefore, in other embodiments, the fast algorithm can also be implemented using the "PC+FPGA" approach through other types of communication methods, and no limitations are made here.

[0090] In summary, this invention rewrites the original definition of the Kendall correlation detector and, based on the rewritten definition on the Zynq UltraScale+ platform, utilizes the special ARM+FPGA architecture of the Zynq SoC and the high-speed AXI bus built into Zynq to perform data interaction between the software and hardware pulsation array modules, thereby reducing the time complexity of the existing Kendall correlation coefficient algorithm applied to radar systems from O(n^2) to a constant order of magnitude O(1).

[0091] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in practical applications, there may be other division methods. For example, multiple units or page components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0092] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0093] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0094] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A Zynq-based Kendall correlation detector, characterized in that, include: The software control module on the PS side and the hardware acceleration module on the PL side; The hardware acceleration module at the PL end is used to acquire radar signal data from the software control module at the PS end; wherein, The hardware acceleration module at the PL end includes an input counting module, a pulsating array module for calculating Kendall correlation coefficients, an output counting module, and an output control module. The pulsating array module for calculating the Kendall correlation coefficient is used to calculate the Kendall correlation coefficient based on the radar signal data and send it to the output control module. The input counting module and the output counting module are respectively used to read the number of data entering the pulsation array module of the Kendall correlation coefficient and the number of data output from the pulsation array module of the Kendall correlation coefficient, and send them to the output control module respectively; The pulsating array module for calculating the Kendall correlation coefficient includes n rows × n columns of operation units, where n is the length of the transmitted signal data; wherein, the operation units in the first n-1 rows are the first operation units, and the operation units in the nth row are the second operation units; The first arithmetic unit includes an adder, a subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops.

2. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, It also includes DMA, which is used to read radar signal data from the software control module of the PS end, and split the data into transmit signal data and receive signal data, and send them to the hardware acceleration module of the PL end.

3. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, The second arithmetic unit includes two adders, one subtractor, two greater than comparators, one less than comparator, ten two-way selectors, and seven D flip-flops.

4. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, The input counting module includes an adder and a D flip-flop.

5. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, The output counting module includes an adder and a D flip-flop.

6. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, The output control module includes an adder, an equal to comparator, a less than or equal to comparator, two AND gates, two D flip-flops, and a synchronously reset D flip-flop.

7. The Kendall correlation detector based on Zynq according to claim 1, characterized in that, The software control module of the PS terminal includes a data transmission logic unit and a data reception logic unit.

8. The Kendall correlation detector based on Zynq according to claim 7, characterized in that, The transmitting data logic unit is used to use radar transmitted signal data of length n and radar received signal data of length m as the transmitting signal data with a low bit width of w; the receiving data logic unit is used to combine the high bit of the received signal data into a set of data with a bit width of 2w and store it in DDR.

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