False-alarm-rate-constant processing method and device, computer device and storage medium

Abstract

The application provides a constant false alarm rate processing method and device, computer equipment and a storage medium, the method comprising calculating the mean value of the first N / 2 reference units of the first measured unit to obtain a first mean value; calculating the mean value of the N / 2+1 to N reference units after the first measured unit to obtain a second mean value; using a constant false alarm rate detection algorithm to calculate the first mean value and the second mean value to obtain a first operation value; calculating the mean value of the N+1 to 3N / 2 reference units after the second measured unit to obtain a third mean value; using a constant false alarm rate detection algorithm to calculate the second mean value and the third mean value to obtain a second operation value. For the second operation value, only the third mean value needs to be calculated, the calculation process of the second mean value is saved, the calculation of each second operation value can save the corresponding calculation process, and the calculation efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of radar data processing technology, and in particular to a constant false alarm rate (CFAR) processing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] A radar system typically consists of two parts: a hardware front-end and a processing back-end. The hardware front-end usually includes a waveform generator, transmitter, receiver, antenna, servo system, and power supply. The processing back-end typically includes signal processing, data processing, information storage and transmission, and display control. The waveform generator produces a radio frequency excitation signal with a specific operating frequency and modulation scheme, also known as the excitation source, and simultaneously generates a coherent local oscillator signal, which is sent to the receiver. The transmitter amplifies the radio frequency excitation signal provided by the excitation source and then feeds it to the antenna via a transceiver switch, where it is radiated. The target echo signal travels through the antenna and transceiver switch to the receiver, where it undergoes low-noise amplification, mixing, and filtering. Signal processing suppresses unwanted signals, such as clutter and interference, and improves the signal-to-weight ratio of the useful signal through coherent or incoherent accumulation. Target detection and false alarm control are achieved using methods such as Moving Target Detection (MTD) and Constant False Alarm Rate (CFAR).

[0003] The signal processing system is the core component of a radar system, determining its target detection performance. The signal processing system primarily utilizes various methods to suppress clutter and interference, detect targets, and extract target information from received radar signals. Radar signal detection always occurs against a background of interference, including internal receiver thermal noise, ground clutter, rain, snow, ocean waves, and sometimes active and passive jamming from the enemy. The purpose of CFAR (Constant False Alarm Rate) is to maintain a constant false alarm rate during signal detection under interference, preventing the computer from becoming overloaded during data processing. This automatic detection process requires no operator intervention; the electronic judgment circuitry executes the necessary actions for detection and decision-making. Modern radars employ automatic detection to overcome the limitations of operator skill.

[0004] CFAR algorithms have various branches, such as mean-based CFAR, statistically ordered CFAR, adaptive CFAR, and clutter map CFAR. Each type of CFAR has subtle differences in implementation, and its advantages and disadvantages also differ. The core implementation of CFAR is to estimate the noise and interference levels around the target cell, and this estimation process can only be achieved by "traversing" the envelope sum near the target. In the implementation of CFAR, such as one-dimensional CFAR, two-dimensional CFAR, and quadratic CFAR, a common feature is that they simultaneously traverse the information around the target point, such as the envelope levels within the left, right, up, and down reference ranges. With the development of technology, the radar cross-section of the detected target is becoming increasingly smaller, resulting in larger and larger bandwidths and time widths of radar signals, leading to a larger amount of data in the detected signal. The traversal operation of CFAR detection requires detecting every single point. This characteristic makes the running speed of CFAR often a major limitation on the real-time performance of signal processing systems. How to efficiently and quickly implement CFAR detection has become one of the urgent problems to be solved in the field of radar applications.

[0005] Traditional radar signal processing systems employ a hardware architecture combining Field-Programmable Gate Arrays (FPGAs) and Digital Signal Processing Chips (DSPs) to develop signal processing functions such as Pulse Compression (PC), Moving Target Indication (MTI), MTD, and CFAR. However, due to computational resource limitations, the two types of chips must allocate functions, with each implementing a portion of the functionality. As radar operating environments become increasingly complex and performance requirements rise, the FPGA+DSP hardware architecture places significant limitations on performance improvements, upgrades, and maintenance of radar signal processing systems.

[0006] Traditional CFAR implementations consume significant computational resources, impacting system real-time performance. In radar signal processing systems, the CFAR algorithm is often the final and most crucial component. Since CFAR's function is to control the false alarm rate, reduce the amount of data transmitted to the data processing system, and prevent the system from overloading or losing critical information due to excessive data volume, CFAR performance affects not only the real-time performance of the signal processing system but also its stability. Traditional CFAR implementations often involve numerous repetitive calculations, consuming excessive computational resources and reducing system real-time performance. Summary of the Invention

[0007] Therefore, it is necessary to provide a constant false alarm rate processing method, apparatus, computer equipment, and storage medium to address the aforementioned technical problems.

[0008] A method for handling constant false alarm rate includes:

[0009] Calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean;

[0010] Calculate the average value of the reference units from the N / 2+1th to the Nth unit after the first unit under test to obtain the second average value;

[0011] The first operation value is obtained by calculating the first mean and the second mean using a constant false alarm rate (CFAR) detection algorithm.

[0012] Compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation;

[0013] The mean of the reference units from the (N+1)th to the 3N / 2th after the second unit under test is calculated to obtain the third mean, wherein the reference units from the (N / 2+1)th to the Nth after the first unit under test are located between the first unit under test and the second unit under test.

[0014] The second operation value is obtained by calculating the second mean and the third mean using a constant false alarm rate (CFAR) detection algorithm.

[0015] Compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the first tested unit and the value of the second operation.

[0016] In one embodiment, the constant false alarm rate (CFAR) detection algorithm is any one of the CA-CFAR detection algorithm, the CA-CFAR detection algorithm and the CA-CFAR detection algorithm.

[0017] In one embodiment, it also includes:

[0018] When the value of the first unit under test is greater than or equal to the value of the first operation, the first unit under test is determined to be the target unit.

[0019] When the value of the second unit under test is greater than or equal to the value of the second operation, the second unit under test is determined to be the target unit.

[0020] In one embodiment, the step of comparing the value of the first tested unit with the value of the first operation and outputting the comparison result of the value of the first tested unit and the value of the first operation includes:

[0021] Get the preset first coefficient;

[0022] Calculate the product of the first operation value and the preset first coefficient to obtain the first product value;

[0023] Compare the value of the first tested unit with the first product value, and output the comparison result of the value of the first tested unit and the first product value.

[0024] In one embodiment, the step of comparing the value of the second tested unit with the value of the second operation and outputting the comparison result of the value of the second tested unit and the value of the second operation includes:

[0025] Obtain the preset second coefficient;

[0026] Calculate the product of the second operation value and the preset second coefficient to obtain the second product value;

[0027] Compare the value of the second tested unit with the second product value, and output the comparison result of the value of the second tested unit and the second product value.

[0028] A radar signal processing system includes: a data reading module, a pulse compression module, a moving target display module, a moving target detection module, and a constant false alarm rate processing device;

[0029] The data reading module is used for radar baseband signal data, and combines the real and imaginary parts of the radar baseband signal data to form a radar IQ signal;

[0030] The pulse compression module is used to perform pulse compression on the radar IQ signal;

[0031] The moving target display module and the moving target detection module are respectively used to suppress stationary clutter in the radar IQ signal using clutter suppression filters;

[0032] The constant false alarm rate processing device is used to implement the steps of the method according to any one of claims 1 to 6;

[0033] The radar signal processing system is deployed on an x86 architecture computer device.

[0034] A constant false alarm rate (CFAR) processing device, comprising:

[0035] The first mean calculation unit is used to calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean;

[0036] The second mean calculation unit is used to calculate the mean of the N / 2+1 to Nth reference units after the first measured unit to obtain the second mean.

[0037] The first operation value calculation unit is used to calculate the first mean and the second mean using a constant false alarm rate (CFAR) detection algorithm to obtain the first operation value.

[0038] The first comparison unit is used to compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation;

[0039] The third mean calculation unit is used to calculate the mean of the N+1 to 3N / 2 reference units after the second tested unit to obtain the third mean, wherein the N / 2+1 to Nth reference units after the first tested unit are located between the first tested unit and the second tested unit.

[0040] The second operation value calculation unit is used to calculate the second mean and the third mean using a constant false alarm rate (CFAR) detection algorithm to obtain the second operation value.

[0041] The second comparison unit is used to compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the first tested unit and the value of the second operation.

[0042] A computer device includes a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the constant false alarm rate processing method described in any of the above embodiments.

[0043] A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the constant false alarm rate processing method described in any of the above embodiments.

[0044] A computer program, when executed by a processor, implements the constant false alarm rate processing method described in any of the above embodiments.

[0045] The aforementioned constant false alarm rate (CFAR) processing method, apparatus, computer equipment, and storage medium utilize a second mean in calculating the first operation value and also utilize the second mean in calculating the second operation value. This means that the second mean participates in both the calculation of the first and second operation values. For the second operation value, only the third mean needs to be calculated, saving the calculation process of the second mean. As a result, the calculation of each second operation value can save the corresponding calculation process, improving the calculation efficiency and thus effectively improving the calculation efficiency of the CFAR processing method. Attached Figure Description

[0046] Figure 1 This is a flowchart illustrating a constant false alarm rate (CFAR) processing method in one embodiment.

[0047] Figure 2 This is a structural block diagram of a constant false alarm rate processing device in one embodiment;

[0048] Figure 3This is an internal structural diagram of a computer device in one embodiment;

[0049] Figure 4A This is a schematic diagram illustrating the implementation principle of the traditional constant false alarm rate (CFAR) processing method.

[0050] Figure 4B This is a schematic diagram illustrating the implementation principle of the constant false alarm rate (CFAR) processing method in one embodiment.

[0051] Figure 5 This is a system block diagram of a radar signal processing system in one embodiment;

[0052] Figure 6 This diagram illustrates a comparison of the computation time between the traditional constant false alarm rate (CFAR) processing method and the CFAR processing method proposed in this application. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0054] Example 1

[0055] In this embodiment, as Figure 1 As shown, a constant false alarm rate processing method is provided, which includes:

[0056] Step 110: Calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean.

[0057] In this embodiment, please refer to Figure 4B The values ​​of the N / 2 reference units preceding the first tested unit D1 are x1, x2, x3...x N / 2 Then the first mean X is:

[0058]

[0059] Step 120: Calculate the average value of the N / 2+1 to Nth reference units after the first tested unit to obtain the second average value.

[0060] In this embodiment, the values ​​of the N / 2+1 to Nth reference units following the first tested unit D1 are x, respectively. N / 2+1 x N / 2+2 ...x N Then the second mean Y is:

[0061]

[0062] Step 130: The constant false alarm rate (CFAR) detection algorithm is used to calculate the first mean and the second mean to obtain the first operation value.

[0063] In this embodiment, the constant false alarm rate (CFAR) detection algorithm is used to calculate the first mean X and the second mean Y, thereby obtaining the first operation value O1.

[0064] In one embodiment, the constant false alarm rate (CFAR) detection algorithm is any one of the CA-CFAR detection algorithm, the CA-CFAR detection algorithm and the CA-CFAR detection algorithm.

[0065] Among them, the CA-constant false alarm rate detection algorithm takes the mean of (X, Y), so the CA-constant false alarm rate detection algorithm is CA:(X+Y) / 2; the SO-constant false alarm rate detection algorithm takes the minimum of (X, Y), so the SO-constant false alarm rate detection algorithm is SO:min(X,Y); and the GO-constant false alarm rate detection algorithm takes the maximum of (X, Y), so the GO-constant false alarm rate detection algorithm is GO:max(X,Y).

[0066] Step 140: Compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation.

[0067] In one embodiment, the step of comparing the value of the first tested unit with the value of the first operation and outputting the comparison result of the value of the first tested unit and the value of the first operation includes: obtaining a preset first coefficient; calculating the product of the first operation value and the preset first coefficient to obtain a first product value; comparing the value of the first tested unit with the first product value and outputting the comparison result of the value of the first tested unit and the first product value.

[0068] In this embodiment, as Figure 4B As shown, the preset first coefficient is α, which is a weighting coefficient. In this embodiment, the first operation value O1 is multiplied by α to obtain the first product value. The first product value is then compared with the value of the first measured unit D1 to obtain the comparison result.

[0069] In one embodiment, when the value of the first unit under test is greater than or equal to the value of the first operation, the first unit under test is determined to be a target unit and the first unit under test is determined to be a target; when the value of the first unit under test is less than the value of the first operation, the first unit under test is determined to be noise.

[0070] Step 150: Calculate the average value of the (N+1)th to (3N / 2)th reference units after the second tested unit to obtain the third average value, wherein the (N / 2+1)th to (N)th reference units after the first tested unit are located between the first tested unit and the second tested unit.

[0071] In this embodiment, the values ​​of the (N+1)th to the 3N / 2th reference units following the second measured unit D2 are x, respectively. N+1 x N+2 ...x 3N / 2 Then the third mean Z is:

[0072]

[0073] In this embodiment, there are N / 2 reference units between two adjacent test units. Specifically, there are N / 2 reference units in front of the first test unit D1, which are the 1st to the N / 2nd reference units; there are N / 2 reference units between the first test unit D1 and the second test unit D2, which are the N / 2+1st to the Nth reference units; and there are N / 2 reference units behind the second test unit D2, which are the N+1st to the 3N / 2nd reference units.

[0074] Step 160: The constant false alarm rate (CFAR) detection algorithm is used to calculate the second mean and the third mean to obtain the second operation value.

[0075] In this embodiment, the constant false alarm rate (CFAR) detection algorithm is used to calculate the second mean Y and the third mean Z, thereby obtaining the second operation value O2.

[0076] In one embodiment, the constant false alarm rate (CFAR) detection algorithm is any one of the CA-CFAR detection algorithm, the CA-CFAR detection algorithm and the CA-CFAR detection algorithm.

[0077] Among them, the CA-constant false alarm rate detection algorithm takes the mean of (Y, Z), so the CA-constant false alarm rate detection algorithm is CA:(Y+Z) / 2; the SO-constant false alarm rate detection algorithm takes the minimum of (Y, Z), so the SO-constant false alarm rate detection algorithm is SO:min(Y,Z); the GO-constant false alarm rate detection algorithm takes the maximum of (Y, Z), so the GO-constant false alarm rate detection algorithm is GO:maY(Y,Z).

[0078] Step 170: Compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the first tested unit and the value of the second operation.

[0079] In one embodiment, the step of comparing the value of the second tested unit with the value of the second operation and outputting the comparison result of the value of the second tested unit and the value of the second operation includes: obtaining a preset second coefficient; calculating the product of the second operation value and the preset second coefficient to obtain a second product value; comparing the value of the second tested unit with the second product value and outputting the comparison result of the value of the second tested unit and the second product value.

[0080] In one embodiment, the second coefficient may be equal to or different from the first coefficient. In one embodiment, such as Figure 4B As shown, the preset second coefficient is α, which is a weighting coefficient. In this embodiment, the second operation value O2 is multiplied by α to obtain the second product value. The second product value is then compared with the value of the second measured unit D2 to obtain the comparison result.

[0081] In one embodiment, when the value of the second unit under test is greater than or equal to the value of the second operation, the second unit under test is determined to be the target unit and the second unit under test is determined to be the target; when the value of the second unit under test is less than the value of the second operation, the second unit under test is determined to be noise.

[0082] In the above embodiments, the second mean is used when calculating the first operation value, and the second mean is also used when calculating the second operation value. This means that the second mean participates in both the calculation of the first operation value and the calculation of the second operation value. For the second operation value, only the third mean needs to be calculated, saving the calculation process of the second mean. As a result, the calculation of each second operation value can save the corresponding calculation process, improve the calculation efficiency, and thus effectively improve the calculation efficiency of the constant false alarm rate processing method.

[0083] Example 2

[0084] In this embodiment, as Figure 5 As shown, a radar signal processing system includes: a data acquisition module, a pulse compression module, a moving target display module, a moving target detection module, and a constant false alarm rate (CFAR) processing device. The data acquisition module is used to read radar baseband signal data and combine the real and imaginary parts of the radar baseband signal data to form a radar IQ signal. The pulse compression module is used to compress the radar IQ signal. The moving target display module and the moving target detection module are respectively used to suppress stationary clutter in the radar IQ signal using clutter suppression filters. The CFAR processing device is used in the steps of the CFAR processing method described in any of the above embodiments. The radar signal processing system is deployed on an x86 architecture computer device.

[0085] It should be understood that the excessively strong hardware-software coupling of traditional radar signal processing systems hinders radar upgrades and modifications. Currently, most radars fall into the category of digital radars. A typical characteristic of digital radars is the use of highly integrated digital devices with strong hardware-software coupling for signal processing system development. When a radar requires functional modifications, the entire hardware architecture (FPGA+DSP) needs to be redesigned and redeveloped at both the hardware and software levels, prolonging the radar's R&D process and significantly restricting upgrades. Furthermore, limited computing resources are another weakness; FPGAs and DSPs often need to each handle a portion of the functionality to complete the entire radar signal processing system, severely limiting the diversification of radar system functions. Additionally, data communication between the FPGA and DSP reduces system real-time performance.

[0086] In this embodiment, the radar signal processing system, based on an x86 architecture CPU processor, can perform a series of signal processing functions. From a computational resource perspective, it does not require decomposing functions across different heterogeneous platforms, avoiding data communication problems between heterogeneous platforms and enhancing the system's real-time performance to some extent. Furthermore, the CPU's development capabilities allow for rapid debugging of new functions within seconds to milliseconds, while the FPGA programming process can take hours at a time. Compared to the traditional FPGA+DSP architecture, the x86 architecture used in this embodiment significantly reduces system development time, enabling more efficient system development or optimization upgrades.

[0087] In this embodiment, the radar signal processing system hardware uses a cVPX6-D2183IT general-purpose computing blade with an Intel Xeon D-2183IT CPU processor based on the x86 architecture as its core. This processor supports up to 16 cores / 32 threads, meaning that up to 32 threads can run simultaneously in the signal processing system. A cVPX6-4SSD storage blade is also used to store the radar baseband data, with a maximum read / write speed of 4*3GBps. A 2U ruggedized shielded VPX chassis is used to protect the computing blade and storage blade. The CFAR runtime in the fast CFAR detection system provided in this application is only responsible for this computing platform. The hardware parameters of the aforementioned computing blade and storage blade are shown in Tables 1 and 2.

[0088] Table 1cVPX6-D2183IT General Calculation Blade

[0089] Memory 4-channel DDR4, 2133MT / s, 32GB / 64GB capacity Local storage 64GB onboard SSD chip + ruggedized storage daughter card External Interface 2-way 40GbE, 2-way sRIO x4, 4-way 1GbE, 2-way PCIe, 4-way SATA3.0 operating system Kylin Linux operating system Blade power consumption ≤150W

[0090] Table 2cVPX6-4SSD Storage Blade

[0091] VPX interface External output 4 PCIe 3.0 x4 lanes Storage capacity Standard configuration: 4*2TB, maximum support: 4*8TB Read / write bandwidth Up to 4*3GBps Blade power consumption ≤100W

[0092] In this embodiment, the radar signal processing system includes a data reading module, a pulse compression module, a moving target display module, a moving target detection module, and a CFAR detection module, wherein:

[0093] Data reading module: The data reading submodule reads the radar baseband signal data in the storage blade into the memory of the computing blade. At the same time, according to the data storage method, it combines the real part (I) and imaginary part (Q) of the signal to form a complete radar IQ signal.

[0094] Pulse Compression (PC) Module: Performs pulse compression on the read IQ signal to improve range resolution. To meet the dual requirements of detection range and range resolution, radar modulates signals, such as using linear frequency modulation (LFM). Pulse compression can improve the target signal-to-noise ratio in the received LFM signal.

[0095] Moving Target Indication (MTI) Module: The principle of MTI is to use clutter suppression filters to suppress stationary clutter, improving the signal-to-clutter ratio of the radar signal to facilitate the detection of moving targets. Taking ground clutter as an example, the frequency characteristics of ground clutter are usually concentrated near DC (Doppler frequency is 0), while moving targets often have Doppler frequencies that are not 0. MTI utilizes the difference in Doppler frequencies between clutter and moving targets, positioning its notch at the clutter frequency to achieve the effect of filtering clutter.

[0096] Moving Target Detection (MTD) Module: In this invention, MTD and MTI are cascaded. Both MTI and MTD use filters to remove clutter based on the target's frequency, but the two algorithms have different focuses, hence the cascading of them. MTD target detection is then performed on the MTI-filtered signal to eliminate some of the clutter's influence on the MTD algorithm and improve the output signal-to-noise ratio.

[0097] Constant False Alarm Rate (CFAR) Module: The purpose of CFAR processing is to maintain a constant false alarm rate during signal detection under interference, preventing the radar system from becoming overloaded due to excessive false alarms. The basic CFAR process involves estimating the noise and interference levels within the target detection unit, setting a threshold based on the estimate, and then comparing it with the detected unit to determine the presence of a target. Finally, the data is transmitted to the data processing system for point track convergence and other operations. Compared to traditional CFAR detection systems, the CFAR detection device used in this embodiment significantly reduces runtime by minimizing redundant calculations.

[0098] Traditional digital radar systems are developed using FPGA+DSP architecture for signal processing. This approach suffers from strong hardware-software coupling, as functions like analog-to-digital conversion and digital down-conversion are often performed on the FPGA. This means that adding or modifying radar functionality often requires a complete re-architecting of both hardware and software. In contrast, this application utilizes a signal processing system with an x86 architecture CPU as its core, offering greater flexibility, lower hardware-software coupling, and easier system upgrades.

[0099] The signal processing system based on the x86 architecture CPU features multi-core / threaded processing, significantly improving the real-time performance of radar signal processing. In this embodiment, the Intel Xeon D-2183IT processor supports up to 16 cores / 32 threads. Anti-asynchronous interference and MTD algorithms in the signal processing system require pulse accumulation, meaning multiple PRI data points need to be accumulated to complete the algorithm implementation. Compared to the single-threaded processing method of traditional radar signal processing systems, when the radar is processing high repetition rate (PRR) modes, tens of thousands of pulse data points can be generated within one second. In this embodiment, 16 threads are used simultaneously to process pulse data from 32 radar channels. With increasing demands on radar, only by adopting a higher-performance hardware architecture can the signal processing system meet the requirements of high performance and high real-time performance.

[0100] Example 3

[0101] This embodiment provides a constant false alarm rate (CFAR) detection implementation based on the concept of sparsity. It differs slightly from traditional CFAR implementations, but shares the same core idea. The main innovation lies in reducing redundant computations by optimizing the computational architecture, thereby reducing runtime. The implementation principle of sparse CFAR detection is as follows: Figure 4B As shown. Let the preceding distance cells be X1, X2, ..., X... N / 2 The mean of the output is X, and the distance between the middle units is X. N / 2+1 , ..., X N The mean of the output is Y. CA (Constant False Alarm Rate) detection takes the mean of (X, Y); SO (Constant False Alarm Rate) detection takes the minimum of (X, Y); and GO (Constant False Alarm Rate) detection takes the maximum of (X, Y). The operation on (X, Y) in these three algorithms is set to O1. O1*α is then compared with the detected unit D1 to obtain the target detection result for unit D1, where α is the weighting coefficient. The Y value is saved during the above operation process. Figure 4BAs can be seen, the Y value can participate in both the detection process of D1 and D2. Similarly, by using the Y value as the left-hand region decision for D2 and then calculating the right-hand region value Z of D2, the detection result of D2 can be obtained by repeating the detection process of D1. In the detection process of D2, only one summation calculation is performed on the right side, saving 50% of the calculation process for D2. Assuming X1 is the starting point of the data, all values ​​on the right side of D2 have achieved efficiency improvement. This property shows that under the method proposed in this innovation, the more detection points the constant false alarm rate (CFAR) detection has, the more time is saved and the higher the efficiency improvement.

[0102] like Figure 4A As shown, the traditional method of constant false alarm rate (CFAR) detection is to calculate the estimated level of interference within the sliding window by using a sliding window, multiply the estimated level by a weighting coefficient and compare it with that of the detected unit D, thereby making a decision on whether the detected unit exists or not. Figure 4A This describes the traditional implementation of constant false alarm rate (CFAR) detection. CA-CFAR calculates the average of the estimated levels from neighboring edges; SO-CFAR calculates the minimum of the estimated levels from neighboring edges; and GO-CFAR calculates the maximum of the estimated levels from neighboring edges. By statistically analyzing the estimated interference levels using various methods, multiplying them by weighting coefficients, and then comparing the results, the target detection is determined.

[0103] Compared to traditional CFAR implementations, the constant false alarm rate (CFAR) processing method in this embodiment reduces a significant amount of redundant calculations, thereby improving the real-time performance of the entire detection system. The implementation principle of traditional CFAR is as follows: Figure 4A As shown in the figure, D is the detected unit. CA-CFAR is calculated by averaging the values ​​of X and Y (Z) and comparing it with α*Z. If D ≥ α*Z, then D is the target; otherwise, it is noise. SO-CFAR differs in that it selects the minimum value of X and Y as Z. GO-CFAR selects the maximum value of X and Y as Z; the other processes are the same, the only difference being the rule for determining the Z value. The constant false alarm rate (CFAR) processing method proposed in this embodiment is based on the following principle: Figure 4B As shown, for detection unit D1, the detection method is the same as the traditional method, the difference being that this method saves the Y value of D1. From Figure 4B As can be seen, the Y value can be used to detect unit D2. By comparing Y with Z, the detection of D2 can be completed, which reduces the amount of computation by half for D2. Figure 6 To compare the runtime of traditional CFAR with that of CFAR in this embodiment, where traditional CFAR is CFAR2 and CFAR in this embodiment is CFAR1, the runtime of the two CFARs is compared under different computational loads. Figure 6 It can be seen that the more calculation points there are, the more time CFAR saves in this embodiment.

[0104] This embodiment proposes a CFAR detection algorithm that significantly reduces the repetitive calculations in the traditional CFAR traversal process, substantially reduces the CFAR runtime, and improves the real-time performance of the signal processing system. Many types of CFAR algorithms exist, such as CA-CFAR, GO-CFAR, and SO-CFAR, all of which can utilize the simplified traversal operation described in this invention, thereby improving algorithm speed.

[0105] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0106] Example 4

[0107] In this embodiment, as Figure 2 As shown, a constant false alarm rate processing device is provided, comprising:

[0108] The first mean calculation unit 210 is used to calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean;

[0109] The second mean calculation unit 220 is used to calculate the mean of the N / 2+1 to Nth reference units after the first measured unit to obtain the second mean;

[0110] The first operation value calculation unit 230 is used to calculate the first mean and the second mean using a constant false alarm rate (CFAR) detection algorithm to obtain the first operation value.

[0111] The first comparison unit 240 is used to compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation;

[0112] The third mean calculation unit 250 is used to calculate the mean of the N+1 to 3N / 2 reference units after the second tested unit to obtain the third mean, wherein the N / 2+1 to Nth reference units after the first tested unit are located between the first tested unit and the second tested unit.

[0113] The second operation value calculation unit 260 is used to calculate the second mean and the third mean using a constant false alarm rate (CFAR) detection algorithm to obtain the second operation value.

[0114] The second comparison unit 270 is used to compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the first tested unit and the value of the second operation.

[0115] Specific limitations regarding the constant false alarm rate (CFAR) processing device can be found in the limitations of the CFAR processing method described above, and will not be repeated here. Each unit in the aforementioned CFAR processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These units can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each unit.

[0116] Example 5

[0117] In this embodiment, a computer device is provided. Its internal structure diagram can be shown as follows: Figure 3 As shown, the computer device includes a processor, memory, network interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs, and is used to store radar signal data. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with other computer devices that have deployed application software. When the computer program is executed by the processor, it implements a constant false alarm rate (CFAR) processing method. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse.

[0118] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0119] In one embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the constant false alarm rate processing method described in any of the above embodiments.

[0120] Example 6

[0121] In this embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the constant false alarm rate processing method described in any of the above embodiments.

[0122] Example 7

[0123] In this embodiment, a computer program is provided, which, when executed by a processor, implements the constant false alarm rate processing method described in any of the above embodiments.

[0124] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A constant false alarm rate processing method, characterized by, include: Calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean; Calculate the average value of the reference units from the N / 2+1th to the Nth unit after the first unit under test to obtain the second average value; The first operation value is obtained by calculating the first mean and the second mean using a constant false alarm rate (CFAR) detection algorithm. Compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation; The mean of the reference units from the (N+1)th to the 3N / 2th after the second unit under test is calculated to obtain the third mean, wherein the reference units from the (N / 2+1)th to the Nth after the first unit under test are located between the first unit under test and the second unit under test. In the calculation process for the second tested unit, the already generated second mean is directly referenced, and the mean calculation is not re-executed for the N / 2+1 to Nth reference units; the constant false alarm rate (CFAR) detection algorithm is used to calculate the second mean and the third mean to obtain the second operation value; Compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the second tested unit and the value of the second operation.

2. The method of claim 1, wherein, The constant false alarm rate (CFAR) detection algorithm is any one of the CA-CFAR detection algorithm, GO-CFAR detection algorithm, and SO-CFAR detection algorithm.

3. The method according to claim 1, characterized in that, Also includes: When the value of the first unit under test is greater than or equal to the value of the first operation, the first unit under test is determined to be the target unit. When the value of the second unit under test is greater than or equal to the value of the second operation, the second unit under test is determined to be the target unit.

4. The method according to claim 1, characterized in that, The step of comparing the value of the first tested unit with the value of the first operation and outputting the comparison result of the value of the first tested unit and the value of the first operation includes: Get the preset first coefficient; Calculate the product of the first operation value and the preset first coefficient to obtain the first product value; Compare the value of the first tested unit with the first product value, and output the comparison result of the value of the first tested unit and the first product value.

5. The method according to claim 1, characterized in that, The step of comparing the value of the second tested unit with the value of the second operation and outputting the comparison result of the value of the second tested unit and the value of the second operation includes: Obtain the preset second coefficient; Calculate the product of the second operation value and the preset second coefficient to obtain the second product value; Compare the value of the second tested unit with the second product value, and output the comparison result of the value of the second tested unit and the second product value.

6. A radar signal processing system, characterized in that, include: Data reading module, pulse compression module, moving target display module, moving target detection module, and constant false alarm rate processing device; The data reading module is used for radar baseband signal data, combining the real and imaginary parts of the radar baseband signal data to form a radar IQ signal; The pulse compression module is used to perform pulse compression on the radar IQ signal; The moving target display module and the moving target detection module are respectively used to suppress stationary clutter in the radar IQ signal using clutter suppression filters; The constant false alarm rate processing device is used to implement the steps of the method according to any one of claims 1 to 5; The radar signal processing system is deployed on an x86 architecture computer device.

7. A constant false alarm rate processing device, characterized in that, include: The first mean calculation unit is used to calculate the mean of the first N / 2 reference units of the first tested unit to obtain the first mean; The second mean calculation unit is used to calculate the mean of the N / 2+1 to Nth reference units after the first measured unit to obtain the second mean. The first operation value calculation unit is used to calculate the first mean and the second mean using a constant false alarm rate (CFAR) detection algorithm to obtain the first operation value. The first comparison unit is used to compare the value of the first tested unit with the value of the first operation, and output the comparison result of the value of the first tested unit and the value of the first operation; The third mean calculation unit is used to calculate the mean of the N+1 to 3N / 2 reference units after the second tested unit to obtain the third mean, wherein the N / 2+1 to Nth reference units after the first tested unit are located between the first tested unit and the second tested unit. The second operation value calculation unit is used to directly reference the already generated second mean value during the calculation process for the second tested unit, without re-performing the mean calculation for the N / 2+1 to Nth reference units; and to calculate the second operation value by using a constant false alarm rate (CFAR) detection algorithm on the second mean value and the third mean value. The second comparison unit is used to compare the value of the second tested unit with the value of the second operation, and output the comparison result of the value of the first tested unit and the value of the second operation.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

10. A computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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