Data storage methods and computer equipment in analog computing

Abstract

This invention discloses a data storage method and computer device for analog computing, primarily addressing the problem of decreased accuracy in large-scale parallel computing due to factors such as line resistance and voltage drop in existing technologies. This invention utilizes the principle of linear superposition to transform the traditional reading process into a circuit configuration equivalent to the calculation process, thereby achieving coupling between the reading and calculation processes. This invention can reduce the impact of array-size-dependent non-ideal factors on the calculation process, improve calculation accuracy, overcome system aging, and can be applied to large-scale analog computing systems with in-memory computing capabilities.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and more specifically, relates to the architecture and operation of integrated circuit computing chips. Background Technology

[0002] With the development of the Internet of Things (IoT) and cloud computing, the complexity of computing tasks is increasing daily, putting greater pressure on computing chips. The main performance indicators of computing chips can be divided into power consumption and computing power. Whether in energy-constrained scenarios such as IoT or energy-intensive scenarios such as cloud computing, power consumption is crucial. Therefore, how to further reduce chip power consumption while providing a given computing power is an important research direction for computing chips.

[0003] The power consumption of computing chips mainly comes from two parts of operations: data read / write and data computation. For specific computations, such as inference and training computations involved in deep neural networks, a large number of data read / write operations occur. The target memory for data read / write can be divided into on-chip memory and off-chip memory. Since on-chip memory widely uses static random access memory (SRAM), its density is relatively low, and therefore its storage capacity is often small. When encountering a large number of data read / write operations, it is necessary to access off-chip memory. Examining data read / write operations, the charging and discharging of parasitic capacitances around interconnects is the main source of energy consumption. Off-chip memory accesses data through interconnects and pins with larger spacing, resulting in much higher energy consumption than on-chip memory. To address this phenomenon, deploying data in on-chip memory as much as possible and further reducing data access to on-chip memory are important strategies for optimizing the energy efficiency of computing chips.

[0004] In-memory computing architecture is one specific implementation of this. This architecture constructs high-density computing units based on memristors, allowing computational data to be partially embedded within these units, thus reducing data access operations. Simultaneously, due to its analog computing approach, it exhibits robustness to stored data, enabling larger-scale on-chip storage. A typical computation method involves inputting a voltage vector V to one side of a memristor array with conductance matrix G via a digital-to-analog converter (DAC), and measuring the output current vector I on the orthogonal other side to perform a matrix-vector multiplication calculation of I = GV. In the context of neural network inference, G corresponds to the network weights and is updated less frequently, while V corresponds to the feature map of the data and is updated more frequently.

[0005] During the aforementioned calculation process, the large number of cells activated during parallel computation generates significant current and creates voltage drops on the interconnects. This alters the voltage across the memory devices, causing a deviation between the actual calculation results and the theoretical linear calculation. This deviation increases further as the array size increases, thus limiting further increases in computational parallelism. Summary of the Invention

[0006] The purpose of this invention is to solve the above-mentioned problems and to propose a data storage method and computer device for simulation computing.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] Firstly, a data storage method for simulation computing is provided.

[0009] A memory that uses memory cells arranged in an array structure, wherein the memory cells contain selectable memory structures;

[0010] The memory's storage units are divided into blocks, so that the data within a single block can be used to implement a specific calculation process;

[0011] Based on the memory and its block relationship, iterative writing is implemented for at least one target storage unit that needs to be written to, in the following manner.

[0012] The iterative data reading process includes,

[0013] First, select the storage structure of all storage units in the block to which the target storage unit belongs.

[0014] Then, a read signal is applied to the target storage cell.

[0015] Then, apply a zero signal to all storage cells in the block to which the target storage cell belongs, excluding the target storage cell.

[0016] Furthermore, the iterative writing process includes:

[0017] First, data is written to the memory according to the target storage value; this is referred to as step one.

[0018] The memory is then read to obtain the simulated stored value, which is denoted as step two.

[0019] Then, based on the target stored value and the simulated stored value, repeat steps one and two until the difference between the target stored value and the simulated stored value is less than a preset value, thus completing the data storage.

[0020] Furthermore, in the memory, each storage cell has at least two stable states, and the states remain consistent across multiple writes.

[0021] Furthermore, the memory uses a magnetic tunnel junction or static random access memory as the information storage medium.

[0022] Furthermore, the memory includes one or more of the following: resistive switching memory, phase change memory, ferroelectric memory, dynamic random access memory, floating gate memory, and charge trapping memory.

[0023] Furthermore,

[0024] The memory array includes excitation lines and sampling lines, wherein the excitation lines provide signal input and the sampling lines provide signal output;

[0025] Any target memory cell can form a read loop by a certain excitation line and a certain sampling line;

[0026] The read signal excitation is a read current input, applied to the excitation line corresponding to the target memory cell, while the excitation line corresponding to the memory cell to which the zero signal is applied is left floating.

[0027] In this case, the calculation process within a single block is as follows:

[0028] Step 1: Set the sampling line within the block to the same zero potential as the excitation line;

[0029] Step 2: Apply an excitation current related to the data to be calculated to the excitation line within the block;

[0030] Step 3: Perform current sampling on the sampling lines within the block;

[0031] The order of steps is as follows: step two precedes step three, and step one precedes step three.

[0032] Furthermore,

[0033] The memory array includes excitation lines and sampling lines, wherein the excitation lines provide signal input and the sampling lines provide signal output;

[0034] Any target memory cell can form a read loop by a certain excitation line and a certain sampling line;

[0035] The read signal excitation is a read voltage input, applied to the excitation line corresponding to the target memory cell, and the excitation line corresponding to the memory cell to which the zero signal is applied is short-circuited to ground.

[0036] In this case, the calculation process within a single block is as follows:

[0037] Step 1: Set the sampling line within the block to the same zero potential as the excitation line;

[0038] Step 2: Apply an excitation voltage related to the data to be calculated to the excitation line within the block;

[0039] Step 3: Perform current sampling on the sampling lines within the block;

[0040] The order of steps is as follows: step two precedes step three, and step one precedes step three.

[0041] Furthermore, the iterative writing process is repeated at regular intervals during memory usage.

[0042] In a second aspect, a computer device is provided, including a memory with computing capabilities, the memory being able to perform the steps of the data storage method as described in the first aspect.

[0043] The beneficial effect of this invention is that by including array parasites such as line resistance voltage drop during the reading process, the accuracy of in-memory parallel computing can be improved.

[0044] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and looking at the accompanying drawings. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This demonstrates a typical in-memory computing simulation method;

[0047] Figure 2 A memory system is shown;

[0048] Figure 3 A specific implementation of a voltage-input 2x3 memory system is shown;

[0049] Figure 4 A flowchart of the read / write verification process is shown;

[0050] Figure 5 A concrete implementation of a 2x3 memory system with current input is shown;

[0051] Figure 6 A memory cell using transistor gating is shown;

[0052] Figure 7 A structure based on a charge memory is shown;

[0053] Figure 8 An architecture based on static random access memory is shown;

[0054] Figure 9A structure based on dynamic random access memory is shown. Detailed Implementation

[0055] In the following detailed description, reference is made to the accompanying drawings, which form part of this invention, wherein specific embodiments in which the invention may be practiced are illustrated by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. For example, features shown or described for one embodiment may be used or combined with other embodiments to produce yet another embodiment. It is intended that the invention include these modifications and variations. Embodiments are described using specific language (which should not be construed as limiting the scope of the appended claims). The drawings are not drawn to scale and are for illustrative purposes only.

[0056] The technical problem that this invention aims to solve is to reduce the computational errors introduced by factors such as line resistance voltage drop during large-scale parallel computing in in-memory computing architecture.

[0057] like Figure 1 As shown, a typical in-memory computing analog computing method is to input the voltage vector V through the bit lines 101 and 102 via a digital-to-analog converter (DAC) on one side of the memristor array with a conductance value of matrix G, and output the current vector I by measuring the source lines 111 and 112 on the other side, which are orthogonal, thus realizing the matrix-vector multiplication calculation of I = GV.

[0058] In the above calculations, the large number of cells turned on during parallel computing generates a significant current and a voltage drop on the interconnects. This causes a change in the voltage across the memory device, resulting in a deviation between the actual calculation results and the theoretical linear calculation. Specifically, considering factors such as read speed, the common memory read current is approximately 10-100 μA. For megabyte (MB) memory arrays, the interconnect resistance is approximately 100-1000 Ω. When 1000 cells on the same source line are turned on simultaneously, assuming all memory cells have a current of 10 μA, a simple estimate shows that, since all memory cells share the source line, the current on the source line will be aggregated, potentially reaching a maximum of 10 mA. Assuming a source line resistance of 100 Ω, this current will cause a voltage drop of approximately 1 V, which is clearly inconsistent because it contradicts the assumption that the source line voltage is 0. In fact, the voltage drop caused by the current significantly reduces the voltage across the memory cells, thus reducing the overall current. Therefore, when a large number of cells are turned on, the source line current value will deviate significantly from the above I=GV.

[0059] like Figure 2 As shown, a storage system includes an excitation circuit 201, a memory 202, a sampling circuit 204, and a control circuit 203. Figure 3As shown, the excitation circuit may include a voltage digital-to-analog converter, the memory bits, i.e., storage cells, may be a series connection of a storage structure and a gating structure, and the sampling circuit may include a current analog-to-digital converter.

[0060] To achieve accurate calculations, the accuracy of the data stored in the memory cells, under the metrics defined by the excitation circuit 201 and the sampling circuit 204, is achieved as follows. Taking a portion of memory region 326 as an example, operations need to be performed on memory bits 320, 330, 350, and 360. For the block-based process, taking matrix calculation as an example, data within the same matrix forms a block. This is illustrated using memory bit 320 as an example; different bits can be operated on sequentially or simultaneously. For example... Figure 4 As shown, memory bit metadata is written using a read-write loop. Specifically, for a given input to the excitation circuit 201, the current state of the memory 202 can be used to obtain an actual sampled value, i.e., the analog stored value Y, in the sampling circuit 204. For a given input to the excitation circuit 201, the target state of the memory 202 can be used to calculate the theoretical sampled value of the sampling circuit, i.e., the target stored value X. Optionally, the state of the memory cell can be modified by applying a write excitation based on the difference between the actual sampled value and the theoretical sampled value. Figure 4 As shown, steps 401, 402, 403, and 404 are repeated until the difference between the actual sampled value and the theoretical sampled value is less than a predetermined threshold Δ.

[0061] In traditional implementations, memory bit reads only select the bits that need to be written. For example, when reading memory bit 320, the operation involves inputting an enable signal on word line 381 and a disable signal on word line 382, ​​thus enabling only selectable structures 322 and 332. Simultaneously, a read voltage is input on source line 303, and a zero signal is input on source line 304, setting bit lines 391 and 393 to the read voltage, and setting bit line 392 to zero potential. The signal from bit line 392 is then input to a sensitive amplifier or other sampling circuit for signal reading. In this traditional implementation, only information from a single memory bit 320 is obtained, without considering the line resistance voltage drop factor during calculation. Consequently, when this corrected memory bit is used for computation, deviations will occur due to the line resistance voltage drop.

[0062] The innovation of this invention lies in using a gating state that matches the calculation process during the reading process. For example, when reading memory bit 320, the operation involves inputting enable signals to word lines 381 and 382, ​​thereby turning on all gating structures. Simultaneously, a read voltage is input to the excitation line, i.e., source line 303, source line 304 is shorted to ground, bit lines 391, 392, and 393 are all set to zero potential, and the signal of 392 is input to a sensitive amplifier or other sampling circuit for signal reading. In this process, the line resistance voltage drop is included in the read signal. According to the principle of circuit superposition, the input state during calculation can be obtained by linearly superimposing the input signals. Therefore, the result obtained by the calculation process will match the memory data, without deviations from array factors such as line resistance voltage drop.

[0063] like Figure 5 As shown, in at least one embodiment, the input can be a current input. For example, when reading memory bit 520, the operation involves inputting enable signals to word lines 581 and 582, thereby turning on all gating structures. Simultaneously, a read current is input to source line 503, source line 504 is left floating, bit lines 591, 592, and 593 are all set to zero potential, and the signal from 592 is input to a sensitive amplifier or other sampling circuit for signal reading.

[0064] like Figure 6 As shown, in at least one embodiment, the memory structure can be selected using a transistor. This transistor can also be shared among multiple memory structures. This memory structure can be a two-terminal magnetic tunneling junction, a two-terminal resistive switching memory, or a two-terminal phase-change memory, or a two-terminal structure in a multi-terminal device.

[0065] like Figure 7 As shown, in at least one embodiment, the memory structure can use transistors with storage capabilities for gating and storage. Floating-gate memories, single-transistor ferroelectric memories, and charge-trapping memories all belong to this category.

[0066] like Figure 8 As shown, in at least one embodiment, the storage structure can use the storage structure 811 of a static random access memory.

[0067] This storage structure can provide a stable voltage to control the switching of transistors, thereby configuring the resistance between the input and output ports of the computing array.

[0068] like Figure 9 As shown, in at least one embodiment, the storage structure can use the storage structure 911 of dynamic random access memory.

[0069] This memory structure can provide a stable voltage to control the switching of transistors, thereby configuring the resistance between the input and output ports of the computing array. The capacitors in memory structure 911 can be non-volatile structures based on ferroelectric materials, thus avoiding repeated data refresh processes.

[0070] In at least one embodiment, the write process can be run repeatedly throughout the lifecycle of the storage system to correct for aging phenomena accumulated or generated during use, such as interconnect wire electromigration, memory data disturbance, and memory data loss.

[0071] In addition, this application also proposes a computer device including a memory with computing functions, the memory being capable of executing the steps in the data storage method described above.

[0072] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0073] The above description is merely a preferred embodiment of the present invention. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall still fall within the protection scope of the technical solutions of the present invention.

Claims

1. A data storage method in simulation computing, characterized in that: A memory that uses memory cells arranged in an array structure, wherein the memory cells contain selectable memory structures; The memory's storage units are divided into blocks, so that the data within a single block can be used to implement the matrix-vector multiplication calculation process in neural network inference computation; Based on the memory and its block relationship, iterative writing is implemented for at least one target storage unit that needs to be written to, in the following manner. The iterative data reading process includes, First, select the storage structure of all storage units in the block to which the target storage unit belongs. Then, a read signal is applied to the target storage cell. Then apply a zero signal to all memory cells in the block to which the target memory cell belongs, excluding the target memory cell itself; The iterative writing process includes, First, data is written to the memory according to the target storage value; this is referred to as step one. The memory is then read to obtain the simulated stored value, which is denoted as step two. Then, based on the target stored value and the simulated stored value, repeat steps one and two until the difference between the target stored value and the simulated stored value is less than a preset value, thus completing the data storage. The memory array includes excitation lines and sampling lines, wherein the excitation lines provide signal input and the sampling lines provide signal output; Any target memory cell can form a read loop by a certain excitation line and a certain sampling line; The read signal excitation is a read current input, applied to the excitation line corresponding to the target memory cell, and the excitation line corresponding to the memory cell to which the zero signal is applied is left floating; The calculation process within a single block is as follows. Step 1: Set the sampling line within the block to the same zero potential as the excitation line; Step 2: Apply an excitation current related to the data to be calculated to the excitation line within the block; Step 3: Perform current sampling on the sampling lines within the block; The order of steps is as follows: step two precedes step three, and step one precedes step three.

2. The data storage method according to claim 1, characterized in that, In the memory, each storage cell has at least two stable states, and the states remain consistent across multiple writes.

3. The data storage method according to claim 2, characterized in that, The memory uses magnetic tunneling junctions or static random access memory as the information storage medium.

4. The data storage method according to claim 1, characterized in that, The memory includes one or more of the following: resistive random access memory, phase change memory, ferroelectric memory, dynamic random access memory, floating gate memory, and charge trapping memory.

5. The data storage method according to any one of claims 1-4, characterized in that, The memory array includes excitation lines and sampling lines, wherein the excitation lines provide signal input and the sampling lines provide signal output; Any target memory cell can form a read loop by a certain excitation line and a certain sampling line; The read signal excitation is a read voltage input, applied to the excitation line corresponding to the target memory cell, and the excitation line corresponding to the memory cell to which the zero signal is applied is short-circuited to ground.

6. The data storage method according to claim 5, characterized in that, The calculation process within a single block is as follows. Step 1: Set the sampling line within the block to the same zero potential as the excitation line; Step 2: Apply an excitation voltage related to the data to be calculated to the excitation line within the block; Step 3: Perform current sampling on the sampling lines within the block; The order of steps is as follows: step two precedes step three, and step one precedes step three.

7. The data storage method according to claim 1, characterized in that, The iterative writing process is repeated at regular intervals during memory usage.

8. A computer device comprising a memory having computing capabilities, the memory being capable of performing the steps of the data storage method as claimed in any one of claims 1-6.

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