A combined encoding method for content addressable memory

Abstract

The application provides a combined encoding method of content addressable memory, and belongs to the technical field of novel storage and calculation.The combined encoding method of the configurable multi-feature content addressable memory based on the nonvolatile memory has the core of combining and encoding a plurality of nonvolatile memory devices as a group.Compared with the traditional implementation mode of storing complementary information representing 1-bit entry information by two nonvolatile memory devices, the encoding efficiency is improved, that is, more entry states are encoded by the same number of memory devices.The application can not only improve the encoding efficiency of the CAM based on the nonvolatile memory, but also can configure the feature number of the CAM according to the actual demand, so that the CAM can be more flexibly used in different search systems, and the higher search speed and energy efficiency can be brought.

Description

Technical Field

[0001] This invention relates to the field of novel storage and computing technologies, specifically to a combined encoding method for implementing configurable multi-feature content addressable memory based on non-volatile memory. Background Technology

[0002] Content-addressable memory (CAM) can perform search operations efficiently and in parallel, and is widely used in network routers for packet forwarding and classification-related table lookup operations, data caching, database searches, and other applications. CAM is a special type of memory used for parallel searches; in addition to the read and write operations of conventional memory, it can perform unique search operations. CAM can complete a search operation on the entire storage array within one clock cycle, resulting in a significant speedup compared to other hardware- or software-based search systems, and has been successfully commercialized in modern routers. With the advent of the era of the Internet of Things, the number of Internet Protocol (IP) addresses has grown exponentially, transitioning from the 32-bit address length of Internet Protocol version 4 (IPv4) to the 128-bit address length of Internet Protocol version 6 (IPv6). The increase in data volume has placed higher demands on the storage density, speed, and energy efficiency of CAM. In the era of big data, due to its ability to achieve high-speed parallel search operations, CAM applications in machine learning, image processing, DNA sequencing, and biomedicine have been extensively researched and explored. Its main difference from traditional routing lookup table applications is that the features of each dimension are not limited to just two states, 0 and 1. For example, DNA sequencing has 4 base types and protein detection has 20 amino acid types, which poses new requirements for the feature expansion of the CAM dimension.

[0003] CAM designs based on traditional Static Random Access Memory (SRAM) occupy a huge cell area. With the slowdown in Moore's Law, it's difficult to increase density by further shrinking device size, and the resulting large parasitic capacitance further increases search latency and power consumption. CAM designs based on various non-volatile memories, such as Resistive Random Access Memory (RRAM), Phase-Change Memory (PCM), Ferroelectric Field-Effect Transistors (FeFETs), and Flash Memory, offer reduced cell area, search latency, and power consumption. However, current CAM designs based on non-volatile memories mainly follow the implementation method based on traditional SRAM. This involves replacing a single SRAM cell with two complementary memory nodes with two non-volatile memory cells storing complementary information to represent an entry, and combining complementary inputs to achieve a linearly inseparable comparison operation between a 1-bit binary input query and the stored entry. However, this encoding method is wasteful of non-volatile memory, inevitably limiting further improvements in CAM density and energy efficiency. Furthermore, when expanding dimensional features for applications requiring multi-feature CAMs, such as DNA sequencing and protein detection, it can only be done bit-by-bit in binary form, further wasting hardware resources. Therefore, combining the characteristics of non-volatile memory with more effective and configurable encoding designs tailored to different application needs is crucial for improving the performance of configurable multi-feature CAM search systems based on non-volatile memory. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention proposes a combinatorial encoding method based on non-volatile memory to implement configurable multi-feature content addressable memory. This invention breaks through the encoding method of CAM based on traditional SRAM and adopts an optimized configurable combinatorial encoding method, which can not only improve the encoding efficiency of CAM based on non-volatile memory, but also configure the number of features of CAM according to actual needs, making it more flexible for use in different search systems, and correspondingly bringing higher search speed and energy efficiency.

[0005] The technical solution of the present invention is as follows:

[0006] A combined encoding method for content-addressable memory, characterized in that,

[0007] 1) The configurable multi-feature CAM array based on non-volatile memory devices adopts a conventional NOR type memory array. Each memory cell can be a 1T1R structure consisting of a field-effect transistor connected in series with an RRAM or PCM, or a 1F structure consisting of a FeFET or Flash. The gate of the field-effect transistor in the 1T1R or the 1F is the search line (SL), and each column of the CAM array shares one SL; the drain of the field-effect transistor in the 1T1R or the 1F is the matching line (ML), and each row of the CAM array shares one ML; one end of the RRAM or PCM in the 1T1R is connected to the source of the field-effect transistor, and the other end is grounded, and the source of the 1F is grounded.

[0008] 2) Each non-volatile memory device can store data "0" or "1", where "0" corresponds to the low-resistivity state of RRAM / PCM or the low-threshold state of FeFET / Flash, and "1" represents the high-configuration state of RRAM / PCM or the high-threshold state of FeFET / Flash. When storing entry information, based on the number of features K required by the CAM, N memory devices are grouped together for encoding. If N is even, N / 2 devices are randomly selected and programmed as data "0", and the remaining N / 2 devices are programmed as data "1". If N is odd, (N-1) / 2 devices are randomly selected and programmed as data "0", and the remaining (N+1) / 2 devices are programmed as data "1". Each programming method represents an entry state, so the number of entry states that N memory devices can represent is: (N is an even number) or (N is odd). The choice of N is such that... (N is an even number) or (N is an odd number) The smallest N greater than K. The encoding method of the search query corresponds to the encoding method of the storage entry, that is, the N inputs are "0" and "1", where "0" represents a low input voltage and "1" represents a high input voltage. Similarly, the positions of "0" and "1" in the search query and the storage entry are the same. In addition, when all N storage devices are stored as "1", it means that the multi-feature CAM matches any input feature, denoted by entry "X"; similarly, when all N inputs are "0", it means that the input feature matches any stored feature, denoted by query "X".

[0009] 3) During the search operation, the voltage of ML is first pre-charged to a high level. Then, a voltage signal consistent with the search query is applied to SL. For arrays based on RRAM or PCM, the field-effect transistors acting on the low-voltage SL are in the off state, and the field-effect transistors acting on the high-voltage SL are in the on state. Only when the storage entry is the same as the search query will all the RRAM or PCM connected to the on field-effect transistors be in the high-impedance state, and the high level of ML can be maintained. Otherwise, there will be at least one on field-effect transistor connected to the low-impedance state, causing ML to discharge to a low level quickly. For 1F arrays based on FeFET or Flash, only when the storage entry is the same as the search query will the low-voltage SL act on the low-threshold state of 1F, and the high-voltage SL act on the high-threshold state of 1F, that is, all of 1F will be in the off state, so that ML will be kept at a high level. Otherwise, there will be at least one high-voltage SL acting on the low-threshold state of 1F, causing ML to discharge to a low level through the on-state 1F. Therefore, the pre-filled ML can only remain high, indicating a match, when the search query matches the stored entry; otherwise, the ML will drop to low, indicating a mismatch.

[0010] 4) The configurable combination encoding method proposed in this invention can not only expand the number of features in CAM, but also further expand the number of dimensions for combination encoding. If the entry dimension to be stored is W and the feature of each dimension is K, then the smallest N that makes formula (1) hold can be taken, that is, W / n K feature entries are implemented in a group of N storage devices. Through bit expansion, the entry storage of dimension W is further implemented in n groups. When n=1, the corresponding largest N is... max That is, with N max Each storage device can be grouped together to achieve storage of K feature entries with dimension W.

[0011]

[0012] In summary, this invention proposes a combined encoding method for implementing configurable multi-feature content addressable memory based on non-volatile memory. The non-volatile memory device can be various types of non-volatile two-terminal resistive random access memory such as RRAM or PCM, or it can be FeFET or Flash. The ferroelectric material can be various HfO2-doped ferroelectric materials such as HfO2-doped Zr (HZO) or HfO2-doped Al (HfAlO), or it can be traditional ferroelectric materials such as perovskite ferroelectric materials (such as PZT, BFO, SBT, etc.) or ferroelectric polymers (such as P(VDF-TrFE) etc.). The device gate stack can be based on various structures such as MFMIS, MFIS, and MFS.

[0013] The technical effects of this invention are as follows:

[0014] 1. The present invention proposes a combined encoding method based on non-volatile memory to implement configurable multi-feature content addressable memory. It combines multiple non-volatile memory devices into a group for encoding. Compared with the traditional implementation method of storing complementary information in two non-volatile memory devices to represent 1 bit of entry information, it improves the encoding efficiency. That is, it encodes more entry states with the same number of memory devices, which can further improve the storage density of CAM based on emerging non-volatile memory.

[0015] 2. The combined encoding method of configurable multi-feature content addressable memory based on non-volatile memory proposed in this invention reduces the number of storage devices required to store entries of the same dimension and features, reduces the total capacitance of ML, and significantly reduces search latency and search power consumption.

[0016] 3. The combined encoding method proposed in this invention, which is based on non-volatile memory to implement configurable multi-feature content addressable memory, can flexibly configure the number of combined encodings N according to application requirements. It can be used to combine and encode the number of features required for CAM, or to further combine and encode multi-dimensional CAM, making it flexible in application. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the array structure and storage cell structure of the combined encoding method based on non-volatile memory to realize configurable multi-feature content addressable memory proposed in this invention;

[0018] Figure 2 This is a schematic diagram illustrating the specific implementation principle of the combined encoding method based on non-volatile memory to implement configurable multi-feature content addressable memory proposed in this invention, taking groups of 3 and 4 memory devices as examples for combined encoding. Detailed Implementation

[0019] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0020] The array structure and memory cell structure diagram of the combined encoding method based on non-volatile memory to implement configurable multi-feature content addressable memory proposed in this invention are shown below. Figure 1As shown, the CAM array based on non-volatile memory devices adopts a conventional NOR type memory array. Each memory cell can be a 1T1R structure composed of a field-effect transistor connected in series with an RRAM or PCM, or a 1F structure composed of a FeFET or Flash. Each row of the CAM array shares one ML, and each column shares one SL. During the search operation, the ML of each row is first charged to a high level through the pre-charge circuit. Then, according to the search query, the corresponding search voltage is applied to the SL of each column, and the search operation of the entire CAM array is completed in parallel. Only the ML corresponding to the entry that stores the search query will remain at a high level during the search process, indicating a match; the ML corresponding to the row that does not match the search query will drop to a low level during the search process.

[0021] Figure 2 This embodiment illustrates the specific implementation principle of a combined encoding method for a configurable multi-feature content addressable memory based on non-volatile memory, using groups of 3 and 4 memory devices as examples. With 3 memory devices as a group, one memory device is arbitrarily selected and programmed as "1", corresponding to a low-impedance state of RRAM / PCM or a high-threshold state of FeFET / Flash; the other two memory devices are programmed as "0", corresponding to a high-impedance state of RRAM / PCM or a low-threshold state of FeFET / Flash. This results in three different combined encoding methods, representing storage entries "0" to "2", thus enabling a CAM with three features. The encoding method for the search query is consistent with that of the storage entries: two inputs are "0", indicating that SL is applied low during the search, and the other input is "1", indicating that SL is applied high during the search. If all three memory devices are programmed as "1" to store entry "X", it means that any input matches; if all three inputs are "0", it means that input "X" matches any storage entry. If four storage devices are grouped together, and any two are programmed as "1" and the other two as "0", then entries "0" to "5" can be stored. This can be used for CAMs with 4, 5, or 6 feature numbers. Figure 2It can be seen that the high-level SL only applies to the storage state "1" of the memory device when the search query and the storage entry are consistent. For the 1T1R structure, the memory device connected to the conducting transistor is in a high-impedance state, while for the 1F structure, the 1F in the high-threshold state is in the off state. When two low-level SLs apply to the storage state "0" of the memory device, either the field-effect transistor in the 1T1R structure or 1F is turned off. Therefore, during the search process, ML remains high, indicating a match. If the search query and the storage entry are inconsistent, at least one high-level SL applies to the storage state "0" of the memory device, causing the conducting field-effect transistor in the 1T1R structure to connect to a low-impedance memory device or turning on the 1F in the low-threshold state. In this case, ML will discharge to a low level during the search process through the low-impedance RRAM or PCM, or through the conducting 1F, indicating a mismatch. For dimensional expansion of combined encoding, expansion can be achieved by increasing the number of storage units in a group of combined encodings and by connecting multiple combined encoding storage units in parallel. Only when all combined encoding storage unit combinations in a row are matched can ML remain high during the search process. If any combination has any mismatch, ML will drop to low during the search process, indicating that this encoding method enables CAM based on non-volatile memory to work correctly.

[0022] This embodiment fully and in detail describes a combined encoding method for implementing configurable multi-feature content addressable memory based on non-volatile memory. Compared with the current encoding method of traditional SRAM-based CAM, the encoding method proposed in this invention improves the encoding efficiency and encoding flexibility for multi-feature CAM, thereby improving the search speed and energy efficiency of CAM arrays of the same size.

[0023] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A combined encoding method for content addressable memory, characterized by, Includes the following steps: 1) The CAM array adopts a conventional NOR type memory array. Each memory cell is a 1T1R structure composed of a field-effect transistor connected in series with an RRAM or PCM, or a 1F structure composed of a FeFET or Flash. Each column of the CAM array shares a search line SL, and each row of the CAM array shares a matching line ML. 2) Each memory cell stores either "0" or "1", where "0" corresponds to the low-resistivity state of RRAM / PCM or the low-threshold state of FeFET / Flash, and "1" represents the high-resistivity state of RRAM / PCM or the high-threshold state of FeFET / Flash. When storing entry information, based on the number of features K required by the CAM, N memory cells are grouped together for encoding. If N is even, N / 2 of the N memory cells are randomly selected and programmed as data "0", and the remaining N / 2 memory cells are programmed as data "1". If N is odd, (N-1) / 2 of the N memory cells are randomly selected and programmed as data "0", and the remaining (N+1) / 2 memory cells are programmed as data "1". Each programming method represents an entry state. Therefore, when N is even, the number of entry states represented by N memory cells is: When N is odd, the number of entry states represented by N storage units is: The or The smallest N greater than K; 3) The encoding method of the search query corresponds to the encoding method of the storage entry. That is, the N inputs are "0" and "1", where "0" represents a low voltage input and "1" represents a high voltage input. Similarly, the positions of "0" and "1" in the search query and the storage entry are the same. When all N storage units are stored as "1", it means that the multi-feature CAM matches any input feature, denoted by entry "X". Similarly, when all N inputs are "0", it means that the input feature matches any stored feature, denoted by query "X". 4) During the search operation, the voltage of ML is pre-charged to a high level, and then a voltage signal consistent with the search query is applied to SL. Only when the search query matches the stored entry can the pre-charged ML maintain a high level, indicating a match; otherwise, ML will drop to a low level, indicating a mismatch. If we want to store entries with dimension W and features K for each dimension, and use n groups to store entries of dimension W, then we use formula (1) to calculate the minimum N, that is, to use N storage units as a group to implement W / n K feature entries. (1) 。 2. The combinational encoding method for content-addressable memory as described in claim 1, characterized in that, The gate of the field-effect transistor or 1F in the 1T1R is the search line SL, the drain of the field-effect transistor or 1F in the 1T1R is the matching line ML, one end of the RRAM or PCM in the 1T1R is connected to the source of the field-effect transistor and the other end is grounded, and the source of the 1F is grounded.

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