Test method and device of storage chip, storage medium and electronic equipment

Abstract

The present disclosure provides a test method of a storage chip, a test device of a storage chip, a computer readable storage medium and an electronic device, and belongs to the technical field of semiconductors. The method comprises: writing test data into a storage unit of the storage chip based on a target write timing parameter of the storage chip, and reading stored data from the storage unit based on a target read timing parameter of the storage chip; determining a test result of the storage chip according to the test data and the stored data; wherein the test data comprises a plurality of different binary sequences, and only one data bit in each binary sequence is 1, the target write timing parameter is less than a standard write timing parameter of the storage chip, and the target read timing parameter is less than a standard read timing parameter of the storage chip. The present disclosure can improve the test efficiency and accuracy of the storage chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for testing memory chips, a testing apparatus for memory chips, a computer-readable storage medium, and an electronic device. Background Technology

[0002] As an important component of digital chips, memory chips can store programs and various data, and can complete the access of programs or data at high speed and automatically during computer operation.

[0003] Before memory chips are put into application, technicians often need to test them to verify their performance. Current testing methods for memory chips determine their performance by traversing each memory cell on the chip and performing read and write operations on each cell according to corresponding read and write rules. However, this method requires the testing time to meet the write, read, communication, and programming times of each memory cell. To complete the testing of each memory cell, the testing time is often longer than the actual testing time required. In mass production testing, the testing process is extremely time-consuming, resulting in low testing efficiency and making it difficult to meet the production requirements of memory chips.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a testing method for memory chips, a testing apparatus for memory chips, a computer-readable storage medium, and an electronic device, thereby improving, to at least some extent, the problem of low testing efficiency of memory chips in the prior art.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to a first aspect of this disclosure, a testing method for a memory chip is provided, the method comprising: writing test data into a memory cell of the memory chip based on a target write timing parameter of the memory chip, and reading stored data from the memory cell based on a target read timing parameter of the memory chip; determining a test result of the memory chip based on the test data and the stored data; wherein the test data includes multiple different binary sequences, and each binary sequence has one and only one data bit that is 1, the target write timing parameter is less than the standard write timing parameter of the memory chip, and the target read timing parameter is less than the standard read timing parameter of the memory chip.

[0008] In one exemplary embodiment of this disclosure, the test data is written to each row of storage cells of the storage chip by traversal access, and the stored data is read from each row of storage cells of the storage chip.

[0009] In one exemplary embodiment of this disclosure, the method further includes: writing the test data into any row of storage cells of the storage chip within a row detection cycle, and reading storage data from the any row of storage cells; and determining the test result of the any row of storage cells based on the test data written into the any row of storage cells and the storage data read from the any row of storage cells.

[0010] In one exemplary embodiment of this disclosure, the method further includes: writing the test data to each column of storage cells of the storage chip in the form of traversal access, and reading the storage data from each column of storage cells of the storage chip.

[0011] In one exemplary embodiment of this disclosure, the method further includes: writing test data into any column of storage cells of the memory chip within a column detection cycle, and reading storage data from the arbitrary column of storage cells; and determining the test result of the arbitrary column of storage cells based on the test data written into the arbitrary column of storage cells and the storage data read from the arbitrary column of storage cells.

[0012] In one exemplary embodiment of this disclosure, the test data is a binary sequence with equal data bits and has different data topologies.

[0013] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the storage chip is greater than the number of bits in the test data.

[0014] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the storage chip is an integer multiple of the number of bits in the test data.

[0015] In one exemplary embodiment of this disclosure, the test data includes any one of the plurality of different binary sequences.

[0016] In one exemplary embodiment of this disclosure, determining the test result of the memory chip based on the test data and the storage data includes: comparing the storage data and the test data to obtain the test result, wherein the test result includes whether each storage cell of the memory chip has a read / write error and the number of bits that have a read / write error.

[0017] In one exemplary embodiment of this disclosure, all memory cells of the memory chip are set to 0 before the test data is written into the memory cells of the memory chip.

[0018] In one exemplary embodiment of this disclosure, after determining the test results of the memory chip, all memory cells of the memory chip are set to 0.

[0019] In one exemplary embodiment of this disclosure, multiple data topologies in the test data are determined by the following method: taking any data bit in the initial test data as a transformation bit, the initial test data is traversed and accessed, and the data of the traversed and accessed transformation bit is converted into the opposite number to obtain a transformation sequence, until all data bits in the initial test data are traversed, and the multiple transformation sequences obtained are determined as the multiple data topologies; wherein, the initial test data is an all-zero sequence of arbitrary length.

[0020] According to a second aspect of this disclosure, a testing apparatus for a memory chip is provided. The apparatus includes: a data module, configured to write test data into a memory cell of the memory chip based on a target write timing parameter of the memory chip, and to read stored data from the memory cell based on a target read timing parameter of the memory chip; and a determination module, configured to determine a test result of the memory chip based on the test data and the stored data; wherein the test data includes multiple different binary sequences, and each binary sequence has one and only one data bit that is 1, the target write timing parameter is less than the standard write timing parameter of the memory chip, and the target read timing parameter is less than the standard read timing parameter of the memory chip.

[0021] In one exemplary embodiment of this disclosure, the data module is used to write the test data to each row of storage cells of the storage chip in the form of traversal access, and to read the stored data from each row of storage cells of the storage chip.

[0022] In one exemplary embodiment of this disclosure, the data module is further configured to write the test data into any row of storage cells of the storage chip and read storage data from any row of storage cells within a row detection cycle. The determining module is further configured to determine the test result of any row of storage cells based on the test data written into the any row of storage cells and the storage data read from the any row of storage cells.

[0023] In one exemplary embodiment of this disclosure, the data module is further configured to write the test data to each column of storage cells of the storage chip in the form of traversal access, and to read the stored data from each column of storage cells of the storage chip.

[0024] In one exemplary embodiment of this disclosure, the data module is further configured to write the test data into any column of storage cells of the storage chip and read the stored data from the any column of storage cells within a column detection cycle; the determining module is configured to determine the test result of the any column of storage cells based on the test data written into the any column of storage cells and the stored data read from the any column of storage cells.

[0025] In one exemplary embodiment of this disclosure, the test data is a binary sequence with equal data bits and has different data topologies.

[0026] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the storage chip is greater than the number of bits in the test data.

[0027] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the storage chip is an integer multiple of the number of bits in the test data.

[0028] In one exemplary embodiment of this disclosure, the test data includes any one of the plurality of different binary sequences.

[0029] In one exemplary embodiment of this disclosure, the determining module is further configured to compare the stored data and the test data to obtain the test result, the test result including whether each storage cell of the storage chip has a read / write error and the number of bits that have a read / write error.

[0030] In one exemplary embodiment of this disclosure, the data module is further configured to set all memory cells of the memory chip to 0 before writing the test data into the memory cells of the memory chip.

[0031] In one exemplary embodiment of this disclosure, the data module is further configured to set all memory cells of the memory chip to 0 after determining the test results of the memory chip.

[0032] In one exemplary embodiment of this disclosure, the data module is further configured to determine multiple data topologies in the test data by performing the following method: taking any data bit in the initial test data as a transformation bit, traversing the initial test data, and converting the data of the traversed transformation bit to the opposite number to obtain a transformation sequence, until all data bits in the initial test data have been traversed, and determining the multiple transformation sequences obtained as the multiple data topologies; wherein, the initial test data is an all-zero sequence of arbitrary length.

[0033] According to a third aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the testing method for any of the above-described memory chips.

[0034] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform a test method for any of the above-described memory chips by executing the executable instructions.

[0035] This disclosure has the following beneficial effects:

[0036] In summary, according to the memory chip testing method, testing apparatus, computer-readable storage medium, and electronic device in this exemplary embodiment, test data can be written to the memory cells of the memory chip based on the target write timing parameters, and stored data can be read from the memory cells based on the target read timing parameters; the test result of the memory chip can be determined based on the test data and the stored data. Since the target write timing parameters and the target read timing parameters of the memory chip are both smaller than the standard write timing parameters and the target read timing parameters are smaller than the standard read timing parameters, the testing time for the memory chip can be shortened, and cells with read / write problems can be quickly detected, greatly improving the testing efficiency of the memory chip.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0039] Figure 1 A flowchart illustrating a testing method for a memory chip in this exemplary embodiment is shown;

[0040] Figure 2 An example of test data is shown in this exemplary embodiment;

[0041] Figure 3A and Figure 3B This illustration shows a test example of a memory chip in this exemplary embodiment;

[0042] Figure 4 A flowchart illustrating another testing method for a memory chip in this exemplary embodiment is shown;

[0043] Figure 5 This diagram illustrates a structural block diagram of a testing apparatus for a memory chip according to this exemplary embodiment.

[0044] Figure 6 This illustration shows a computer-readable storage medium for implementing the above-described method in this exemplary embodiment;

[0045] Figure 7 An electronic device for implementing the above method is shown in this exemplary embodiment. Detailed Implementation

[0046] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0047] Testing memory chips is crucial for ensuring their long-term reliable use. Therefore, companies often need to conduct high-speed and meticulous testing on memory chips before they leave the factory. However, for various types of memory chips, changes to each memory cell can affect other cells within the memory. This interrelationship makes memory chip testing a very complex problem, so it's not possible to draw conclusions simply by testing each memory cell sequentially.

[0048] In view of the aforementioned problems, the exemplary embodiments of this disclosure first provide a testing method for a memory chip. This method writes test data into the memory cells of the memory chip in stages, and determines the test result of the memory chip based on the reading results of each written test data. In this exemplary embodiment, the memory chip may be DRAM (Dynamic Random Access Memory).

[0049] Figure 1 A process of this exemplary embodiment is shown, which may include the following steps S110 to S120:

[0050] Step S110. Based on the target write timing parameters of the memory chip, write test data into the memory cell of the memory chip, and based on the target read timing parameters of the memory chip, read the stored data from the memory cell.

[0051] The target write timing parameter is less than the standard write timing parameter of the memory chip, and the target read timing parameter is less than the standard read timing parameter of the memory chip. The standard write timing parameter refers to the write recovery time of the memory chip, which is the time from when the write command is issued or when writing begins until the next precharge interval. The standard read timing parameter refers to the RAS precharge time, which is the time required for the memory chip to prepare to operate on the next row address in the same logical bank after the previous row address operation is completed and the row address close command is issued. A memory cell is a unit in the memory chip that has the function of storing and reading / writing data. Each memory cell consists of an etched transistor and a capacitor. The etched transistor maintains its storage state through the charge of the capacitor. Test data can be used to test the memory cells of the memory chip. Since the memory chip represents and stores data in binary form, the test data can, for example, include multiple different binary sequences, and each binary sequence has exactly one data bit that is "1". For example, in... Figure 2 In the multiple test data examples shown, when the test data has 8 data bits, it consists of 8 binary sequences, each representing a data topology. Generally, the sequence length of the test data is less than or equal to the number of storage cells in the memory chip. Stored data refers to the data obtained by reading and writing test data from the storage cells of the memory chip, and can be used to verify the read and write functionality of the storage cells.

[0052] When testing a memory chip, test data can be written into its storage cells. For example, the binary sequence of the test data can be written sequentially into each storage cell of the memory chip, with each bit of binary data in the binary sequence written into each storage cell, so that each storage cell contains 1 bit of data, i.e., "0" or "1". Then, the written test data can be read from the storage cells of the memory chip to obtain the stored data in each storage cell.

[0053] Specifically, when writing test data, target write timing parameters can be set through logic control circuits, allowing specific input signals to be applied periodically to the capacitors in the memory cells to write test data into the memory chip's memory cells. This completes the write of test data to each memory cell in the memory chip, ensuring that each memory cell contains one bit of binary data. When reading test data, the logic control circuits can control the memory chip to complete the pre-charge process of the next memory cell within the clock time corresponding to the target read timing parameters, thereby reading the test data of the next memory cell and obtaining the test data written in the memory cell, thus obtaining the stored data. Here, the timing of the memory chip refers to the clock cycle value. A clock cycle is defined as the rise and fall of a pulse signal until the next rise. As the frequency of the memory chip increases, the clock cycle shortens. In this exemplary embodiment, the clock signal of the memory chip can be a square wave, and the memory chip performs one data transmission each during the rise and fall of the clock signal. Therefore, when writing and reading test data in the memory chip, the logic control circuit can control the clock signal according to the target write timing parameters and the target read timing parameters, so that it generates pulse signals according to the corresponding clock cycle, and controls the memory cells in the memory chip to write and read test data according to the corresponding write cycle and read cycle, so as to obtain the stored data.

[0054] In one alternative implementation, the test data can be any one of the multiple different binary sequences mentioned above. In this approach, any binary sequence can be written into the memory cells of the memory chip according to the target write timing parameters, such that each memory cell contains one bit of data. The process of reading data from the memory cells is then completed according to the target read timing parameters of the memory chip.

[0055] Furthermore, to facilitate writing test data into the storage cells, in one optional implementation, the test data can be a binary sequence with equal data bits, and this test data has a different data topology. The data topology can be used to represent the data structure of the binary sequence written to the storage cells in each test cycle. The test data written to the storage cells in each test cycle can be the same, but the test data written to the storage cells in different test cycles can be different, and the data topology will also be different for different test data. A test cycle refers to the time period during which test data is written to all storage cells of the storage chip at once.

[0056] For memory cells in a memory chip, they can be distributed as a corresponding memory array. Under these conditions, test data can be written according to the rows or columns of memory cells, with the length of the test data written in each row or column being equal. In each test cycle, the same test data can be written to all memory cells of the memory chip. For example, assuming that the length of the test data is equal to the number of columns of memory cells in the memory chip, the test data can be written to each row of memory cells, so that each row of memory cells is written with 1 bit of binary data. In this case, the binary data written to memory cells in the same column is the same.

[0057] For test data with different data topologies, in one optional implementation, multiple data topologies in the test data can be determined by the following method:

[0058] Using any data bit in the initial test data as the transformation bit, the initial test data is traversed, and the data of the traversed transformation bit is converted to its opposite, resulting in a transformation sequence. This process is repeated until all data bits in the initial test data have been traversed, and the resulting multiple transformation sequences are used to determine multiple data topologies. The initial test data can be a sequence of all zeros of arbitrary length.

[0059] For example, assuming the initial test data is "00000000", we can use the first data bit in the initial test data as the conversion bit, convert the data in the conversion bit to the opposite number, and get the first conversion sequence "10000000". Then, we can use the second data bit as the conversion bit, convert the data in the conversion bit in the initial test data to the opposite number, and get the second conversion sequence "01000000". We can use the third data bit as the conversion bit, and so on, until we use the last data bit in the initial test data as the conversion bit, convert the data in the conversion bit to the opposite number, and get the last conversion sequence. All the conversion sequences can form multiple different data topologies.

[0060] Using the above method, multiple conversion sequences can be obtained from the initial test data. During testing, each sequence of the test data, consisting of the initial test data and each conversion sequence, can be written to all memory cells of the memory chip. After each write operation to all memory cells is completed, the data written to the memory cells is read to obtain the stored data.

[0061] Step S120. Determine the test results of the memory chip based on the test data and the storage data.

[0062] By comparing the test data and the stored data, it is determined whether the data read from each storage cell of the storage chip is consistent with the data written, and the test results of the storage chip are obtained. These test results can indicate whether the read and write performance of the storage cells in the storage chip is abnormal.

[0063] Specifically, in one optional implementation, the test results can be obtained by comparing the stored data and the test data. The test results may include whether read / write errors occurred in each storage cell of the memory chip and the number of bits involved in the read / write errors.

[0064] For example, the data read from a storage cell can be compared with the test data written to that cell according to the data writing direction of the test data. This determines whether the read and written data in each storage cell are consistent. If the read and written data of any storage cell are inconsistent, it can be determined that a read / write error has occurred in that storage cell, and the data bit of that storage cell is the data bit where the read / write error occurred. Conversely, if the read and written data are consistent, it can be concluded that no read / write error has occurred in the storage cell. Thus, the test results for all storage cells in the memory chip can be obtained.

[0065] Using the above method, test data can be written into the storage cells of the memory chip, and the data written into the storage cells can be read to obtain the stored data. Based on the difference between the stored data and the test data, the memory cells in the memory chip with read / write anomalies and the number of bits in the memory cells with read / write anomalies can be found, thus completing the test of the memory chip. At the same time, since the target write timing parameters and target read timing parameters are smaller than the standard timing parameters for the memory chip to perform write and read operations, the reduced timing time can create insufficient time conditions for the read and write operations of the memory chip, thereby improving the efficiency of detecting memory cells with read / write anomalies in the memory chip, that is, improving the test efficiency of the memory chip.

[0066] For DRAM memory chips, data is stored through capacitors. Due to the inherent properties of capacitors, information is gradually lost with changes in time and temperature. Therefore, to prevent information loss in memory cells and ensure the continuous storage of the second test data in the memory chip, in one optional implementation, after determining the test result of the memory chip, all memory cells of the memory chip can be set to 0. Specifically, a binary sequence of all "0"s can be written to all memory cells of the memory chip; that is, one bit of binary data "0" can be written to each memory cell of the memory chip until the data writing to all memory cells of the memory chip is completed. In this way, the written data can be kept stored in the memory cells, improving the test accuracy of other memory cells and facilitating the next test of the memory chip.

[0067] As mentioned earlier, memory cells in a memory chip are generally arranged in an array. To facilitate testing the memory chip, corresponding test data can be written according to the row or column where the memory cells are located. Therefore, in one optional implementation, test data can be written to each row of memory cells in the memory chip and read from each row of memory cells in the memory chip through traversal access. For example, test data can be written to each row of memory cells in the memory chip according to the row of the array where the memory cells are located, such as writing 1 bit of binary data to each memory cell in each row in sequence until every memory cell of the memory chip has been written with test data.

[0068] Furthermore, in an alternative implementation, the following method may also be performed:

[0069] Within a row detection cycle, test data is written to any row of storage cells in the storage chip, and stored data is read from that row of storage cells.

[0070] The test result of any one of the above storage cells is determined based on the test data written to and the storage data read from any one of the above storage cells.

[0071] A row testing cycle refers to the time required to test a row of storage cells. When writing test data row by row, test data can be written to any row of the storage chip within one row testing cycle. After writing the data for that row, the data stored in that row's storage cell is read, and this stored data is compared bit by bit with the test data written for that row to determine the test result for that row's storage cell. In this way, the read and write performance of each row of storage cells can be determined on a row-by-row basis to ensure it is normal.

[0072] Correspondingly, in an alternative implementation, test data can be written to each column of memory cells in the memory chip and read from each column of memory cells in the memory chip through traversal access. For example, test data can be written to each column of memory cells in the memory chip according to the columns of the array where the memory cells are located, such as writing 1 bit of binary data to each memory cell in each column of memory cells in sequence until each memory cell of the memory chip has been written with test data.

[0073] Furthermore, in an alternative implementation, the following method may also be performed:

[0074] Within a single column detection cycle, test data is written to any column of memory cells in the memory chip, and stored data is read from that column of memory cells.

[0075] The test result of any one of the above-mentioned storage cells is determined based on the test data written to and the storage data read from any one of the above-mentioned storage cells.

[0076] A column testing cycle refers to the time required to test a row of storage cells. When writing test data column by column, test data can be written to any column of the storage chip within one column testing cycle. After writing the data for that column is complete, the data stored in that column's storage cells is read to obtain the stored data. This stored data is then compared bit by bit with the test data written for that column to determine the test result for that column's storage cells. In this way, the read and write performance of each column of storage cells can be determined to be normal.

[0077] In practice, when writing test data to the storage cells of a memory chip row-by-row or column-by-column, the length of the test data can be arbitrary. For example, in one optional implementation, the number of rows or columns of storage cells in the memory chip can be greater than the number of bits in the test data. Taking row-by-row writing as an example, assuming each row of the memory chip has N storage cells, and the number of bits in the test data is M, where M and N are both positive integers and N > M, when writing test data to the storage cells of each row from left to right or from right to left, each storage cell stores 1 bit of binary data. After completing the writing of the data in the Mth storage cell, the (M+1)th storage cell can be used as the first storage cell of the row, and the test data can be rewritten in sequence until all storage cells in the row are written. If the number of bits in the test data M is greater than the number of storage cells N in each row, the data in the first storage cell of the row can be written from left to right or from right to left. Test data is written into the memory, with each storage cell storing one bit of binary data, until all storage cells in that row have been written. When writing test data into the next row, the test data can be rewritten starting from the first storage cell of that row. In this way, data bits in the test data that are greater than the number of rows in the storage cell will not be written into the storage cell. That is, each row of storage cells in the memory chip will only write the part of the test data whose data bits are equal to the number of rows in the storage cell. Assuming that the number of data bits M in the test data is equal to the number of storage cells N in each row, then it is only necessary to write each bit of binary data sequentially into the storage cells of the same row.

[0078] Furthermore, when the number of rows or columns of storage cells in the memory chip is greater than the number of bits in the test data, in one optional implementation, the number of rows or columns of storage cells in the memory chip can be an integer multiple of the number of bits in the test data. Therefore, when writing test data, taking row-by-row writing as an example, the test data can be written sequentially to each row of storage cells, so that each row of storage cells stores several sets of test data, and each set of test data is sequentially stored in consecutive storage cells.

[0079] Furthermore, to comprehensively test the read and write performance of each storage cell, in one optional implementation, all storage cells of the storage chip can be set to 0 before writing test data into them. That is, before writing test data into the storage cells, a binary sequence of all "0"s can be written into all storage cells, meaning one bit of binary data "0" can be written into each storage cell until all storage cells are written.

[0080] Furthermore, in an optional implementation, after setting all memory cells of the memory chip to 0, the data written in each memory cell can be read to obtain the corresponding stored data. It is then determined whether each data bit of the stored data is "0" to ascertain whether the written and read data of each memory cell are consistent. If the written and read data of a memory cell are consistent, it indicates that the read / write function of that memory cell regarding "0" is normal; otherwise, it indicates that the read / write function of that memory cell regarding "0" is abnormal. In addition, since the data written in each memory cell is all "0", when reading the data written in each memory cell, the data can be read in any direction, or the data can be read randomly. This exemplary implementation does not specifically limit this.

[0081] Using the above method, it is possible to determine whether the read and write function of each storage unit for the data "0" is abnormal before writing test data, thus achieving preliminary testing of each storage unit. This allows for quick determination of whether the read and write function of the data "1" in each storage unit is normal when reading and writing test data, without needing to judge the read and write results of the data "0" in each storage unit. Therefore, it can improve the accuracy and comprehensiveness of storage chip testing, as well as improve testing efficiency.

[0082] In one alternative implementation, row and column tests can be performed simultaneously on the memory cells in the memory chip. For example... Figure 3A As shown, for Figure 2The data topologies shown can be written separately to the storage cells of the memory chip. The test result for each data topology is determined based on the stored data read after writing. Specifically, taking topology 1 as an example, assuming that each row and each column of the memory chip has 8 storage cells, a sequence of all "0"s can be written to all storage cells of the memory chip first, so that each storage cell initially stores data "0". Then, topology 1, i.e., "10000000", is written along the X-axis to each word line of the memory chip, i.e., the first row of storage cells corresponding to WL0, WL1, WL2...WLn. After writing is completed, the stored data of the first row of storage cells is read, and then the stored data of the first row is compared with the written test data to determine the test result of the first row of storage cells. When testing other rows of storage cells, the data of the first row of storage cells can be set to 0, and then test data can be written to the row to be tested according to the above method. Then, the stored data of that row is read and compared to determine the test result of that row of storage cells. In this way, the test of each row of storage cells can be completed. Furthermore, as... Figure 3B As shown, a sequence of all "0"s can be written to all memory cells of the memory chip first, so that each memory cell stores data "0" in its initial state. Then, starting a new line along the Y-axis, topology 1, i.e., "10000000", is written to each word line of the memory chip, i.e., each column of memory cells corresponding to WL0, WL1, WL2...WLn, as shown in the second column of memory cells. After writing is completed, the stored data of the second column of memory cells is read, and then the stored data of the second column is compared with the written test data to determine the test result of the second column of memory cells. When testing each column of memory cells according to this method, the stored data of all other columns of memory cells except the currently tested column is 0. After completing the test of each column of memory cells in the memory chip for topology 1 according to the above method, the data writing and reading of topologies 2-8 in the memory chip are repeated, and the test results are determined.

[0083] Using the above method, the read and write performance of each row and column of storage cells can be determined from both row and column directions, thus completing a comprehensive test of the storage chip.

[0084] In this exemplary embodiment, the memory chip may include multiple memory pages, and each memory page may include the same or different numbers of memory cells. During testing, test data can be written to the memory cells in each memory page, and the stored data of the memory cells in each memory page can be read. This stored data is then compared with the written test data to determine the test results of the memory cells for each memory page corresponding to the memory chip. For example, in an optional embodiment, refer to... Figure 4 As shown, the memory chip can be tested using the following steps S410 to S450:

[0085] Step S410: Write a sequence of all "0"s into the storage cells of each storage page of the storage chip.

[0086] Specifically, a sequence of "0"s can be written to each row or column of memory cells in each page of the memory chip, either row or column. For example, a sequence of "0"s can be written to each column of memory cells in each page of the memory chip, so that each memory cell contains one bit of binary data "0".

[0087] Step S420: Read the sequence of all "0"s written in the storage cell of each storage page in sequence to obtain the storage data. Compare the storage data with the sequence of all "0"s to determine the test result of the storage chip regarding "0".

[0088] Specifically, the data written to each memory cell in each memory page can be read according to the data writing direction of the all-zero sequence. For example, the data written to each column of memory cells can be read according to the data writing order of the all-zero sequence to obtain the stored data corresponding to that column of memory cells. Then, the all-zero sequence is compared with the stored data to determine whether the data of each data bit is consistent, and to determine whether the read and write functions of each memory cell in that column of memory cells are normal, thus obtaining the test result of that column of memory cells. The test results of each column of memory cells in each memory page are determined in the same way to obtain the test results of the memory chip regarding "0".

[0089] In step S430, after completing the read operation on the storage unit, the storage unit is refreshed by writing "0" back to each storage unit.

[0090] To maintain the storage of data "0" in the storage units and prevent changes in the state of some storage units from affecting the test results of other storage units, a refresh process can be performed on the storage units after a read operation is performed on each storage page. Specifically, the storage unit refresh process can be performed when a sequence of all "0"s is written to each row or column of storage units on the storage page, thus writing the "0"s back to each storage unit.

[0091] Using the above method, after completing the read operation of each row or column of storage unit and each storage page of storage unit, the storage unit of each row or column and the storage unit of each storage page can be refreshed to ensure that the data in the storage unit of each storage page is continuously and stably stored.

[0092] Step S440: Based on the target write timing parameters of the memory chip, write test data to the memory cell of each memory page of the memory chip.

[0093] Test data can include multiple different binary sequences. When writing test data, a clock signal matching the target write timing parameters can be generated through logic control circuitry. One binary sequence from the test data is written row-wise or column-wise to each row or column of memory cells in each page of the memory chip. The data write direction of the first test data can be the same as or different from the all-zero data written in the first test.

[0094] Taking row-by-row writing as an example, a binary sequence can be written to each row or column of each storage cell of each storage page of the storage chip according to the data writing direction of the test data, until one bit of data from the binary sequence is written to each storage cell of all storage pages.

[0095] Step S450: Based on the target read timing parameters of the memory chip, read the stored data from the memory cell, and determine the second test result of the memory chip based on the test data and the stored data.

[0096] To determine the performance of a memory cell, the memory chip can be set to read mode using logic control circuitry, and a clock signal matching the target read timing parameters can be generated. The binary sequence written to the memory cell in each memory page can be read row by row or column by column to obtain a set of stored data. Then, the test result of the memory chip corresponding to the binary sequence can be determined by comparing the set of stored data with the corresponding binary sequence.

[0097] After completing the writing and reading of one binary sequence in the test data across all storage pages, steps S440 to S450 can be re-executed to write another binary sequence from the test data into each storage page of the storage chip. By reading the binary sequence written into the storage chip, the newly read storage data is compared with the other binary sequence to determine the test result of the storage chip corresponding to the other binary sequence. This process continues until the writing and reading of each binary sequence in the test data into the storage cells of each storage page is completed, and the corresponding test result is determined.

[0098] Finally, based on the test results, the read and write performance of each storage cell of the storage page of the memory chip when storing different binary sequences can be determined, thus completing the test of the memory chip.

[0099] In summary, according to the memory chip testing method in this exemplary embodiment, test data can be written to the memory cells of the memory chip based on the target write timing parameters, and stored data can be read from the memory cells based on the target read timing parameters. The test results of the memory chip are determined based on the test data and the stored data. Since the target write timing parameters and the target read timing parameters of the memory chip are both smaller than the standard write timing parameters and the target read timing parameters are smaller than the standard read timing parameters, the testing time of the memory chip can be shortened, and cells with read / write problems can be quickly detected, greatly improving the testing efficiency of the memory chip.

[0100] This exemplary embodiment also provides a testing apparatus for memory chips, with reference to... Figure 5 As shown, the testing apparatus 500 for the memory chip may include: a data module 510, which can be used to write test data into the memory cell of the memory chip based on the target write timing parameters of the memory chip, and to read stored data from the memory cell based on the target read timing parameters of the memory chip; and a determination module 520, which can be used to determine the test result of the memory chip based on the test data and the stored data; wherein the target write timing parameters are less than the standard write timing parameters of the memory chip, and the target read timing parameters are less than the standard read timing parameters of the memory chip.

[0101] In one exemplary embodiment of this disclosure, the data module 510 can be used to write test data to each row of storage cells of the storage chip and read storage data from each row of storage cells of the storage chip in the form of traversal access.

[0102] In one exemplary embodiment of this disclosure, the data module 510 can also be used to write test data to any row of storage cells in the storage chip and read storage data from any row of storage cells within a row detection cycle. The determination module 520 can be used to determine the test result of any row of storage cells based on the test data written to and the storage data read from any row of storage cells.

[0103] In one exemplary embodiment of this disclosure, the data module 510 can also be used to write test data to each column of storage cells of the storage chip and read storage data from each column of storage cells of the storage chip in the form of traversal access.

[0104] In one exemplary embodiment of this disclosure, the data module 510 can also be used to write test data to any column of storage cells of the storage chip and read storage data from any column of storage cells within a column detection cycle; the determination module 520 can be used to determine the test result of any column of storage cells based on the test data written to and the storage data read from any column of storage cells.

[0105] In one exemplary embodiment of this disclosure, the test data is a binary sequence with equal data bits and different data topologies.

[0106] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the memory chip is greater than the number of bits of the test data.

[0107] In one exemplary embodiment of this disclosure, the number of rows or columns of storage cells in the memory chip is an integer multiple of the number of bits of the test data.

[0108] In one exemplary embodiment of this disclosure, the test data includes any one of the aforementioned multiple different binary sequences.

[0109] In one exemplary embodiment of this disclosure, the determining module 520 can also be used to compare the stored data and the test data to obtain the test results. The test results include whether each storage cell of the storage chip has a read / write error and the number of bits that have a read / write error.

[0110] In one exemplary embodiment of this disclosure, the data module 510 may also be used to set all memory cells of the memory chip to 0 before writing test data into the memory cells of the memory chip.

[0111] In one exemplary embodiment of this disclosure, the data module 510 can also be used to set all memory cells of the memory chip to 0 after determining the test results of the memory chip.

[0112] In one exemplary embodiment of this disclosure, the data module 510 can also be used to determine multiple data topologies in the test data by performing the following method: taking any data bit in the initial test data as a transformation bit, traversing the initial test data, and converting the data of the traversed transformation bit to the opposite number to obtain a transformation sequence, until all data bits in the initial test data have been traversed, and determining the multiple transformation sequences obtained as multiple data topologies, wherein the initial test data is an all-zero sequence of arbitrary length.

[0113] The specific details of each module in the above-mentioned device have been described in detail in the method section of the implementation plan. For details of the undisclosed scheme, please refer to the implementation plan of the method section, and therefore will not be repeated here.

[0114] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0115] Exemplary embodiments of this disclosure also provide a computer-readable storage medium having a program product stored thereon capable of implementing the methods described above in this specification. In some possible embodiments, various aspects of this disclosure may also be implemented as a program product including program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure.

[0116] refer to Figure 6 As shown, a program product 600 for implementing the above-described method according to an exemplary embodiment of the present disclosure is described. This product may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, the readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0117] The program product 600 may employ any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0118] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0119] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0120] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing devices can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0121] Exemplary embodiments of this disclosure also provide an electronic device capable of implementing the above-described method. Referring below... Figure 7 To describe an electronic device 700 according to such an exemplary embodiment of the present disclosure. Figure 7 The electronic device 700 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0122] like Figure 7 As shown, the electronic device 700 can be represented as a general-purpose computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including storage unit 720 and processing unit 710), and a display unit 740.

[0123] The storage unit 720 stores program code, which can be executed by the processing unit 710 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. For example, the processing unit 710 can perform... Figure 1 and Figure 4 The methods and steps shown are as follows.

[0124] Storage unit 720 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 721 and / or cache memory 722, and may further include a read-only memory (ROM) 723.

[0125] The storage unit 720 may also include a program / utility 724 having a set (at least one) of program modules 725, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0126] Bus 730 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0127] Electronic device 700 can also communicate with one or more external devices 800 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 700, and / or with any device that enables electronic device 700 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 750. Furthermore, electronic device 700 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 via bus 730. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0128] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to exemplary embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0129] Furthermore, the above figures are merely illustrative representations of the processes included in the methods according to exemplary embodiments of this disclosure, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0130] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the exemplary embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the method according to the exemplary embodiments of this disclosure.

[0131] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

Claims

1. A test method of a memory chip, characterized by, The method includes: Based on the target write timing parameters of the memory chip, test data is written to the memory cells of the memory chip, and based on the target read timing parameters of the memory chip, stored data is read from the memory cells; wherein, the clock signal is controlled by the logic control circuit according to the target write timing parameters and the target read timing parameters to control the memory cells of the memory chip to write test data according to the write cycle corresponding to the target write timing parameters, and to read stored data according to the read cycle corresponding to the target read timing parameters; The test results of the memory chip are determined based on the test data and the storage data; The test data includes multiple different binary sequences, and each binary sequence has only one data bit that is 1. The target write timing parameter is less than the standard write timing parameter of the memory chip, and the target read timing parameter is less than the standard read timing parameter of the memory chip.

2. The method of claim 1, wherein, The method further includes: The test data is written to each row of storage cells of the storage chip by traversing through the storage cells, and the stored data is read from each row of storage cells of the storage chip.

3. The method of claim 2, wherein, The method further includes: Within a row detection cycle, test data is written to any row of storage cells in the storage chip, and stored data is read from any row of storage cells. The test result of any given row of storage cells is determined based on the test data written to and the storage data read from that row.

4. The method of claim 1, wherein, The method further includes: The test data is written to each column of storage cells of the memory chip by traversing through the memory chip, and the stored data is read from each column of storage cells of the memory chip.

5. The method of claim 4, wherein, The method further includes: During a column detection cycle, test data is written to any column of storage cells in the storage chip, and stored data is read from any column of storage cells. The test result of any one column of storage cells is determined based on the test data written to and the storage data read from that column.

6. The method of claim 1, wherein, The test data is a binary sequence with equal data bits, and the test data has different data topologies.

7. The method according to any one of claims 2-5, characterized in that, The number of rows or columns of storage cells in the memory chip is greater than the number of bits in the test data.

8. The method according to any one of claims 2-5, characterized in that, The number of rows or columns of storage cells in the storage chip is an integer multiple of the number of bits in the test data.

9. The method of claim 1, wherein, The test data includes any one of the multiple different binary sequences.

10. The method of claim 1, wherein, Determining the test result of the memory chip based on the test data and the storage data includes: The stored data and the test data are compared to obtain the test results, which include whether each storage cell of the storage chip has read / write errors and the number of bits that have read / write errors.

11. The method of claim 1, wherein, Before writing the test data into the memory cells of the memory chip, all memory cells of the memory chip are set to 0.

12. The method of claim 1, wherein, After determining the test results of the memory chip, all memory cells of the memory chip are set to 0.

13. The method of claim 6, wherein, Multiple data topologies in the test data were determined using the following method: Using any data bit in the initial test data as the transformation bit, the initial test data is traversed and accessed, and the data of the traversed transformation bit is converted into the opposite number to obtain a transformation sequence. This process is repeated until all data bits in the initial test data are traversed, and the resulting multiple transformation sequences are determined as the multiple data topologies. The initial test data is a sequence of all zeros of arbitrary length.

14. A testing apparatus for a memory chip, characterized by, The device includes: The data module is used to write test data into the storage cells of the storage chip based on the target write timing parameters of the storage chip, and to read stored data from the storage cells based on the target read timing parameters of the storage chip; wherein, the clock signal is controlled by the logic control circuit according to the target write timing parameters and the target read timing parameters to control the storage cells of the storage chip to write test data according to the write cycle corresponding to the target write timing parameters, and to read stored data according to the read cycle corresponding to the target read timing parameters; A determining module is used to determine the test result of the memory chip based on the test data and the storage data; The test data includes multiple different binary sequences, and each binary sequence has only one data bit that is 1. The target write timing parameter is less than the standard write timing parameter of the memory chip, and the target read timing parameter is less than the standard read timing parameter of the memory chip.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1-13.

16. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1-13 by executing the executable instructions.

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