Single event effect detection method and apparatus

Abstract

Embodiments of the present disclosure provide a single event effect detection method and device. Applied to the field of electronic technology, the method comprises: acquiring current configuration information of an FPGA; checking the current configuration information by using a check algorithm truth table to obtain a configuration information frame that fails to pass the check in the current configuration information, wherein the configuration information frame that fails to pass the check is a position in the FPGA where a single event effect occurs. In this way, the technical problem that it is currently difficult to know the situation that the FPGA is affected by high-energy charged particles can be solved.

Description

Technical Field

[0001] This disclosure relates to the field of electronic technology, and in particular to a method and apparatus for detecting single-event effects. Background Technology

[0002] With the development of integrated circuit technology, highly integrated large-scale programmable chips such as FPGAs are playing an increasingly important role in promoting aerospace electronics technology. Static Random Access Memory (SRAM), as a type of memory, has advantages such as high speed, low power consumption, and compatibility with standard processes. SRAM-based FPGAs are becoming increasingly widely used due to their powerful functionality and low cost. However, microelectronic devices are very sensitive to the high-energy particles in the space environment, and ionizing radiation effects can cause single-event effects in memory cells. SRAM-based FPGAs in lunar spacecraft may malfunction or even fail due to the single-event effects caused by high-energy charged particles in lunar orbit. Currently, lunar radiation environment detectors are commonly used to obtain information about space radiation in lunar orbit. These detectors are often used as dedicated payloads in exploration missions, directly detecting the energy and distribution of space particles, which is costly and cannot directly analyze the actual impact of charged particles on the FPGA.

[0003] There is currently no effective solution to the technical problem of the difficulty in knowing how FPGAs are affected by high-energy charged particles. Summary of the Invention

[0004] This disclosure provides a method and apparatus for detecting single-event effects.

[0005] According to a first aspect of this disclosure, a method for detecting single-event effects is provided. The method includes: acquiring current configuration information of an FPGA; verifying the current configuration information using a truth table of a verification algorithm to obtain configuration information frames that fail verification in the current configuration information, wherein the configuration information frames that fail verification represent the locations where single-event effects occur in the FPGA.

[0006] In addition to the aspects described above and any possible implementation, a further implementation is provided in which obtaining the current configuration information of the FPGA includes: reading the current configuration information of the FPGA through the internal configuration access port of the FPGA; and caching the current configuration information into a shift register in a configurable logic block of the FPGA.

[0007] In addition to the aspects and any possible implementations described above, a further implementation is provided, which uses a verification algorithm truth table to verify the current configuration information and obtains configuration information frames that fail verification in the current configuration information, including: using a verification algorithm based on XOR calculation and parity binary search to verify the current configuration information cached in the shift register and obtaining configuration information frames that fail verification in the current configuration information.

[0008] In addition to the aspects described above and any possible implementation, a further implementation is provided, which uses a verification algorithm based on XOR calculation and parity binary search to verify the current configuration information of the shift register buffer, and obtains the configuration information frames that fail verification in the current configuration information, including: splitting the configuration information to be verified into odd-bit configuration information and even-bit configuration information, inputting them into the lookup table of the configurable logic block respectively, and obtaining the output value, wherein the truth table of the verification algorithm is mapped in the lookup table of the configurable logic block, and the configuration information to be verified is the current configuration information of the shift register buffer in the initial state; determining whether there are configuration information frames that fail verification in the odd-bit configuration information and even-bit configuration information based on the comparison result of the output value and the predetermined value; determining the odd-bit configuration information and / or even-bit configuration information of the configuration information frames that fail verification as new configuration information to be verified, until the configuration information to be verified only includes configuration information frames that fail verification.

[0009] In addition to the aspects and any possible implementations described above, a further implementation is provided, which, after verifying the current configuration information using a verification algorithm truth table and obtaining configuration information frames that failed verification in the current configuration information, further includes: sending the address information of the configuration information frames that failed verification to an external processor, wherein the external processor stores the original configuration information of the FPGA; receiving the original configuration information frames corresponding to the address information sent by the external processor; and writing the original configuration information frames into the FPGA according to the address information through an internal configuration access port to repair the single-event fault of the FPGA.

[0010] In addition to the aspects and any possible implementations described above, a further implementation is provided, in which, after verifying the current configuration information using a verification algorithm truth table and obtaining the configuration information frames that failed verification in the current configuration information, the method further includes: outputting the location and flip type of the configuration information frames that failed verification in ASCII code form; assembling the output ASCII codes into packets and adding a timestamp to obtain a fault information packet, wherein the fault information packet is used to parse and obtain the fault information of the FPGA experiencing a single-event effect.

[0011] In addition to the aspects described above and any possible implementation, a further implementation is provided for obtaining the current configuration information of the FPGA, including: obtaining the current configuration information of the FPGA according to a preset period, wherein the preset period is determined according to the frequency of single-event effects occurring in the FPGA.

[0012] According to a second aspect of this disclosure, a single-event effect detection device is provided. The device includes: an acquisition unit for acquiring current configuration information of an FPGA; and a verification unit for verifying the current configuration information using a verification algorithm truth table to obtain configuration information frames that fail verification in the current configuration information, wherein the configuration information frames that fail verification represent the locations in the FPGA where single-event effects occur.

[0013] According to a third aspect of this disclosure, an FPGA is provided, including a configurable logic block for configuring a single-event effect detection device as described above.

[0014] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described above.

[0015] According to a fifth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods as described in the first and / or second aspects of this disclosure.

[0016] This disclosure provides a direct way to obtain information about the impact of single-event effects on SRAM-type FPGAs in lunar spacecraft by obtaining the current configuration information of the FPGA, verifying the current configuration information using a verification truth table, and determining the location of single-event effects in the FPGA from the configuration information frames that fail to be verified. This solves the technical problem that it is currently difficult to know the impact of high-energy charged particles on FPGAs.

[0017] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0018] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of this disclosure. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0019] Figure 1 A flowchart of a single-event effect detection method according to an embodiment of the present disclosure is shown;

[0020] Figure 2 A schematic diagram of a single-event upset detection module implemented within an FPGA according to an embodiment of the present disclosure is shown.

[0021] Figure 3 A schematic diagram of the ECA verification algorithm calculation for a single-event flip detection module according to an embodiment of the present disclosure is shown;

[0022] Figure 4 A flowchart illustrating the execution of a single-event upset detection module and information downlink according to an embodiment of the present disclosure is shown.

[0023] Figure 5 A schematic diagram of an on-orbit protection method according to an embodiment of the present disclosure is shown;

[0024] Figure 6 A block diagram of a single-event effect detection apparatus according to an embodiment of the present disclosure is shown;

[0025] Figure 7 A block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure is shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0027] Furthermore, the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0028] Currently, related technologies involve launching dedicated lunar radiation environment detectors to obtain information about space radiation in lunar orbit. These detectors are often used as dedicated payloads in exploration missions, directly detecting the energy and distribution of space particles. This approach is costly and cannot directly analyze the actual impact of charged particles on FPGAs. Furthermore, to avoid single-event effects on FPGAs, lunar spacecraft are often designed with highly radiation-resistant aerospace-grade components, resulting in very high costs and limitations imposed by production volume, delivery time, and development cycles. This makes it difficult to meet the demands of the rapidly evolving commercial space industry.

[0029] In this disclosure, by obtaining the current configuration information of the FPGA and verifying the current configuration information using a verification truth table, the location of the single-event effect in the FPGA can be determined from the configuration information frame that fails to verify. This solves the technical problem that it is currently difficult to know the situation of the FPGA being affected by high-energy charged particles.

[0030] Figure 1 A flowchart of a single-event effect detection method 100 according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, the single-event effect detection method 100 includes:

[0032] Step S110: Obtain the current configuration information of the FPGA;

[0033] Step S120: The current configuration information is verified using the truth table of the verification algorithm to obtain the configuration information frames that fail verification in the current configuration information. The configuration information frames that fail verification are the locations where single-event effects occur in the FPGA.

[0034] Configuration information in FPGAs is susceptible to the effects of high-energy particles, resulting in single-event upsets that can impair normal functionality.

[0035] The truth table of the above verification algorithm is used to represent the original configuration information of the FPGA. When the current configuration information is verified using the truth table of the verification algorithm, if the verification fails, it indicates that the FPGA has experienced a single-event effect.

[0036] According to embodiments of this disclosure, by obtaining the current configuration information of the FPGA and verifying the current configuration information using a verification truth table, the location of single-event effects in the FPGA can be determined from the configuration information frames that fail the verification. This provides a direct way to obtain information on the impact of single-event effects on SRAM-type FPGAs in lunar spacecraft, solving the technical problem that it is currently difficult to know the impact of high-energy charged particles on FPGAs. Without using a dedicated irradiated particle detection payload, the single-event effect status of FPGAs in lunar orbit can be effectively and directly obtained, simplifying spacecraft missions and reducing costs.

[0037] In some embodiments, obtaining the current configuration information of the FPGA includes:

[0038] The current configuration information of the FPGA can be read through the FPGA's internal configuration access port.

[0039] The current configuration information is cached in the shift register of the configurable logic block of the FPGA.

[0040] The Internal Configuration Access Port (ICAP) allows direct reading and writing of the FPGA's internal configuration registers within the FPGA logic code, thereby enabling specific configuration functions.

[0041] Configurable Logic Block (CLB), also known as basic Logic Unit, is one of the underlying components of an FPGA. A Configurable Logic Block can include a shift register and a look-up table (LUT).

[0042] To effectively monitor single-event events in an FPGA, the FPGA's current configuration information can be read periodically.

[0043] According to embodiments of this disclosure, the current configuration information is read through the internal configuration access port of the FPGA and cached through the configurable logic blocks of the FPGA. Single-event effect detection is achieved using a small amount of logic resources inside the FPGA, avoiding the use of external chips and simplifying the FPGA system design.

[0044] In some embodiments, obtaining the current configuration information of the FPGA includes: obtaining the current configuration information of the FPGA according to a preset period, wherein the preset period is determined according to the frequency of single-event effects occurring in the FPGA.

[0045] Optionally, when acquiring the current configuration information of the FPGA according to a preset cycle, the current configuration information can be acquired in segments, and each segment of configuration information can be verified in subsequent steps to improve detection efficiency.

[0046] Optionally, the current configuration information of the FPGA can be read through the FPGA's internal configuration access port, including: reading the current configuration information of the FPGA through the FPGA's internal configuration access port according to a preset period, wherein the preset period is determined according to the frequency of single-event effects occurring in the FPGA.

[0047] For example, the preset period for reading the current configuration information through the internal configuration access port can be set to 10ms. From the historical detection results of single-event effect detection, the frequency of single-event effects occurring in the FPGA can be known. If the frequency of single-event effects occurring in a recent period is less than a certain threshold, the preset period can be adjusted from 10ms to 20ms.

[0048] According to embodiments of this disclosure, configuration information is scanned and read through the FPGA's internal configuration access port. This scanning efficiency is significantly higher than that of commonly used external dedicated refresh chips in the industry. Once a single-event event occurs in the FPGA, it can be saved relatively quickly. After a certain period of accumulation, the frequency and location of single-event events in the FPGA can be directly statistically determined. The cycle for acquiring FPGA configuration information can be adaptively adjusted based on the frequency of single-event events.

[0049] In some embodiments, verifying the current configuration information using a verification algorithm truth table to obtain configuration information frames that fail verification in the current configuration information includes: using a verification algorithm based on XOR calculation and parity binary search to verify the current configuration information cached in the shift register to obtain configuration information frames that fail verification in the current configuration information.

[0050] According to embodiments of this disclosure, the current configuration information can be compared with the original configuration information by XOR calculation to obtain the comparison result. This allows for a quick determination of whether the current configuration information is consistent with the original configuration information. By splitting the current configuration information according to the parity bit using the parity binary search method, the efficiency of the verification can be improved, and the configuration information frame that failed the verification can be quickly located.

[0051] In some embodiments, a verification algorithm based on XOR calculation and parity binary search is used to verify the current configuration information of the shift register buffer, resulting in configuration information frames that failed verification in the current configuration information, including:

[0052] The configuration information to be verified is split into odd-numbered configuration information and even-numbered configuration information, which are then input into the lookup table of the configurable logic block to obtain the output value. The truth table of the verification algorithm is mapped to the lookup table of the configurable logic block. The configuration information to be verified is the current configuration information of the shift register buffer in the initial state.

[0053] Based on the comparison results between the output value and the predetermined value, determine whether there are configuration information frames with failed verification in the odd-numbered configuration information and the even-numbered configuration information.

[0054] The odd-numbered and / or even-numbered configuration information bits of the configuration information frames that failed verification are identified as new configuration information to be verified, until the configuration information to be verified contains only configuration information frames that failed verification.

[0055] Through the above steps, the truth table of the verification algorithm is mapped into the lookup table (LUT) of the configurable logic block (CLB). The configuration information bits cached in the shift register are used as the input to the lookup table. The output of the lookup table is compared with the predetermined value by a comparator, and the comparison result is used as the verification criterion. The judgment of multiple configuration information bits is achieved by interconnecting a carry chain (Carry Logic) and a switch matrix.

[0056] For example, the XOR result of all odd-numbered bits in a configuration information segment (i.e., the configuration information to be verified) yields one bit (the result of XORing 32 bits), and the XOR result of all even-numbered bits yields another bit (again, 32 bits). During the detection process, these two bits are recalculated after each segment of configuration information is read, and then compared with the previously correct result. In this way, by comparing the two bits in the two calculation results, it can be determined whether the error occurred in an odd-numbered bit or an even-numbered bit. This is a parity-even binary search. Similarly, parity-even division and XOR calculation can be performed again on the identified erroneous bits to gradually approach the final misalignment position.

[0057] According to embodiments of this disclosure, single-event effect detection in an FPGA is achieved by verifying configuration information using a lookup table of configurable logic blocks in the FPGA. Single-event effect detection is achieved using a small amount of logic resources within the FPGA, avoiding the use of external chips and simplifying the FPGA system design. Furthermore, by employing a carry chain Carry Logic and Switch Matrix interconnection to implement a verification algorithm based on XOR calculation and parity binary search, the fault location efficiency of single-event effects is improved.

[0058] In some embodiments, after verifying the current configuration information using a verification algorithm truth table and obtaining configuration information frames that failed verification in the current configuration information, the method further includes:

[0059] The address information of the configuration information frame that failed the verification is sent to an external processor, which stores the original configuration information of the FPGA.

[0060] Receive the raw configuration information frame corresponding to the address information sent by the external processor;

[0061] By using the internal configuration access port, the original configuration information frame is written into the FPGA according to the address information to repair the single-event fault of the FPGA.

[0062] When a single-event event is detected by a configurable logic block, the address of the configuration information frame where the single-event event occurred can be sent to an external processor via a simple communication protocol such as a serial port. The external processor stores a complete configuration file of the FPGA in advance. Based on the received address, it extracts a segment of the configuration information frame related to that address, sends it to the configurable logic block via the JTAG interface, and then writes it into the corresponding address of the FPGA through the internal configuration access port, thereby refreshing the error location and eliminating the single-event fault.

[0063] For example, the electronic system of a spacecraft often has multiple subsystem processing modules. For SRAM-type FPGAs in spacecraft, other processor chips (such as CPUs, DSPs, etc.) in the spacecraft's electronic system can be used as external processors to assist in the on-orbit refresh and protection of the SRAM-type FPGA.

[0064] According to embodiments of this disclosure, by storing the original configuration information of the FPGA in an external processor, after the configurable logic block in the FPGA detects a single-event effect, the configuration information frame that failed the verification can be automatically refreshed through information transmission between the external processor and the configurable logic block in the FPGA, thus automatically eliminating the single-event fault. For FPGAs in spacecraft, automatic detection and elimination of single-event effects can be achieved, realizing on-orbit protection against single-event effects.

[0065] In some embodiments, after verifying the current configuration information using a verification algorithm truth table and obtaining configuration information frames that failed verification in the current configuration information, the method further includes:

[0066] Output the location and flip type of the configuration information frame that failed the verification in ASCII code format;

[0067] The output ASCII codes are grouped into packets and timestamps are added to obtain fault information packets. These fault information packets are used to parse and obtain fault information indicating that the FPGA has experienced a single-event effect.

[0068] For FPGAs in spacecraft, upon detecting a single-event event (SEE), the location of the configuration information frame indicating the SEE and the type of SEE flip can be output to the application program in ASCII code. The application program then packages the information, adds a timestamp, and transmits it to the ground via telemetry. Ground personnel can then parse the information to obtain detailed information about the SEE flip that occurred in the on-orbit FPGA.

[0069] According to embodiments of this disclosure, by packaging the detection results of single-event effect detection and transmitting them to the ground via a telemetry channel, the frequency and location of single-event effects occurring in the FPGA in lunar orbit can be directly calculated after a certain period of time.

[0070] The method 100 of this disclosure embodiment will be described below using specific implementation examples:

[0071] The Moon has a weak magnetic field and lacks the protection of Earth's magnetic field, resulting in a large number of charged radiation particles, such as galactic cosmic rays and solar cosmic rays, existing in its orbit and on its surface. With the development of integrated circuit technology, highly integrated large-scale programmable chips, such as FPGAs, are playing an increasingly important role in advancing aerospace electronics technology. SRAM-based FPGAs are becoming increasingly widely used due to their powerful functionality and low cost. However, the high-energy charged particles in lunar orbit exert a significant single-event effect on the Moon, potentially leading to device malfunctions or even failure.

[0072] Currently, space radiation conditions in lunar orbit are obtained by launching dedicated lunar radiation environment detectors. These detectors are often used as dedicated payloads in exploration missions, directly detecting the energy and distribution of space particles. This approach is costly and cannot directly analyze the actual impact of charged particles on FPGAs. Furthermore, to avoid single-event effects on FPGAs, lunar spacecraft are often designed with highly radiation-hardened aerospace-grade components, resulting in very high costs and limitations imposed by production volume, delivery time, and development cycles. This makes it difficult to meet the demands of the rapidly evolving commercial space industry.

[0073] This disclosure proposes a statistical method for SRAM-type single-event effect information in lunar orbit, while also taking into account on-orbit single-event protection design. Without using a dedicated radiation particle detection payload, it can effectively and directly obtain the single-event occurrence status of SRAM-type FPGAs in lunar orbit, and can also correct single-event errors, avoiding the use of expensive dedicated radiation-hardened devices and improving the space reliability of FPGAs.

[0074] SRAM-based FPGAs or SRAM-based PLs in SOCs are susceptible to configuration information fluctuations caused by high-energy particles, leading to flips and affecting normal functionality. This disclosure presents a single-event upset (SOME) detection module that operates within the FPGA with minimal resource consumption. Utilizing the FPGA's underlying ICAP interface, it periodically reads the FPGA configuration information in segments and performs verification calculations on each segment using EAC (Effective Energy Check). When an error is detected, it indicates a space SOME has occurred. The detection module outputs the location and type of the flipped configuration information in ASCII code to the application software. The application software packages the information, adds a timestamp, and transmits it to the ground via telemetry. Ground personnel can then analyze the information to obtain detailed information about the on-orbit FPGA experiencing an SOME.

[0075] The single-particle flip detection module designed in this embodiment is implemented entirely using FPGA basic logic units (CLBs). Figure 2 A schematic diagram of a single-event upset detection module implemented within an FPGA according to an embodiment of the present disclosure is shown, such as... Figure 2 As shown, the single-event flip detection module uses a shift register in the CLB to cache the read configuration information. The truth table of the verification algorithm is mapped to the LUT lookup table in the CLB. The configuration information bits cached in the shift register are used as the input to the LUT. The output of the LUT is compared with a predetermined value using a comparator, and the comparison result serves as the verification criterion. The judgment of multiple configuration information bits is achieved through the interconnection of a carry chain logic and a switch matrix.

[0076] The single-event flip detection module employs an Error Check Algorithm (ECA) based on XOR computation and parity binary search. The basic process of ECA is as follows:

[0077] Figure 3 A schematic diagram of the ECA verification algorithm calculation for a single-event upset detection module according to an embodiment of the present disclosure is shown, as follows: Figure 3 As shown, when configuring FPGA information, the XOR result of all odd-numbered bits in a configuration information segment yields one bit (the result of XORing 32 bits), and the XOR result of all even-numbered bits yields another bit (again, 32 bits). During the detection process, the single-event upset detection module recalculates these two bits each time it reads a segment of configuration information and then compares them with the previously correct result. By comparing these two bits in the two calculation results, it can be determined whether the error occurred in an odd-numbered bit or an even-numbered bit. This is an example of parity-even binary search. Similarly, parity-even division and XOR calculations can be performed again on the identified erroneous bits to gradually approximate the final misalignment position.

[0078] Figure 4 A flowchart illustrating the execution of a single-event upset detection module and information downlink according to an embodiment of the present disclosure is shown, as follows: Figure 4 As shown, the scanning cycle for reading configuration information via the ICAP interface can be set to 10ms. The scanning cycle can be adaptively adjusted based on the frequency of errors, significantly exceeding the scanning efficiency of commonly used external dedicated refresh chips in the industry. For each frame / segment of configuration information verification, error-related configuration information frames can also be extracted. Multiple frames can be read simultaneously, fully utilizing idle resources in the FPGA design and further improving scanning and detection efficiency and flexibility.

[0079] In this way, once a single-event upset occurs in the lunar orbit, the FPGA can be saved relatively quickly and transmitted to the ground via a telemetry channel. After a certain period of accumulation, the frequency and location of single-event upsets in the lunar orbit of the FPGA can be directly calculated.

[0080] Since the single-event upset detection module program only occupies very little FPGA resources, with an actual usage of <1%, it can be assumed that the possibility of the detection module itself flipping is extremely small.

[0081] While the detection module detects a single-event upset (SWE) error and transmits it to the ground, this disclosure proposes an on-orbit protection method to eliminate SWE. A spacecraft's electronic system often has multiple subsystem processing modules. This invention utilizes other processor chips in the spacecraft system, such as CPUs and DSPs, in conjunction with the SWE detection module to assist in the on-orbit refresh and protection of SRAM-type FPGAs.

[0082] Figure 5 A schematic diagram of an on-orbit protection method according to an embodiment of the present disclosure is shown, such as... Figure 5 As shown, the single-event detection module can send the address of the configuration information where the single-event upset occurred to an external processor through simple communication protocols such as serial port. The external processor stores a complete configuration file of the FPGA in advance. Based on the address where the error occurred, it extracts a segment of configuration information frame related to that address and sends it to the single-event detection module through the JTAG interface. The single-event detection module then writes it into the corresponding configuration address of the FPGA through the ICAP interface, thereby refreshing the error location and eliminating the single-event fault.

[0083] This disclosure proposes a method for directly acquiring information about single-event upset (SWE) faults occurring in a lunar orbit FPGA. This avoids the need for payloads carried out in dedicated radiation environments, simplifying spacecraft missions and reducing costs. The method utilizes a small amount of logic resources within the FPGA to detect SWE, avoiding the use of external chips and simplifying FPGA system design. Furthermore, it enables on-orbit protection against SWE by leveraging existing modules or subsystems in the spacecraft design, without adding additional FPGA-related resources. This approach ensures the FPGA's space radiation resistance while reducing design complexity.

[0084] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0085] The above is an introduction to the method embodiments. The following describes the solution described in this disclosure further through device embodiments.

[0086] Figure 6A block diagram of a single-event effect detection apparatus 600 according to an embodiment of the present disclosure is shown. The apparatus 600 can be included in a configurable logic block of an FPGA for performing the single-event effect detection method described above. Figure 6 As shown, the device 600 includes:

[0087] Acquisition unit 610 is used to acquire the current configuration information of the FPGA;

[0088] The verification unit 620 is used to verify the current configuration information using the truth table of the verification algorithm, and to obtain the configuration information frames that fail to be verified in the current configuration information. The configuration information frames that fail to be verified are the locations where single-event effects occur in the FPGA.

[0089] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the described module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0090] According to embodiments of this disclosure, this disclosure also provides an FPGA including configurable logic blocks for configuring the above-described single-event effect detection device.

[0091] Since the single-event effect detection device occupies very little FPGA resources, with an actual usage of <1%, it can be assumed that the single-event effect detection device itself is extremely unlikely to flip.

[0092] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0093] Figure 7 A schematic block diagram of an electronic device 700 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0094] Electronic device 700 includes a computing unit 701, which can perform various appropriate actions and processes according to a computer program stored in ROM 702 or a computer program loaded into RAM 703 from storage unit 708. RAM 703 can also store various programs and data required for the operation of electronic device 700. The computing unit 701, ROM 702, and RAM 703 are interconnected via bus 704. I / O interface 705 is also connected to bus 704.

[0095] Multiple components in electronic device 700 are connected to I / O interface 705, including: input unit 706, such as keyboard, mouse, etc.; output unit 707, such as various types of displays, speakers, etc.; storage unit 708, such as disk, optical disk, etc.; and communication unit 709, such as network card, modem, wireless transceiver, etc. Communication unit 709 allows electronic device 700 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0096] The computing unit 701 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 701 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as method 100. For example, in some embodiments, method 100 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 700 via ROM 702 and / or communication unit 709. When the computer program is loaded into RAM 703 and executed by the computing unit 701, one or more steps of method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform method 100 by any other suitable means (e.g., by means of firmware).

[0097] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0099] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0100] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including voice input, speech input, or tactile input).

[0101] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0102] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0103] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0104] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for detecting single-event effects, comprising: Obtain the current configuration information of the FPGA; This includes: reading the current configuration information of the FPGA through the FPGA's internal configuration access port; The current configuration information is cached in a shift register within a configurable logic block of the FPGA; The current configuration information is verified using a verification algorithm truth table to obtain configuration information frames that fail verification. The configuration information to be verified is split into odd-numbered configuration information and even-numbered configuration information, which are respectively input into the lookup table of the configurable logic block to obtain the output value. The verification algorithm truth table is mapped to the lookup table of the configurable logic block. The configuration information to be verified is the current configuration information cached by the shift register in the initial state. Based on the comparison result between the output value and the predetermined value, it is determined whether there are configuration information frames with failed verification in the odd-numbered configuration information and even-numbered configuration information. The odd-numbered configuration information and / or the even-numbered configuration information of the configuration information frame that has failed verification are identified as new configuration information to be verified, until the configuration information to be verified contains only configuration information frames that have failed verification; wherein, the configuration information frame that has failed verification is the location in the FPGA where a single-event effect occurs.

2. The method according to claim 1, wherein, After verifying the current configuration information using a truth table of a verification algorithm and obtaining configuration information frames that failed verification in the current configuration information, the method further includes: The address information of the configuration information frame that failed the verification is sent to an external processor, wherein the external processor stores the original configuration information of the FPGA; Receive the original configuration information frame corresponding to the address information sent by the external processor; The original configuration information frame is written into the FPGA according to the address information through the internal configuration access port to repair the single-event fault of the FPGA.

3. The method according to claim 1, wherein, After verifying the current configuration information using a truth table of a verification algorithm and obtaining configuration information frames that failed verification in the current configuration information, the method further includes: The location and flip type of the configuration information frame that failed the verification are output in ASCII code format; The output ASCII codes are grouped into packets and timestamps are added to obtain fault information packets, which are used to parse and obtain fault information of single-event effect in the FPGA.

4. The method according to claim 1, wherein, The process of obtaining the current configuration information of the FPGA includes: The current configuration information of the FPGA is obtained according to a preset period, wherein the preset period is determined according to the frequency of single-event effects occurring in the FPGA.

5. A single-event effect detection device, comprising: The acquisition unit is used to acquire the current configuration information of the FPGA; This includes: reading the current configuration information of the FPGA through the FPGA's internal configuration access port; The current configuration information is cached in a shift register within a configurable logic block of the FPGA; The verification unit is used to verify the current configuration information using a verification algorithm truth table to obtain configuration information frames that fail verification in the current configuration information. The configuration information to be verified is split into odd-numbered configuration information and even-numbered configuration information, which are respectively input into the lookup table of the configurable logic block to obtain the output value. The verification algorithm truth table is mapped to the lookup table of the configurable logic block. The configuration information to be verified is the current configuration information cached by the shift register in the initial state. Based on the comparison result between the output value and the predetermined value, it is determined whether there are configuration information frames with failed verification in the odd-numbered configuration information and even-numbered configuration information. The odd-numbered configuration information and / or the even-numbered configuration information of the configuration information frame that has failed verification are identified as new configuration information to be verified, until the configuration information to be verified contains only configuration information frames that have failed verification; wherein, the configuration information frame that has failed verification is the location in the FPGA where a single-event effect occurs.

6. An FPGA including a configurable logic block for configuring the single-event effect detection device as claimed in claim 5.

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