An on-chip micro ion pump and its fabrication method

Abstract

This application provides an on-chip micro ion pump and its fabrication method. The on-chip micro ion pump includes: an electron emission layer, a first spacer layer with a first through-hole, an electron acceleration layer with a second through-hole, a second spacer layer with a third through-hole, and an ion adsorption layer with an ion adsorbent. The first, second, and third through-holes constitute a first chamber. The electron emission layer includes an electron emission structure, which is either a thermionic emission structure or an internal field electron emission structure. Both electron emission structures provide stable electron emission and have low requirements for the vacuum level of the working environment, significantly reducing the operating voltage. Therefore, the on-chip micro ion pump provided in this application provides stable electron emission, low operating voltage, and low requirements for the vacuum level of the working environment, providing a relatively reliable vacuum pump for obtaining on-chip vacuum.

Description

Technical Field

[0001] This application relates to the field of micro ion pump technology, and in particular to an on-chip micro ion pump and a method for fabricating the on-chip micro ion pump. Background Technology

[0002] Vacuum electronic devices are widely used in aerospace, military, medical and health, security inspection, home appliances, scientific research equipment and other fields, and the development of vacuum electronic devices towards miniaturization, on-chip, and integration is an inevitable trend. Currently, microelectronic devices that can operate independently are very small and usually require vacuum pumps or vacuum pump arrays to maintain a vacuum environment. However, traditional vacuum pumps are not only bulky but also energy-intensive and expensive, which to some extent limits the miniaturization development of vacuum electronic devices. Therefore, the invention of micro vacuum pumps aimed at achieving on-chip vacuum environments is of great significance, especially on-chip micro ion pumps. Summary of the Invention

[0003] In view of this, this application provides an on-chip micro ion pump and its fabrication method, as follows:

[0004] An on-chip micro ion pump, the on-chip micro ion pump comprising:

[0005] An electron emission layer, the electron emission layer including an electron emission structure, the electron emission structure being a thermionic emission structure or an internal field electron emission structure;

[0006] A first spacer layer, bonded to the side of the electron emission layer having the electron emission structure, has a first through-hole;

[0007] An electron accelerator layer, bonded to the side of the first spacer layer away from the electron emission layer, has at least one second via;

[0008] The second spacer layer, bonded to the side of the electron accelerating layer away from the electron emitting layer, has a third via;

[0009] An ion adsorption layer is bonded to the side of the second spacer layer away from the electron emission layer, and has an ion adsorbent on the side facing the second spacer layer;

[0010] The first through-hole, the second through-hole, and the third through-hole are arranged sequentially along the first direction to form the first chamber of the on-chip micro ion pump, and the electron emission structure and the ion adsorption layer are located in the first chamber.

[0011] The first direction is perpendicular to the surface of the electron emission layer.

[0012] Optionally, the electron emission structure is a thermionic emission structure, which includes the first electrode and a thermionic emitter; the electron emission layer further includes a substrate;

[0013] The first electrode includes two first sub-electrodes, which penetrate the substrate;

[0014] The two ends of the thermionic emitter are respectively connected to the two first sub-electrodes, and there is a gap between them and the substrate below.

[0015] Optionally, the thermionic emitter is a conductive filament with a thermionic material on its surface;

[0016] The conductive filament is made of at least one of iridium, platinum-iridium, or platinum.

[0017] The heat-emitting material includes at least one of yttrium oxide, barium oxide, aluminum oxide, scandium oxide, and calcium oxide.

[0018] Optionally, the electron emission structure is an internal field electron emission structure, which includes a silicon oxide layer and at least one second electrode. The electron emission layer further includes a substrate, the silicon oxide layer is located on the surface of the substrate, the second electrode includes two second sub-electrodes, the second sub-electrodes include a third sub-electrode and a fourth sub-electrode, the third sub-electrode penetrates the substrate and the silicon oxide layer, and the fourth sub-electrode is located on the surface of the silicon oxide layer and is connected to the third sub-electrode.

[0019] There is a gap between the fourth sub-electrode of the two second sub-electrodes, and the portion of the silicon oxide layer located in the gap is softly broken down, changing from an insulating state to a conductive state.

[0020] Optionally, the substrate is a silicon substrate, the first spacer layer is a glass layer, the electron acceleration layer is a silicon layer, the second spacer layer is a glass layer, and the ion adsorption layer is a silicon layer.

[0021] Optionally, the substrate is a glass substrate, the first spacer layer and the electron acceleration layer are both silicon layers located in the same layer, the second spacer layer is a glass layer, and the ion adsorption layer is a silicon layer.

[0022] Optionally, the ion adsorbent includes at least one of titanium, barium, aluminum, zinc, vanadium, and chromium.

[0023] Optionally, the on-chip micro ion pump also includes at least one second chamber, which is connected to the first chamber;

[0024] The second chamber's top and bottom layers are any two of the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer.

[0025] Optionally, the on-chip micro ion pump includes multiple second chambers that are connected in sequence, and the first chamber is connected to one of the multiple second chambers;

[0026] Alternatively, the first chamber may be connected to the plurality of second chambers.

[0027] Optionally, the on-chip micro ion pump also includes a third chamber connected to the second chamber, and the third chamber contains an alkali metal releasing agent for releasing alkali metal atom gas, so that the second chamber contains alkali metal atom gas.

[0028] The top and bottom layers of the third chamber are any two of the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer.

[0029] A method for fabricating an on-chip micro ion pump, used to fabricate the on-chip micro ion pump described in the above embodiments, the method comprising:

[0030] It provides a first parent layer, a second parent layer, a third parent layer, a fourth parent layer, and a fifth parent layer;

[0031] The first to fifth master layers are bonded using an anodic bonding process; wherein, the first master layer has N periodically arranged electron emission layers, the second master layer has N first spacer layers with the same period, the third master layer has N electron acceleration layers with the same period, the fourth master layer has N second spacer layers with the same period, and the fifth master layer has N ion adsorption layers with the same period.

[0032] Then, the chip is cut to obtain the on-chip micro ion pump.

[0033] Optionally, the first to fifth parent layers are sequentially bonded using anodizing bonding technology, including:

[0034] The first parent layer and the second parent layer are bonded together using an anodic bonding process to form a first bonding structure;

[0035] The second parent layer in the first bonding structure is bonded to the third parent layer using an anodic bonding process to form a second bonding structure;

[0036] The fourth parent layer and the fifth parent layer are bonded together using an anodic bonding process to form a third bonding structure;

[0037] The third parent layer in the second bonding structure is bonded to the fourth parent layer in the third bonding structure using an anodic bonding process;

[0038] The second bonding structure and the third bonding structure are bonded in a high-vacuum chamber.

[0039] Compared with the prior art, the beneficial effects of the technical solution of this application are as follows:

[0040] The on-chip micro ion pump provided in this application sequentially comprises: an electron emission layer, a first spacer layer, an electron acceleration layer, a second spacer layer, and an ion adsorption layer. The electron emission layer includes an electron emission structure, which is either a thermionic emission structure or an internal field electron emission structure. Thermionic emission structures emit electrons by heating them to cause them to overflow from their surface, while internal field electron emission structures utilize the tunneling effect. Both methods offer relatively stable electron emission and do not require a high vacuum environment, thus significantly reducing the operating voltage. Therefore, the on-chip micro ion pump provided in this application provides stable electron emission, a low operating voltage, and low vacuum requirements, thus offering a relatively reliable vacuum pump for obtaining on-chip vacuum. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0042] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size should still fall within the scope of the technical content disclosed in this application, provided that they do not affect the effects and purposes that this application can produce.

[0043] Figure 1 This application provides a schematic diagram of the structure of an on-chip micro ion pump;

[0044] Figure 2 for Figure 1 A sectional view;

[0045] Figure 3 A schematic diagram of the working principle of an on-chip micro ion pump provided in this application;

[0046] Figure 4 A schematic diagram of a thermionic emission structure in an on-chip micro ion pump provided in this application;

[0047] Figure 5 for Figure 4 A sectional view;

[0048] Figure 6 A schematic diagram of an internal field electron emission structure in an on-chip micro ion pump provided in this application;

[0049] Figure 7 for Figure 6 A sectional view;

[0050] Figure 8 A schematic diagram of the structure of the first spacer layer in an on-chip micro ion pump provided in this application;

[0051] Figure 9 A schematic diagram of the structure of an electron acceleration layer in an on-chip micro ion pump provided in this application;

[0052] Figure 10 A schematic diagram of the structure of an ion acceleration layer in an on-chip micro ion pump provided in this application;

[0053] Figure 11 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment 1 of this application;

[0054] Figure 12 This is a schematic diagram of another on-chip micro ion pump provided in Embodiment 1 of this application;

[0055] Figure 13 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment 2 of this application;

[0056] Figure 14 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment 3 of this application;

[0057] Figure 15 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment 4 of this application;

[0058] Figure 16 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment 5 of this application;

[0059] Figure 17 This is a schematic diagram of an on-chip micro ion pump provided in Embodiment Six of this application;

[0060] Figure 18 A flowchart illustrating a method for fabricating an on-chip micro ion pump for the purposes of this application;

[0061] Figure 19 A schematic diagram of the bonding sequence in a method for fabricating an on-chip micro ion pump provided for the implementation of this application;

[0062] Figure 20 A bonding principle diagram of a method for fabricating an on-chip micro ion pump provided for the implementation of this application;

[0063] Figure 21 A schematic diagram of the bonding device used in the fabrication method of an on-chip micro ion pump provided for the implementation of this application. Detailed Implementation

[0064] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely one area of ​​this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0065] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0066] As can be seen from the background technology, the invention of the on-chip micro ion pump plays a very important role in the miniaturization development of vacuum electronic devices.

[0067] An ion pump is an active adsorption vacuum pump that adds an ionization process to the adsorption process. The generated ions collide with the electrodes covering the adsorption material under the action of an electric field, causing the ions to be captured by the electrodes, or magnetron sputtering can expose fresh surfaces of the adsorption material, thus better exerting the adsorption and burial effect. It also has a certain adsorption effect on inert gases, so it is more efficient for obtaining on-chip micro vacuum.

[0068] Currently, there are two main types of on-chip micro-ion pumps under research, distinguished by their ionization mechanisms. One type utilizes collisions between electrons and gas molecules for ionization, using an on-chip electron source to provide electrons. This type of micro-ion pump can achieve an ultimate vacuum of 10⁻³ Pa, but its performance depends on the emission performance of the electron source, exhibits poor stability, requires a high initial vacuum (0.1 Pa), and has a narrow operating vacuum range. The other type utilizes glow discharge to ionize gas molecules. This structure offers higher stability and can achieve a vacuum of 10⁻⁵ Pa, but it requires a very high operating voltage, typically 500-2000 V. Therefore, there is currently no reliable solution for achieving on-chip micro-vacuum.

[0069] Based on this, embodiments of this application provide an on-chip micro ion pump, such as... Figure 1 and Figure 2 As shown, Figure 2 for Figure 1 A cross-sectional view of the on-chip micro-ion pump, which includes:

[0070] An electron emission layer 10, the electron emission layer 10 including an electron emission structure 11, the electron emission structure 11 being a thermionic emission structure or an internal field electron emission structure;

[0071] A first spacer layer 20 is located on the side of the electron emission layer 10 having the electron emission structure 11, is bonded to the electron emission layer 10, and has a first through-hole 21.

[0072] An electron acceleration layer 30 is located on the side of the first spacer layer 20 away from the electron emission layer 10, is bonded to the first spacer layer 20, and has at least one second via 31.

[0073] The second spacer layer 40 is located on the side of the electron accelerator layer 30 away from the electron emission layer 10, is bonded to the electron accelerator layer 30, and has a third through-hole 41.

[0074] An ion adsorption layer 50 is located on the side of the second spacer layer 40 away from the electron acceleration layer 30 and is bonded to the second spacer layer 40. The surface of the ion adsorption layer 50 facing the electron emission layer 10 has an ion adsorbent 52. Optionally, the ion adsorbent includes at least one of titanium, barium, aluminum, zinc, vanadium, and chromium, but this application does not limit it. The ion adsorbent can also be other substances with the ability to adsorb ions, depending on the specific circumstances.

[0075] The first through hole 21, the second through hole 31 and the third through hole 41 are arranged sequentially along the first direction to form the first chamber of the on-chip micro ion pump. The first chamber is the vacuum chamber of the on-chip micro ion pump and is isolated from the outside. The electron emission structure 11 and the ion adsorbent 51 are located in the first chamber.

[0076] It should be noted that the thermionic emission structure emits electrons by heating the surface to cause them to overflow, while the internal field electron emission structure utilizes the tunneling effect. Both types of electron emission structures have low requirements for the vacuum level of the operating environment, significantly reducing the operating voltage. Therefore, the on-chip micro-ion pump provided in this embodiment exhibits stable electron emission, low operating voltage, and low vacuum requirements, providing a relatively reliable vacuum pump for achieving on-chip vacuum.

[0077] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating the working principle of the on-chip micro ion pump provided in this embodiment. The first through-hole 21, the second through-hole 31, and the third through-hole 41 are interconnected to form a cavity. This cavity, together with the ion adsorption layer 50 and the electron emission layer 10 on its upper and lower sides, forms a closed chamber, namely the first chamber of the on-chip micro ion pump. When the on-chip micro ion pump is working, the electron emission structure 11 in the electron emission layer 10 generates and emits electrons by applying a driving voltage through an external power supply. The emitted electrons reach the electron acceleration layer 30 through the first through-hole 21. The electron acceleration layer 30 is externally positively biased, i.e., electrically connected to the positive terminal of the external power supply, and can attract the electrons emitted by the electron emission layer 10, thereby collecting and accelerating the electrons emitted by the electron emission layer 10. After acceleration, the electrons reach the third through-hole 41 through the second through-hole 31, where they collide with air molecules in the third through-hole 41, ionizing the air molecules in the third through-hole 41 to generate ions. The ion adsorption layer 50 is externally negatively biased, i.e., electrically connected to the negative terminal of an external power supply. This allows the ion adsorption layer 50 to attract ions generated by the ionization of air molecules, enabling it to collect these ions. These ions then come into contact with the ion adsorbent 51 on the ion adsorption layer 50, allowing the ion adsorbent 51 to adsorb and bury the ions, thereby reducing the pressure in the first chamber. Furthermore, the external negative bias of the ion adsorption layer 50, connecting it to the negative terminal of the external power supply, also causes the ions to collide with the ion adsorption layer 50. During this collision, magnetron sputtering occurs, continuously exposing fresh surfaces to the ion adsorbent 51. This allows the ion adsorbent 51 to perform its adsorption and burying function more efficiently, resulting in a stronger vacuum generation capability for the on-chip micro-ion pump.

[0078] As described above, when the on-chip micro ion pump is working, the electron acceleration layer can collect electrons generated by the electron emission layer, and the ion adsorption layer can collect ions formed by the ionization of air molecules after being bombarded by electrons. Therefore, the on-chip micro ion pump provided in this application can characterize the vacuum level inside the chamber based on the ratio of the ion current collected by the ion adsorption layer to the electron current collected by the electron acceleration layer, without the need for an additional vacuum gauge.

[0079] Based on the above embodiments, in one embodiment of this application, the electron emission structure is a thermionic emission structure, such as... Figure 4 and Figure 5 As shown, Figure 5 for Figure 4The cross-sectional view shows that the electron emission structure includes a first electrode 12 and a thermionic emitter 13; the electron emission layer also includes a substrate 14. The first electrode 12 includes two first sub-electrodes 121 that penetrate the substrate 14. The two ends of the thermionic emitter 13 are electrically connected to the two first sub-electrodes 121 respectively. There is a gap between the thermionic emitter 13 and the portion of the substrate 14 located below it, so that the thermionic emitter 13 is suspended to dissipate the heat generated by the thermionic emitter 13 and prevent the temperature of the thermionic emitter 13 from becoming too high, which would affect its operation.

[0080] Continue as Figure 5 As shown, in one embodiment of this application, the substrate has a first trench 17, the bottom of the first trench 17 is located in the substrate 14, the two first sub-electrodes 121 are respectively located on opposite sides of the first trench 17, and the thermionic emitter 13 is suspended above the first trench, thus the thermionic emitter 13 is in a suspended state. In another embodiment of this application, the height of the first sub-electrodes can be increased so that the end of the first sub-electrodes connected to the thermionic emitter is at a certain distance from the substrate surface, thereby making the thermionic emitter in a suspended state. This application is not limited to this; in other embodiments of this application, the thermionic emitter can also be made to be in a suspended state in other ways, depending on the specific circumstances.

[0081] Specifically, when the on-chip micro ion pump is working, one of the two sub-electrodes is connected to a positive bias voltage and the other is connected to a negative bias voltage or grounded to apply a driving voltage to the thermionic emitter, thereby heating and activating it to emit electrons.

[0082] It should be noted that the on-chip micro ion pump may also have multiple electron emission structures. If it has multiple electron emission structures, the substrate of the electron emission layer also has multiple first trenches, and each of the multiple first trenches corresponds one-to-one with a thermionic emitter in the multiple electron emission structures. The specific number of electron emission structures is not limited in this application embodiment; it depends on the specific circumstances.

[0083] Optionally, in one embodiment of this application, the thermionic emitter is a conductive filament coated with a thermionic material; wherein the material of the conductive filament includes at least one of iridium, platinum-iridium, or platinum; and the thermionic material includes at least one of yttrium oxide, barium oxide, aluminum oxide, scandium oxide, and calcium oxide. However, this application is not limited thereto, and in other embodiments of this application, the thermionic emitter...

[0084] The above describes the case where the electron emission structure is a thermionic emission structure. Next, we will describe the case where the electron emission structure is an internal field electron emission structure. Specifically, in another embodiment of this application, the electron emission structure is an internal field electron emission structure. The electron emission structure includes a silicon oxide layer and at least one second electrode. The electron emission layer further includes a substrate. The silicon oxide layer is located on the surface of the substrate. The second electrode includes two second sub-electrodes, each of which includes a third sub-electrode and a fourth sub-electrode. The third sub-electrode penetrates the substrate and the silicon oxide layer. The fourth sub-electrode is located on the surface of the silicon oxide layer and is connected to the third sub-electrode. There is a gap between the fourth sub-electrode of the two second sub-electrodes. The portion of the silicon oxide layer located in the gap is softly broken down, changing from an insulating state to a conductive state. This soft breakdown of the portion of the silicon oxide layer located in the gap from an insulating state to a conductive state refers to the process of fabricating the on-chip micro-ion pump. In order to enable the portion of the silicon oxide layer located in the gap to have electron emission capability, a soft breakdown is performed on this portion, putting it in an active state with electron emission capability.

[0085] Specifically, in one embodiment of this application, such as Figure 6 and Figure 7 As shown, Figure 7 for Figure 6 A cross-sectional view shows that the electron emission structure includes a second electrode, which includes two second sub-electrodes 16. Each second sub-electrode 16 includes a third sub-electrode 161 and a fourth sub-electrode 162. The third sub-electrode 161 penetrates the substrate 14 and the silicon oxide layer 15. The fourth sub-electrode 162 is located on the surface of the silicon oxide layer 15 and is in contact with the third sub-electrode 161. There is a gap between the fourth sub-electrode 162 of the two second sub-electrodes 16. The portion of the silicon oxide layer 15 located in the gap is softly broken down from an insulating state to a conductive state.

[0086] When the on-chip micro ion pump is working, the third sub-electrode of one of the two second sub-electrodes is positively biased, and the third sub-electrode of the other second sub-electrode is negatively biased or grounded, so that a potential difference is formed between the two second sub-electrodes, which in turn causes the silicon oxide layer located between the two second sub-electrodes to tunnel, generating and emitting electrons.

[0087] In other embodiments of this application, the electron emission structure may further include multiple second electrodes, which may be arranged in an array or in other arrangements as needed, depending on the specific circumstances. It should be noted that when the electron emission structure includes multiple second electrodes, the structure and positional relationships of each sub-electrode within the second electrodes are the same as when the electron emission structure includes only one second electrode, and will not be repeated here.

[0088] The above embodiments describe the case where the internal field electron emission structure is a tunneling electron emission structure of metal-insulator-metal (MIM). In the first embodiment, the internal field electron emission structure is a vertical MIM tunneling electron emission structure, and in the second embodiment, it is a horizontal MIM tunneling electron emission structure. However, this application is not limited to this. In other embodiments of this application, the internal field electron emission structure can also be a metal-insulator-semiconductor tunneling junction, a graphene-insulator-semiconductor tunneling junction, a graphene-insulator-metal tunneling junction, a Schottky junction, a PN junction, etc., depending on the specific circumstances, and will not be described in detail here.

[0089] Based on any of the above embodiments, in one embodiment of this application, the substrate in the electron emission layer is a silicon substrate, the first spacer layer is a glass layer, the electron acceleration layer is a silicon layer, the second spacer layer is a glass layer, the ion adsorption layer is a silicon layer, and the on-chip micro ion pump includes a five-layer structure.

[0090] In another embodiment of this application, the substrate in the electron emission layer is a glass substrate, the first spacer layer and the electron acceleration layer are both silicon layers and can be merged into the same layer, the second spacer layer is a glass layer, the ion adsorption layer is a silicon layer, and the on-chip micro ion pump includes a four-layer structure, which is simpler.

[0091] It should be noted that the electron accelerating layer and the ion adsorption layer are silicon layers, and in order to make the electron accelerating layer and the ion adsorption layer conductive, the electron accelerating layer and the ion adsorption layer are doped silicon layers. It should also be noted that when the substrate is a glass substrate, the first spacer layer is a silicon layer, and the electron accelerating layer is also a silicon layer. Therefore, the first spacer layer and the electron accelerating layer can be combined into one layer, and the first via and the second via can be formed sequentially, respectively.

[0092] As described above, the on-chip micro ion pump consists of silicon and glass layers arranged in a cyclic pattern. Therefore, the layers can be bonded using anodizing to form the on-chip micro ion pump. This results in a smaller size, allowing integration with on-chip vacuum electronic devices and providing an effective solution for the independent operation of these devices. Furthermore, the use of anodizing to bond the layers enables mass production, improving efficiency and reducing costs.

[0093] It should be noted that when the substrate is a silicon substrate, the electrode located in the substrate is a through-silicon via (TSV) electrode. Specifically, a through-silicon via (TSV) is formed in the silicon substrate, and then a conductive material is formed in the TSV to form the TSV electrode. When the substrate is a glass substrate, the electrode located in the substrate is a through-glass via (TGV) electrode. Specifically, a through-glass via (TGV) is formed in the silicon substrate, and then a conductive material is formed in the TGV to form the TGV electrode.

[0094] It should also be noted that, such as Figure 8 As shown, the shape of the first through-hole 21 in the first spacer layer 20 can be circular or square, etc., and the shape of the third through-hole in the second spacer layer is similar; for example... Figure 9 As shown, the plurality of second vias 31 in the electron acceleration layer 30 can be arranged in a circular array or a square array, depending on the specific situation. Additionally, the structure of the ion adsorption layer 50 is as follows: Figure 10 As shown, the ion adsorbent 51 covers a portion of the surface of the ion adsorption layer 50.

[0095] Based on the above embodiments, in one embodiment of this application, the on-chip micro ion pump may further have at least one second chamber to be evacuated, which is connected to the first chamber. This second chamber can serve as an atomic gas chamber for a micro-MEMS, enhancing the practicality of the on-chip micro ion pump. The top and bottom layers of the second chamber are any two layers selected from the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer. Furthermore, when the on-chip micro ion pump includes multiple second chambers, the multiple second chambers are sequentially connected, and the first chamber is connected to one of the multiple second chambers; or, the first chamber is connected to each of the multiple second chambers, thereby connecting the first chamber and the second chamber.

[0096] The following example illustrates the structure of an on-chip micro ion pump with a first chamber and a second chamber.

[0097] In Embodiment 1 of this application, as Figure 11As shown, the first spacer layer 20 further has a fourth through-hole 61, the electron acceleration layer 30 further has a fifth through-hole 62, and the second spacer layer 40 further has a sixth through-hole 63, which is connected to the third through-hole 41. The fourth through-hole 61, the fifth through-hole 62, and the sixth through-hole 63 are arranged sequentially along the first direction, forming the second chamber of the on-chip micro ion pump. The upper and lower surfaces of the second chamber are the ion adsorption layer 50 and the electron emission layer 10, respectively, both being silicon layers. The first chamber and the second chamber are arranged sequentially along a third direction and are interconnected. The third direction is parallel to the surface of the electron emission layer. It should be noted that the sixth through-hole is connected to the third through-hole by forming a gap between the portion of the second spacer layer located between the third and sixth through-holes and the ion adsorption layer. The first chamber and the second chamber are interconnected through this gap. It should be noted that the substrate in this structure is a silicon substrate. For example... Figure 12 As shown, the substrate can also be a glass substrate. The second chamber structure is the same, except that the substrate is a glass substrate. The first spacer layer and the electron acceleration layer are made of the same silicon layer 20.

[0098] In Embodiment 2 of this application, as Figure 13 As shown, the electron emission layer 10 has a seventh via 64, the electron acceleration layer 30 also has a fifth via 62, and the second spacer layer 40 also has a sixth via 63, which is connected to the third via 41. The seventh via 64, the fifth via 62, and the sixth via 63 are arranged sequentially along the first direction. The fifth via 62 and the sixth via 63 constitute the second chamber of the on-chip micro ion pump. The upper and lower surfaces of the second chamber are the ion adsorption layer 50 and the first spacer layer 20, respectively. The first chamber and the second chamber are arranged sequentially along a third direction and are interconnected. The third direction is parallel to the surface of the electron emission layer. It should be noted that the substrate in this structure is a silicon layer.

[0099] In Embodiment 3 of this application, as Figure 14As shown, the electron emission layer 10 has a seventh via 64, and the electron acceleration layer 30 also has a fifth via 62; the second spacer layer 40 has a second trench 65 on the side facing the electron acceleration layer, and the second trench 65 is connected to the third via 41; wherein, the seventh via 64, the fifth via 62, and the second trench 65 are arranged sequentially along the first direction, and the fifth via 62 and the second trench 65 constitute the second chamber of the on-chip micro ion pump, and the upper and lower surfaces of the second chamber are the second spacer layer 40 and the first spacer layer 20, respectively; the first chamber and the second chamber are arranged along a third direction, and the first chamber and the second chamber are interconnected, and the third direction is parallel to the surface of the electron emission layer. It should be noted that the substrate in this structure is a silicon substrate.

[0100] In Embodiment 4 of this application, as Figure 15 As shown, the first spacer layer 20 further has a fourth through-hole 61, the electron acceleration layer 30 further has a fifth through-hole 62, and the ion adsorption layer 50 has an eighth through-hole 66. The fourth through-hole 61 is connected to the first through-hole 21. The fourth through-hole 61, the fifth through-hole 62, and the eighth through-hole 66 are arranged sequentially along the first direction. The fourth through-hole 61 and the fifth through-hole 62 constitute the second chamber of the on-chip micro ion pump. The upper and lower surfaces of the second chamber are the second spacer layer 40 and the electron emission layer 10, respectively. The first chamber and the second chamber are arranged sequentially along a third direction and are interconnected. The third direction is parallel to the surface of the electron emission layer. It should be noted that the fourth through-hole is connected to the first through-hole by forming a gap between the portion of the first spacer layer located between the fourth and first through-holes and the electron emission layer. The first chamber and the second chamber are interconnected through this gap. It should be noted that in this structure, the substrate is a glass substrate, and the first spacer layer and the second spacer layer are made of the same material and are located in the same silicon layer.

[0101] In Embodiment 5 of this application, as Figure 16As shown, the on-chip micro ion pump also includes a top glass layer 60, which is located on the side of the ion adsorption layer 50 facing away from the electron emission layer 10; the ion adsorption layer 50 has a third groove 67 on the side facing the second spacer layer 40, which corresponds to the third through hole 41. The first through hole 21, the second through hole 31, the third through hole 41, and the third groove 67 constitute the first chamber, and the upper and lower surfaces of the first chamber are the surface of the third groove 67 and the electron emission layer 10, respectively; the first spacer layer 20 also has a fourth through hole 61, the electron acceleration layer 30 also has a fifth through hole 62, and the second spacer layer 40 also has a sixth through hole 62. The ion adsorption layer 50 also has an eighth through-hole 66, which is connected to the third trench 67. The fourth through-hole 61, the fifth through-hole 62, the sixth through-hole 63, and the eighth through-hole 66 are arranged sequentially along the first direction, forming the second chamber of the on-chip micro ion pump. The upper and lower surfaces of the second chamber are a glass top layer 60 and an electron emission layer 10, respectively. The first chamber and the second chamber are arranged sequentially along a third direction and are interconnected. This third direction is parallel to the surface of the electron emission layer. Compared to the aforementioned embodiment without a glass top layer, the first and second chambers have a larger space. It should be noted that the substrate in this structure is a silicon substrate.

[0102] In Embodiment Six of this application, as Figure 17As shown, the on-chip micro ion pump also includes a top glass layer 60, which is located on the side of the ion adsorption layer 50 facing away from the electron emission layer 10; the ion adsorption layer 50 has a third groove 67 on the side facing the second spacer layer 40, the third groove 67 corresponding to the third through hole 41, the first through hole 21, the second through hole 31, the third through hole 41 and the third groove 67 constitute the first chamber, the upper and lower surfaces of the first chamber are the surface of the third groove 67 and the electron emission layer 10, respectively; the electron emission layer 10 has a seventh through hole 64, and the electron acceleration layer 30 also has a fifth through hole 62, The second spacer layer 40 also has a sixth through-hole 63, and the ion adsorption layer 50 also has an eighth through-hole 66, which is connected to the third trench 67. The seventh through-hole 65, the fifth through-hole 62, the sixth through-hole 63, and the eighth through-hole 66 are arranged sequentially along the first direction, forming the second chamber of the on-chip micro ion pump. The upper and lower surfaces of the second chamber are the glass top layer 60 and the first spacer layer 20, respectively. The first chamber and the second chamber are arranged sequentially along a third direction, which is parallel to the surface of the electron emission layer. Compared to the aforementioned embodiment without a glass top layer, the first chamber has a larger space. It should be noted that the substrate in this structure is a silicon substrate.

[0103] Based on the above embodiments, in one embodiment of this application, when the second chamber serves as the atomic gas chamber of the MEMS, the on-chip micro ion pump further includes a third chamber. The third chamber is connected to the second chamber and contains an alkali metal releasing agent. The top and bottom layers of the third chamber are any two of the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer. When the second chamber is evacuated, the alkali metal releasing agent in the third chamber can be activated to release alkali metal atomic gas. Since the third chamber is connected to the second chamber, the third chamber can be used to fill the second chamber (which serves as the atomic gas chamber) with alkali metal atomic gas, resulting in a low concentration of alkali metal atomic gas in the second chamber.

[0104] Optionally, the atomic gas releasing agent in the third chamber releases atomic gases such as lithium, sodium, potassium, rubidium, and cesium, but this application does not limit this and it depends on the specific circumstances.

[0105] Based on any of the above embodiments, in one embodiment of this application, the on-chip micro ion pump further includes two magnets located on the top and bottom or on both sides of the first cavity. The magnetic field generated by the two magnets can further accelerate the electrons emitted by the electron emission layer, which helps the electrons to collide with air molecules and ionize the air molecules.

[0106] This application also provides a method for preparing a micro ion pump, such as... Figure 18 As shown, the preparation method includes:

[0107] S1: Provides the first parent layer, the second parent layer, the third parent layer, the fourth parent layer, and the fifth parent layer;

[0108] S2: The first to fifth master layers are bonded using an anodic bonding process. The first master layer includes N periodically arranged electron emission layers, the second master layer includes N periodically arranged first spacer layers, the third master layer includes N periodically arranged electron acceleration layers, the fourth master layer includes N periodically arranged second spacer layers, and the fifth master layer includes N periodically arranged ion adsorption layers, where N ≥ 1. That is, the first to fifth master layers each have multiple cyclic units, i.e., the first to fifth master layers each have the same number and period of electron emission layers, first spacer layers, electron acceleration layers, second spacer layers, and ion adsorption layers. When the first to fifth master layers are bonded, the periods of each master layer correspond, so that the cyclic units in each master layer correspond.

[0109] S3: After bonding, the layers are then diced to form the on-chip micro-ion pumps. Specifically, the layers are diced according to the cycle of the circulating units in each parent layer to obtain multiple on-chip micro-ion pumps.

[0110] As described above, the fabrication method provided in this application utilizes an anodic bonding process to create on-chip micro-ion pumps. This results in small-sized on-chip micro-ion pumps that can be integrated with on-chip vacuum electronic devices, providing an effective solution for the independent operation of these devices. Furthermore, as explained above, this method involves bonding the first to fifth parent layers and then dicing them to create multiple on-chip micro-ion pumps. Therefore, the fabrication method allows for mass production of these on-chip micro-ion pumps, improving production efficiency and reducing production costs.

[0111] Specifically, step S1, such as Figure 19 Bonding using anodic bonding processes includes:

[0112] S11: The first parent layer and the second parent layer are bonded together using an anodic bonding process to form a first bonding structure; the specific bonding process is as follows:

[0113] like Figure 20As shown, the anodic bonding apparatus includes a power supply 71, a heating plate 72, an anode head 73, and a sealed vacuum bonding chamber 74. Both the heating plate 72 and the anode head 73 are made of thermally and electrically conductive materials. The two poles of the power supply 71 are connected to the heating plate 72 and the anode head 73 respectively to provide voltage, and the power supply 71 has a range of 1500V. The heating plate 72 serves as a bonding stage and heats the film layer located on it during the bonding process. The anode head 73 outputs voltage and applies a certain pressure to the sample. The sealed vacuum bonding chamber 74 provides a vacuum environment for the bonding process.

[0114] Before bonding, the first master layer 81 and the second master layer 82 are ultrasonically cleaned sequentially with acetone, ethanol, and deionized water, and then dried with a nitrogen gun to ensure the surfaces of the first master layer 81 and the second master layer 82 are clean. Then, the first master layer 81 and the second master layer 82 are placed together on the hot plate 72, with the first master layer 81 below and the second master layer 82 above. The anode head 73 is then pressed onto the upper surface of the second master layer 82. The hot plate 72 is connected to the positive terminal of the power supply 71, and the anode head 73 is connected to the negative terminal of the power supply 71. Appropriate pressure and temperature are applied to the first master layer 81 and the first spacer layer, with the temperature between 300℃ and 450℃, to preheat the first master layer 81 and the second master layer 82 for several minutes. Next, turn on the power supply, maintaining the voltage between 900V and 1500V, and record the changes in bonding current. When the current drops to 0mA, turn off the power supply 71 and the temperature switch, reduce the pressure to zero, and allow the bonded first and second parent layers 81 and 82 to cool to room temperature on the heating plate before removing them. Observe the bonding effect between the first and second parent layers 81 and 82 using infrared light, and test the airtightness of the bond between the first and second parent layers 81 and 82 using a helium mass spectrometer leak detector, thus completing the bonding process.

[0115] It should be noted that the principle by which the first parent layer 81 and the second parent layer 82 can achieve anodic bonding is as follows: Figure 20 During the bonding process, sodium ions Na in the second parent layer 82 + Far from the interface, sodium ions (Na) are formed. + Depletion layer, oxygen ions O 2- Near the interface, the silicon ions Si in the first parent layer 81 2+ Near the interface, oxygen ions O 2- and silicon ions Si 2+ Silicon-oxygen bonds are formed at the interface, thereby achieving a tight bond between the first parent layer 81 and the second parent layer 82.

[0116] It is important to note that, Figure 20 In the bonding process shown, the first mother layer 81 is placed on the bottom and the second mother layer 82 is placed on the top on the heating plate 72. However, this application is not limited to this; in other embodiments, such as... Figure 21As shown, the first parent layer 81 is on top of the second parent layer 82, which is on the heating plate 72. The heating plate 72 is electrically connected to the negative terminal of the power supply 71, and the anode head 73 is electrically connected to the positive terminal of the power supply 71. The bonding process is as described above and will not be repeated here. In other words, during the anodic bonding process, it is necessary to ensure that the end contacting the silicon layer is connected to the positive terminal of the power supply, and the end contacting the glass layer is connected to the negative terminal of the power supply.

[0117] S12: Using an anodic bonding process, the second parent layer 82 in the first bonding structure is bonded to the third parent layer 83 to form a second bonding structure; during this process, the third parent layer 83 is connected to the positive terminal of the power supply, and the bonding process is the same as the bonding process of the first parent layer 81 and the second parent layer 82 described above, and will not be repeated here.

[0118] S13: The fourth parent layer 84 and the fifth parent layer 85 are bonded together using an anodic bonding process to form a third bonding structure; during this process, the fifth parent layer 85 is connected to the positive terminal of the power supply, and the bonding process is the same as above.

[0119] S14: Using an anodic bonding process, the third parent layer 83 in the second bonding structure is bonded to the fourth parent layer 84 in the third bonding structure to form the on-chip micro ion pump. During this process, the third parent layer 83 is electrically connected to the positive terminal of the power supply, and the fourth parent layer 84 is electrically connected to the negative terminal of the power supply; the bonding process is the same as above. It should be noted that the final bonding step must be completed in a high-vacuum chamber to form a high-vacuum sealed cavity.

[0120] It should be noted that the above embodiments only illustrate the preparation method provided in this application using one bonding sequence as an example. The order of bonding in this preparation method is not strict and can have multiple sequences, depending on the specific circumstances. Furthermore, the above embodiments illustrate the preparation method under the condition that the first spacer layer and the electron accelerating layer are made of different materials and are not the same layer. When the first spacer layer and the electron accelerating layer are one layer, the bonding process remains the same; only the first spacer layer and the electron accelerating layer are a single layer, and each film layer is bonded one by one.

[0121] It should also be noted that the preparation method further includes preparing each parent layer before bonding them together. However, the process used to prepare each parent layer is a well-known technology in the industry and will not be described in detail here.

[0122] In summary, this application provides an on-chip micro ion pump and its fabrication method. The electron emission structure of this on-chip micro ion pump is a thermionic emission structure or an internal field electron emission structure, which does not require a high vacuum operating environment, has a low operating voltage, and is less affected by other external factors, resulting in relatively stable electron emission. Therefore, the on-chip micro ion pump provided in this application provides stable electron emission, a low operating voltage, and low environmental vacuum requirements, offering a relatively reliable vacuum pump for obtaining on-chip vacuum.

[0123] The various embodiments in this specification are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical areas between embodiments can be referred to interchangeably. For the apparatuses disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant details can be found in the description of the method area.

[0124] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0125] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0126] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An on-chip micro ion pump, characterized in that, include: An electron emission layer, the electron emission layer including an electron emission structure, the electron emission structure being a thermionic emission structure or an internal field electron emission structure; A first spacer layer, bonded to the side of the electron emission layer having the electron emission structure, has a first through-hole; An electron accelerator layer, bonded to the side of the first spacer layer away from the electron emission layer, has at least one second via; The second spacer layer, bonded to the side of the electron accelerating layer away from the electron emitting layer, has a third via; An ion adsorption layer is bonded to the side of the second spacer layer away from the electron emission layer, and has an ion adsorbent on the side facing the second spacer layer; The first through-hole, the second through-hole, and the third through-hole are arranged sequentially along the first direction to form the first chamber of the on-chip micro ion pump, and the electron emission structure and the ion adsorption layer are located in the first chamber. The first direction is perpendicular to the surface of the electron emission layer.

2. The on-chip micro ion pump according to claim 1, characterized in that, The electron emission structure is a thermionic emission structure, which includes a first electrode and a thermionic emitter; the electron emission layer also includes a substrate. The first electrode includes two first sub-electrodes, which penetrate the substrate; The two ends of the thermionic emitter are respectively connected to the two first sub-electrodes, and there is a gap between them and the substrate below.

3. The on-chip micro ion pump according to claim 2, characterized in that, The thermionic emitter is a conductive filament with a thermionic material on its surface; The conductive filament is made of at least one of iridium, platinum-iridium, or platinum. The heat-emitting material includes at least one of yttrium oxide, barium oxide, aluminum oxide, scandium oxide, and calcium oxide.

4. The on-chip micro ion pump according to claim 1, characterized in that, The electron emission structure is an internal field electron emission structure. The electron emission structure includes a silicon oxide layer and at least one second electrode. The electron emission layer also includes a substrate. The silicon oxide layer is located on the surface of the substrate. The second electrode includes two second sub-electrodes. The second sub-electrodes include a third sub-electrode and a fourth sub-electrode. The third sub-electrode penetrates the substrate and the silicon oxide layer. The fourth sub-electrode is located on the surface of the silicon oxide layer and is connected to the third sub-electrode. There is a gap between the fourth sub-electrode of the two second sub-electrodes, and the portion of the silicon oxide layer located in the gap is softly broken down, changing from an insulating state to a conductive state.

5. The on-chip micro ion pump according to claim 2 or 4, characterized in that, The substrate is a silicon substrate, the first spacer layer is a glass layer, the electron accelerator layer is a silicon layer, the second spacer layer is a glass layer, and the ion adsorption layer is a silicon layer.

6. The on-chip micro ion pump according to claim 2 or 4, characterized in that, The substrate is a glass substrate, the first spacer layer and the electron acceleration layer are both silicon layers located in the same layer, the second spacer layer is a glass layer, and the ion adsorption layer is a silicon layer.

7. The on-chip micro ion pump according to claim 1, characterized in that, The ion adsorbent includes at least one of titanium, barium, aluminum, zinc, vanadium, and chromium.

8. The on-chip micro ion pump according to claim 1, characterized in that, The on-chip micro ion pump also includes at least one second chamber, which is connected to the first chamber. The second chamber's top and bottom layers are any two of the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer.

9. The on-chip micro ion pump according to claim 8, characterized in that, The on-chip micro ion pump includes multiple second chambers that are connected in sequence, and the first chamber is connected to one of the multiple second chambers. Alternatively, the first chamber may be connected to the plurality of second chambers.

10. The on-chip micro ion pump according to claim 8, characterized in that, The on-chip micro ion pump also includes a third chamber, which is connected to the second chamber, and contains an alkali metal releasing agent for releasing alkali metal atom gas, so that the second chamber contains alkali metal atom gas. The top and bottom layers of the third chamber are any two of the electron emission layer, the first spacer layer, the electron acceleration layer, the second spacer layer, and the ion adsorption layer.

11. A method for fabricating an on-chip micro ion pump, characterized in that, The method for preparing the on-chip micro ion pump according to any one of claims 1-10 includes: It provides a first parent layer, a second parent layer, a third parent layer, a fourth parent layer, and a fifth parent layer; The first to fifth master layers are bonded using an anodic bonding process; wherein, the first master layer has N periodically arranged electron emission layers, the second master layer has N periodically identical first spacer layers, the third master layer has N periodically identical electron acceleration layers, the fourth master layer has N periodically identical second spacer layers, and the fifth master layer has N periodically identical ion adsorption layers. Then, the chip is cut to obtain the on-chip micro ion pump.

12. The preparation method according to claim 11, characterized in that, The first to fifth parent layers are sequentially bonded using an anodic bonding process, including: The first parent layer and the second parent layer are bonded together using an anodic bonding process to form a first bonding structure; The second parent layer in the first bonding structure is bonded to the third parent layer using an anodic bonding process to form a second bonding structure; The fourth parent layer and the fifth parent layer are bonded together using an anodic bonding process to form a third bonding structure; The third parent layer in the second bonding structure is bonded to the fourth parent layer in the third bonding structure using an anodic bonding process; The second bonding structure and the third bonding structure are bonded in a high-vacuum chamber.

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