Method for manufacturing non-volatile memory elements

Abstract

A method for manufacturing a non-volatile memory element includes the following steps. A stack structure is formed on a substrate, the stack structure including a gate dielectric layer, an auxiliary gate, an insulating layer, and a sacrificial layer stacked in sequence. A tunnel dielectric layer is formed on one side of the stack structure. A floating gate is formed on the tunnel dielectric layer. The stack structure is etched until the uppermost edge of the floating gate is higher than the top surface of the insulating layer. A dielectric material layer is formed to cover the sidewall of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, wherein a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device. More specifically, this invention relates to a method for manufacturing a non-volatile memory element and the non-volatile memory element manufactured by this method. Background Technology

[0002] Because non-volatile memory can repeatedly perform operations such as storing, reading, and erasing data, and the stored data is not lost when the non-volatile memory is turned off, it has been widely used in personal computers and electronic devices.

[0003] Existing non-volatile memory structures have a stacked gate structure, including a tunneling oxide layer, a floating gate, an inter-gate dielectric layer, and a control gate sequentially disposed on a substrate. When programming or erasing operations are performed on such flash memory elements, appropriate voltages are applied to the source region, drain region, and control gate, respectively, causing electrons to be injected into the floating gate or pulled out of the floating gate.

[0004] In programming and erasing operations of non-volatile memory, a high gate-coupling ratio (GCR) between the floating gate and the control gate typically represents a lower operating voltage, thus significantly improving the operating speed and efficiency of flash memory. However, during programming or erasing operations, electrons must flow through a tunneling oxide layer located beneath the floating gate to be injected into or extracted from the floating gate. This process often damages the structure of the tunneling oxide layer, thereby reducing the reliability of the memory element.

[0005] To improve the reliability of memory devices, an erase gate can be used and integrated into the memory device. By applying a positive voltage to the erase gate, electrons are pulled out of the floating gate. Therefore, since electrons in the floating gate are pulled out through the tunneling oxide layer on the floating gate, rather than through the tunneling oxide layer below the floating gate, the reliability of the memory device is further improved.

[0006] With the increasing demand for high-efficiency memory components, there is still a need for an improved memory component that can efficiently erase stored data, as well as a method for manufacturing such a memory component. Summary of the Invention

[0007] This invention provides a method for manufacturing a non-volatile memory element and a non-volatile memory element manufactured by this method. The non-volatile memory element can efficiently erase stored data with a low erase voltage.

[0008] According to some embodiments of the present invention, a method for manufacturing a non-volatile memory element includes the following steps: Forming a stacked structure on a substrate, the stacked structure including a gate dielectric layer, an auxiliary gate, an insulating layer, and a sacrificial layer stacked sequentially. Forming a tunneling dielectric layer on the substrate on one side of the stacked structure. Forming a floating gate on the tunneling dielectric layer. Etching the stacked structure until the uppermost edge of the floating gate is above the top surface of the insulating layer. Forming a dielectric material layer to cover the sidewalls of the floating gate. Etching the dielectric material layer to form an etched dielectric material layer and exposing the uppermost edge of the floating gate. Forming an upper gate structure on the etched dielectric material layer, wherein a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

[0009] According to some embodiments of the present invention, a non-volatile memory element includes at least one stacked gate structure, a tunneling dielectric layer, and at least one floating gate. The stacked gate structure is disposed on a substrate and includes a gate dielectric layer, an auxiliary gate, and a top gate structure stacked sequentially. The tunneling dielectric layer is located on the substrate on one side of the stacked gate structure. The floating gate is disposed on the tunneling dielectric layer and includes a top edge, curved sidewalls, and two lateral sidewalls. The top edge of the floating gate is embedded in the top gate structure. The bottom surface of the top gate structure, extending beyond the lateral sidewalls of the floating gate, is separated from the tunneling dielectric layer. To further optimize the operation of the non-volatile memory element described in the embodiments, an additional intermediate gate may be provided to increase gate coupling with the floating gate.

[0010] By using the non-volatile memory element of this invention, the erase voltage applied to the device can be reduced, which means that electrons can be effectively pulled out of the floating gate, thereby increasing the speed of erasing data.

[0011] To make the above features and advantages of the present invention easier to understand, the embodiments are described in detail below with reference to the drawings.

[0012] The above and other objects of the present invention will undoubtedly become apparent to those skilled in the art after reading the detailed description of the preferred embodiments shown in the following figures. Attached Figure Description

[0013] The following figures are intended to facilitate a better understanding of the invention and are incorporated into and constitute a part of the specification. The figures illustrate embodiments of the invention and, together with paragraphs describing the embodiments, illustrate the working principle of the invention.

[0014] Figure 1 This is a schematic cross-sectional view of a certain process stage of a method for manufacturing non-volatile memory elements according to some embodiments of the present invention. The structure includes a stacked structure and conductive spacer walls.

[0015] Figure 2This is a structural cross-sectional schematic diagram of a certain process stage in the manufacturing method of a non-volatile memory element according to some embodiments of the present invention. The structure includes a floating gate disposed on the sidewall of a stacked structure.

[0016] Figure 3 This is a top view of a structural stage in a manufacturing method for a non-volatile memory element according to some embodiments of the present invention. The structure includes a floating gate disposed on the sidewall of a stacked structure.

[0017] Figure 4 This is a structural cross-sectional schematic diagram of a certain process stage in the manufacturing method of non-volatile memory elements according to some embodiments of the present invention, and the cross-sectional schematic diagram corresponds to... Figure 3 Section lines B-B' and C-C'.

[0018] Figure 5 For some embodiments of the present invention Figure 4 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is higher than the top surface of the stacked structure.

[0019] Figure 6 For some embodiments of the present invention Figure 5 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by a dielectric material layer.

[0020] Figure 7 For some embodiments of the present invention Figure 6 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by an etched dielectric material layer.

[0021] Figure 8 For some embodiments of the present invention Figure 7 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by the upper gate structure.

[0022] Figure 9 For some embodiments of the present invention Figure 8 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are removed, and the gap wall is removed to expose the sidewall of the floating gate.

[0023] Figure 10 For some embodiments of the present invention Figure 9 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure.

[0024] Figure 11 As an alternative embodiment of the present invention Figure 9 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure.

[0025] Figure 12 As an alternative embodiment of the present invention Figure 6 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the residual gap wall is disposed between the upper gate structure and the stacked structure.

[0026] Figure 13 As an alternative embodiment of the present invention Figure 12 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The schematic diagram of the cross sections taken by sections A-A', B-B' and C-C', and the sidewall of the floating gate is covered by the intermediate gate structure.

[0027] Figure 14 As an alternative embodiment of the present invention Figure 5 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered with a dielectric material layer.

[0028] Figure 15 As an alternative embodiment of the present invention Figure 14 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by the upper gate structure.

[0029] Figure 16 For some embodiments of the present invention Figure 15 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure.

[0030] Figure reference numerals: 102 - Isolation structure; 110 - First memory cell region; 112 - Second memory cell region; 200 - Substrate; 202 - Gate dielectric layer; 204 - Auxiliary gate; 206 - Insulating layer; 208 - Sacrificial layer; 210 - Stacked structure; 211 - First sidewall; 212 - Isolation material layer; 213 - Second sidewall; 214 - Dielectric layer; 216 - Dielectric layer; 218 - Tunneling dielectric layer; 220 - Conductive spacer wall; 222 - Source region; 224 - Floating gate; 224-1 - Inner sidewall; 224-2 - Lateral sidewall; 224-3 - Curved sidewall; 2 26 - Top edge; 228 - Dielectric material layer; 230 - Etched dielectric material layer; 230-1 - First part; 230-2 - Second part; 234 - Upper gate dielectric layer; 235 - Upper gate; 236 - Upper gate structure; 237-1 - Bottom edge; 237-2 - Bottom edge; 238 - Inter-gate dielectric; 239 - Control gate; 240 - Middle gate structure; 242 - Drain region; 250 - Etched dielectric material layer; 250-1 - First part; 250-2 - Second part; 250-3 - Third part; H0 - Height; H1 - Height; H2 - Height. Detailed Implementation

[0031] This invention provides several different embodiments that can be used to implement different features of the invention. For the sake of simplicity, examples of specific components and arrangements are also described. These embodiments are provided for illustrative purposes only and are not intended to be limiting. For example, the following statement regarding "a first feature forming on or above a second feature" can mean "the first feature and the second feature are in direct contact" or "there are other features between the first feature and the second feature," such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of this invention may use repeated reference numerals and / or textual annotations. The use of these repeated reference numerals and annotations is for the purpose of making the description more concise and clear, and is not intended to indicate any correlation between different embodiments and / or configurations.

[0032] Furthermore, for the spatially related descriptive terms mentioned in this invention, such as "below," "low," "down," "above," "above," "below," "top," "bottom," and similar terms, for ease of description, their use is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientations of the semiconductor device during use and operation. As the orientation of the semiconductor device varies (rotation 90 degrees or other orientations), the spatially related descriptions used to describe its orientation should also be interpreted in a similar manner.

[0033] Although the invention is described below by way of specific embodiments, the inventive principles of the invention are defined by the claims and can therefore be applied to other embodiments. Furthermore, certain details have been omitted to avoid obscuring the spirit of the invention; these omitted details fall within the scope of knowledge of those skilled in the art.

[0034] Figure 1 This is a cross-sectional schematic diagram of a structure at a certain process stage of a method for manufacturing a non-volatile memory element according to some embodiments of the present invention. The structure includes a stacked structure and conductive spacer walls. (Reference) Figure 1 The structure formed during this process stage includes at least a substrate 200, at least one stacked structure 210, an isolation material layer 212, a tunneling dielectric layer 218, a conductive spacer 220, and a source region 222.

[0035] According to some embodiments of the present invention, the substrate 200 may be a semiconductor substrate having a suitable conductivity type, such as p-type or n-type. The composition of the substrate 200 may include, but is not limited to, silicon, germanium, gallium nitride or other suitable semiconductor materials.

[0036] At least one stacked structure 210 is located on the substrate 200. For example, two stacked structures 210 are disposed on the substrate 200 and laterally spaced from each other. Each stacked structure 210 includes a gate dielectric layer 202, an auxiliary gate 204, an insulating layer 206, and a sacrificial layer 208 stacked sequentially. Each stacked structure 210 includes a first sidewall 211 and a second sidewall 213, and the first sidewalls 211 of adjacent stacked structures 210 are opposite to each other. The auxiliary gate 204 is composed of a conductive material and is configured to open / close a carrier channel in the substrate 200 below it when a suitable voltage is applied thereto. The insulating layer 206 is composed of an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, but not limited thereto, and is used to electrically isolate the auxiliary gate 204 from the layer disposed above the auxiliary gate 204. The sacrificial layer 208 is the uppermost layer in the stacked structure 210. The sacrificial layer 208 is a temporary layer, so it will be removed before the subsequent step of forming a gate structure (e.g., an upper gate structure) on the auxiliary gate 204.

[0037] An isolation material layer 212 is formed on the first sidewall 211 and the second sidewall 213 of the stacked structure 210. The material of the isolation material layer 212 is, for example, silicon oxide / silicon nitride / silicon oxide, or silicon nitride / silicon oxide. The method for forming the isolation material layer 212 includes, for example, firstly forming dielectric layers 214 and 216 covering each stacked structure 210 sequentially on a substrate 200, and then removing portions of dielectric layers 214 and 216 to form the isolation material layer 212 on the sidewall of each stacked structure 210. The material of dielectric layer 214 is, for example, silicon nitride, and the material of dielectric layer 216 is, for example, silicon oxide. The method for forming dielectric layers 214 and 216 is, for example, chemical vapor deposition. The method for removing portions of dielectric layers 214 and 216 is, for example, anisotropic etching.

[0038] The tunneling dielectric layer 218 is formed at least on the substrate 200 between the stacked structures 210, or further formed on both sides of the stacked structures 210. The material of the tunneling dielectric layer 218 is, for example, silicon oxide or other layers that allow hot electrons to pass through the layer through the tunneling effect. The tunneling dielectric layer 218 is formed by methods such as thermal oxidation or deposition, but is not limited thereto.

[0039] Conductive spacer walls 220 are formed on the first sidewall 211 and the second sidewall 213 of each stacked structure 210. The method of forming the conductive spacer walls 220 may include the following steps: First, a conductive layer (not shown) is formed on the substrate 200. The material of the conductive layer is, for example, doped polysilicon, polysilicide, or other suitable conductive material. When the material of the conductive layer is doped polysilicon, its formation method includes, for example, performing an ion implantation step after forming an undoped polysilicon layer by chemical vapor deposition; or utilizing chemical vapor deposition combined with an in-situ dopant implantation method. Then, an etching process, such as anisotropic etching or etch-back, is performed to etch the conductive layer. As a result, the tunneling dielectric layer 218 located between the stacked structures 210 is partially exposed, forming the conductive spacer walls 220.

[0040] Subsequently, a source region 222 is formed in the substrate 200 between adjacent conductive spacer walls 220, with the conductive spacer walls 220 disposed on the first sidewall 211 of the stacked structure 210. The method of forming the source region 222 includes, for example, performing an ion implantation process by using the conductive spacer walls 220 as a shield. Depending on the device requirements, the implanted dopant can be an n-type or p-type dopant. The source region 222 can be considered a shared source region because it is shared by two adjacent memory cells, and each memory cell includes at least the stacked structure 210 and the conductive spacer walls 220.

[0041] Figure 2This is a cross-sectional schematic diagram of a structure in a process stage of a method for manufacturing a non-volatile memory element according to some embodiments of the present invention. The structure includes a floating gate disposed on the sidewall of a stacked structure. (Reference) Figure 2 The conductive spacer wall 220 may be patterned and / or trimmed to form a floating gate 224. The method for patterning the conductive spacer wall 220 is as follows. See also... Figure 1 and Figure 2 A patterned photoresist layer (not shown) is formed on the substrate 200 to cover a portion of the conductive spacer wall 220. Then, the conductive spacer wall 220 exposed from the patterned photoresist layer is completely removed, leaving only the conductive spacer wall 220 disposed on the first sidewall 211 of the stacked structure 210. Furthermore, the portion of the conductive spacer wall 220 disposed on the first sidewall 211 of the stacked structure 210 can be patterned such that this portion of the conductive spacer wall 220 has a polygonal outline when viewed from a top view. Then, the patterned photoresist layer is removed. The height of the floating gate 224 can be appropriately controlled by performing a trimming process. According to some embodiments of the invention, the uppermost edge 226 of the floating gate 224 is higher than the top surface of the auxiliary gate 204 and higher than or slightly lower than the bottom surface of the sacrificial layer 208. Figure 3 The diagram shows the corresponding Figure 2 A top view of the structure shown.

[0042] Figure 3 This is a top view schematic diagram of a certain process stage in a method for manufacturing a non-volatile memory element according to some embodiments of the present invention. The structure includes a floating gate disposed on the sidewall of a stacked structure. Figure 3 The section line A-A' in the middle can correspond to Figure 2 The cross-sectional view shown. (Reference) Figure 3 The substrate 200 between the isolation structures 102 (e.g., shallow trench isolation structures) can serve as the active region of a memory element, and the active region can extend in a first direction, such as the x-direction. The auxiliary gate 204 and the sacrificial layer 208 (both elements of the stacked structure 210) and the source region 222 can extend in a second direction perpendicular to the first direction, such as the y-direction. At least one floating gate, such as two floating gates 224, is disposed between two adjacent auxiliary gates 204. Each floating gate 224 includes an inner sidewall 224-1, a lateral sidewall 224-2, and a curved sidewall 224-3, wherein the inner sidewall 224-1 faces the sidewall of the isolation material layer 212, and the curved sidewall 224-3 connects to the edge of the inner sidewall 224-1 and the edge of the lateral sidewall 224-2. According to some embodiments of the present invention, Figure 3The top view shown includes at least two memory cell regions, such as a first memory cell region 110 and a second memory cell region 112. The first memory cell region 110 and the second memory cell region 112 can each be used to accommodate memory cells, and the two memory cells can be mirror images of each other.

[0043] Figure 4 This is a cross-sectional schematic diagram of the structure of a certain process stage in the manufacturing method of non-volatile memory elements according to some embodiments of the present invention, and the cross-sectional schematic diagram corresponds to... Figure 3 Section lines B-B' and C-C'. Figure 4 Views BB' and CC' and Figure 2 View AA' is at the same manufacturing stage. Please refer to... Figure 4 In view BB', isolation structures 102 are respectively disposed below the stacked structure 210, and the source region 222 is defined between two adjacent isolation structures 102. (See reference) Figure 4 In view CC', isolation structures 102 are disposed on both sides of floating gate 224, and active regions (not shown) can be defined in substrate 200 between two adjacent isolation structures 102.

[0044] Figure 5 For some embodiments of the present invention Figure 4 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is higher than the top surface of the stacked structure. (Reference) Figure 5 Especially Figure 5 In view AA', the sacrificial layer 208 in each stack structure 210 is completely removed until the top surface of the insulating layer 206 is exposed. During the removal of the sacrificial layer 208, a portion of the insulating layer 206 may be slightly removed. Additionally, a portion of the insulating material layer 212 disposed between the stack structure 210 and the floating gate 224 may be removed. The method for removing the sacrificial layer 208 and a portion of the insulating layer 206 may be, for example, wet etching or dry etching, but is not limited thereto. By applying the above etching process, the uppermost edge 226 of the floating gate 224 will be higher than the top surface of the insulating layer 206, and a portion of the inner sidewall 224-1 of the floating gate 224 may be exposed.

[0045] Figure 6 For some embodiments of the present invention Figure 5 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by a dielectric material layer. After completion... Figure 5 The process stage involves etching the stacked structure 210, followed by referring to... Figure 6 A dielectric material layer 228 is formed on the substrate 200 to cover the inner sidewall 224-1, the lateral sidewall 224-2, and the curved sidewall 224-3 of the floating gate 224. (Reference) Figure 6 In view AA', a portion of the inner sidewall 224-1 of the floating gate 224 is in direct contact with the dielectric material layer 228. According to some embodiments of the invention, the dielectric material layer 228 is a conformal layer that maintains the shape of the layer located beneath it. The material of the dielectric material layer 228 is, for example, silicon oxide or other insulating materials, and its formation method is, for example, chemical vapor deposition or other blanket deposition methods, but is not limited thereto.

[0046] Figure 7 For some embodiments of the present invention Figure 6 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by an etched dielectric material layer. (Reference) Figure 7 The dielectric material layer 228 is etched to form an etched dielectric material layer 230 comprising a first portion 230-1 and a second portion 230-2. By etching the dielectric material layer 228, the uppermost edge 226 of the floating gate 224 and a portion of the inner sidewall 224-1 of the floating gate 224 can be exposed to the etched dielectric material layer 230.

[0047] The first portion 230-1 and the second portion 230-2 of the etched dielectric material layer 230 have a gap-wall structure, which can be respectively disposed on opposite sides of each stacked structure 210. For example, the first portion 230-1 of the etched dielectric material layer 230 can be disposed on the first side of each stacked structure 210, such that the first portion 230-1 can cover the first sidewall 211 of the stacked structure 210 and the curved sidewall 224-3 of the floating gate 224, while the second portion 230-2 of the etched dielectric material layer 230 can be disposed on the opposite side (or the second side) of each stacked structure 210, such that the second portion 230-2 can cover the second sidewall 213 of the stacked structure 210. (See reference...) Figure 7 In view AA', the height H0 of the floating gate 224 is higher than the height H1 of the first portion 230-1 of the etched dielectric material layer 230. Furthermore, refer to... Figure 7Based on different requirements, the height H1 of the first portion 230-1 of the etched dielectric material layer 230 on the curved sidewall 224-3 of the floating gate 224 can be the same as or different from the height H2 of the first portion 230-1 of the etched dielectric material layer 230 on the first sidewall 211 of the stacked structure.

[0048] Figure 8 For some embodiments of the present invention Figure 7 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by the upper gate structure. (Refer to...) Figure 8 At least one drain region, such as two drain regions 242, can be formed on the side of the stacked structure 210. The drain regions 242 are respectively disposed in the first memory cell region 110 and the second memory cell region 112, and in subsequent manufacturing processes, the multiple drain regions 242 can be electrically coupled to each other through vias or contacts. According to some embodiments of the invention, the drain regions 242 can also be formed before the formation of the dielectric material layer 228, instead of after the formation of the etched dielectric material layer 230. The method of forming the drain regions 242 includes, for example, performing an ion implantation process. Depending on the device design, the implanted dopant can be an n-type or p-type dopant. The dopant and dopant concentration of the source region 222 and the drain region 242 can be the same or different.

[0049] Then, refer to Figure 8 View AA' shows that at least one upper gate structure, such as two upper gate structures 236, is formed on the top surface of each stacked structure 210. When viewed from a top view, the upper gate structures 236 and the stacked structure 210 can extend along the same direction, such as the y-direction, and the two upper gate structures 236 can be respectively disposed in the first memory cell region 110 and the second memory cell region 112. Each upper gate structure 236 may include a stacked structure of an upper gate dielectric layer 234 and an upper gate 235. Depending on the actual needs, the upper gate structure 236 can serve as an erase gate or simultaneously as an erase gate and a control gate.

[0050] The width of the upper gate structure 236 is independent of the width of the auxiliary gate 204; therefore, the width of the upper gate structure 236 can be equal to, less than, or greater than the width of the auxiliary gate 204. A portion of the upper gate structure 236 in the lateral direction overlaps with the floating gate 224, such that the uppermost edge 226, a portion of the inner sidewall 224-1, and a portion of the curved sidewall 224-3 of the floating gate 224 can overlap the upper gate structure 236. Furthermore, the outer surfaces of the first portion 230-1 and the second portion 230-2 of the etched dielectric material layer 230 are lower than the bottom edge 237-1 of the upper gate structure 236, and the first portion 230-1 and the second portion 230-2 of the etched dielectric material layer 230 are separated from the sidewall of the upper gate 235.

[0051] The material of the upper gate dielectric layer 234 is, for example, silicon oxide or silicon oxynitride. The upper gate dielectric layer 234 is formed, for example, by chemical vapor deposition. The upper gate 235 is formed as follows: a conductive layer (not shown) is formed on the substrate 200, and then the conductive layer is patterned. The material of the conductive layer is, for example, doped polysilicon or polysilicide. When the material of the conductive layer is doped polysilicon, its formation method includes, for example, performing an ion implantation step after forming an undoped polysilicon layer by chemical vapor deposition; or using chemical vapor deposition combined with an in-situ dopant implantation method. Methods for forming the patterned conductive layer include, for example, lithography and etching processes.

[0052] refer to Figure 8 In view BB', a portion of the upper gate structure 236 located above the isolation structure 102 covers the first portion 230-1 of the etched dielectric material layer 230. In other words, the first portion 230-1 of the etched dielectric material layer 230 can be disposed between the upper gate structure 236 and the substrate 200. Furthermore, the bottom edge 237-2 of the upper gate structure 236 disposed above the isolation structure 102 is lower than the top surface of the stacked structure 210.

[0053] refer to Figure 8 In view CC', the upper part of the lateral sidewall 224-2 of the floating gate 224 can be covered by the upper gate structure 236, and the lower part of the lateral sidewall 224-2 of the floating gate 224 can be covered by the etched dielectric material layer 230. Due to the presence of the etched dielectric material layer 230, the bottom surface of the upper gate structure 236, which extends beyond the lateral sidewall 224-2 of the floating gate 224, is separated from the tunneling dielectric layer 218.

[0054] when Figure 8Upon completion of the manufacturing phase, a non-volatile memory cell comprising three gate electrodes is obtained, including an auxiliary gate 204, a floating gate 224, and an upper gate 235. In this case, the etched dielectric layer 230 is composed of an insulating material instead of a conductive material, thereby avoiding unnecessary electrical connections. Specifically, the auxiliary gate 204 can serve as a word line for turning on / off the carrier channel located below the auxiliary gate 204. The floating gate 224 can be used to store or trap electrons, and thus determine the state of the memory cell, such as state "1" or state "0". The upper gate structure 236 can serve not only as a control gate to allow hot electrons to tunnel from the carrier channel to the floating gate 224, but also simultaneously as an erase gate to remove electrons stored in the floating gate 224.

[0055] according to Figure 8 The structure shown, for example, in view CC', has an etchable dielectric layer 230 disposed on the lateral sidewalls 224-2 of the floating gate 224, and the bottom surface of the upper gate structure 236 extending beyond the lateral sidewalls 224-2 of the floating gate 224 is separated from the tunneling dielectric layer 218. By forming the etchable dielectric layer 230, the overlap area between the upper gate structure 236 and the lateral sidewalls 224-2 of the floating gate 224 can be reduced, which means that the coupling capacitance between the upper gate structure 236 and the floating gate 224 can be reduced accordingly. During the erase operation, since electrons stored in the floating gate 224 tunnel primarily through the uppermost edge 226 of the floating gate 224 into the upper gate structure 236, the reduced overlap area between the upper gate structure 236 and the lateral sidewalls 224-2 of the floating gate 224 effectively improves the erase efficiency and reduces the required erase voltage.

[0056] Several alternative embodiments of the invention are further described below, and for the sake of brevity, only the main differences between these embodiments are described below.

[0057] Figure 9 For some embodiments of the present invention Figure 8 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 Sections A-A', B-B', and C-C' were drawn, and the gap wall was removed to expose the sidewalls of the floating gate. (Reference) Figure 9 In view AA', the etched dielectric material layer 230 is further removed, so that the curved sidewalls 224-3 of the floating gate 224 are no longer covered by the etched dielectric material layer 230. (Reference) Figure 9 In view CC', the bottom surface of the upper gate structure 236, which extends beyond the transverse sidewall 224-2 of the floating gate 224, will be exposed and suspended on the tunneling dielectric layer 218.

[0058] Figure 10 For some embodiments of the present invention Figure 9 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure. (Reference) Figure 10 In view AA', after forming the upper gate structure 236, an intermediate gate structure 240 is formed on the floating gate 224, and the curved sidewalls 224-3 of the floating gate 224 are covered by the intermediate gate structure 240. The intermediate gate structure 224 is a stacked structure including an inter-gate dielectric 238 and a control gate 239. (See reference...) Figure 10 In view BB', the bottom edge 237-2 of the upper gate structure 236, positioned above the isolation structure 102, can be covered by the intermediate gate structure 240. (See reference...) Figure 10 In view CC', a portion of the intermediate gate structure 240 is disposed between the bottom surface of the upper gate structure 236 and the substrate 200. Therefore, the inter-gate dielectric 238 is continuously disposed on the bottom surface of the upper gate structure 234 and the lateral sidewall 224-2 of the floating gate 224.

[0059] The inter-gate dielectric 238 is made of silicon oxide / silicon nitride / silicon oxide. The inter-gate dielectric 238 is formed by, for example, sequentially forming a silicon oxide layer, a silicon nitride layer, and another silicon oxide layer using chemical vapor deposition. The inter-gate dielectric 238 can also be made of silicon nitride / silicon oxide or other high dielectric constant materials (k>4). The control gate 239 is made of, for example, doped polysilicon or polysilicide. The control gate 239 is formed by, for example, first forming a conductive layer (not shown) on a substrate, and then patterning the conductive layer to form the control gate 239. The conductive layer is formed by, for example, chemical vapor deposition.

[0060] when Figure 10 Upon completion of the manufacturing phase, a non-volatile memory cell comprising four gate electrodes is obtained, including an auxiliary gate 204, a floating gate 224, an upper gate 235, and an intermediate gate structure 240. Similarly, the auxiliary gate 204 and the floating gate 224 function similarly to... Figure 8 The corresponding gate functions the same. However, in this embodiment, the upper gate 236 can only serve as an erase gate to remove electrons stored in the floating gate 224. In this embodiment, the intermediate gate structure 240 can be a control gate shared by two adjacent memory cells and can cause hot electrons to tunnel from the carrier channel to the floating gate 224 of the selected memory cell.

[0061] according to Figure 10As shown in the structure, such as in view CC', the bottom surface of the upper gate structure 236 extends beyond the lateral sidewall 224-2 of the floating gate 224, and this outwardly extending bottom surface is separated from the tunneling dielectric layer 218. Therefore, the overlap area between the upper gate structure 236 and the lateral sidewall 224-2 of the floating gate 224 is reduced, while the overlap area between the intermediate gate structure 236 and the lateral sidewall 224-2 of the floating gate 224 is increased. As a result, the coupling capacitance between the upper gate structure 236 and the floating gate 224 can be reduced, which means that the erasure efficiency of the erase operation can be improved. Furthermore, the coupling capacitance between the intermediate gate structure 236 and the floating gate 224 is increased, which means that the programming efficiency of the programming operation can also be improved.

[0062] Figure 11 As an alternative embodiment of the present invention Figure 9 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure. Figure 11 The structure shown is similar to Figure 10 The main difference in the structure shown is that Figure 11 The control gate 239 of the intermediate gate structure 240 shown is relatively thin, and it not only covers the curved sidewall 224-3 of the floating gate 224, but also the top surface of the upper gate structure 236.

[0063] Figure 12 As an alternative embodiment of the present invention Figure 6 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the residual gap wall is placed between the upper gate structure and the stacked structure. Figure 12 The structure shown is similar to Figure 8 The main difference in the structure shown is that Figure 12 The etched dielectric layer 250 shown includes residual spacer walls, such as a third portion 250-3, and the etched dielectric layer 250 is formed by etching the dielectric layer 228. (Reference) Figure 12 View AA' shows that the etched dielectric material layer 250 includes at least a first portion 250-1, a second portion 250-2, and a third portion 250-3. The first portions 250-1 are interconnected and disposed between the sidewalls of the opposing floating gates 224. The second portion 250-2 is disposed opposite to the first portion 250-1, and the third portion 250-3 is disposed between the auxiliary gate 204 and the upper gate structure 236. (See reference...) Figure 12In view AA', the third portion 250-3 of the etched dielectric material layer 250 can directly contact the inner sidewall 224-1 of the floating gate 224, but the uppermost edge 226 of the floating gate 224 is still higher than the third portion 250-3 of the etched dielectric material layer 250. Therefore, during the erasure operation, even if the third portion 250-3 of the etched dielectric material layer 250 is disposed between the auxiliary gate 204 and the upper gate structure 236, electrons stored in the floating gate 224 can tunnel from the uppermost edge 226 of the floating gate 224 into the upper gate structure 236.

[0064] Figure 13 As an alternative embodiment of the present invention Figure 12 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The schematic diagram of the cross sections taken by sections A-A', B-B' and C-C', and the sidewall of the floating gate is covered by the intermediate gate structure. Figure 13 The structure shown is similar to Figure 10 The main difference in the structure shown is that Figure 13 The etched dielectric layer 250 includes residual spacer walls, such as a third portion 250-3, and the etched dielectric layer 250 is formed by etching the dielectric layer 228 such that the third portion 250-3 of the etched dielectric layer 250 is disposed between the auxiliary gate 204 and the upper gate structure 236. Reference Figure 13 In view AA', the third part 250-3 of the etched dielectric material layer 250 can directly contact the inner sidewall 224-1 of the floating gate 224, but the uppermost edge 226 of the floating gate 224 is still higher than the third part 250-3 of the etched dielectric material layer 250.

[0065] Figure 14 As an alternative embodiment of the present invention Figure 5 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered with a dielectric material layer. (Refer to...) Figure 14An etchable dielectric material layer 230 with a flat top surface is formed on substrate 200. The upper part of the floating gate 224 may protrude beyond the etchable dielectric material layer 230, such that the uppermost edge of the floating gate 224 does not directly contact the etchable dielectric material layer 230. The material of the etchable dielectric material layer 230 is, for example, silicon oxide or other conductive or insulating materials. The method of forming the etchable dielectric material layer 230 may include blanket deposition of a dielectric material layer (not shown) on substrate 200. Then, the dielectric material layer is planarized to have a flat top surface. Subsequently, the planarized dielectric material layer is etched down to a certain depth to expose the uppermost edge 226 of the floating gate 224, thereby obtaining... Figure 14 The structure shown.

[0066] Figure 15 As an alternative embodiment of the present invention Figure 14 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the uppermost edge of the floating gate is covered by the upper gate structure. Figure 15 The structure shown is similar to Figure 8 The structure shown differs primarily in that the etched dielectric material layer 230 has a flat top surface. Additionally, see reference... Figure 15 In view BB', the bottom edge of the upper gate structure 236 is coplanar with the top surface of the stacked structure 210, rather than being lower than the top surface of the stacked structure 210.

[0067] Figure 16 For some embodiments of the present invention Figure 15 A cross-sectional view after the manufacturing stage, where the cross-sectional view corresponds to... Figure 3 The cross-sections A-A', B-B', and C-C' are defined, and the sidewalls of the floating gate are covered by the intermediate gate structure. Figure 16 The structure shown is similar to Figure 10 The main difference in the structure shown is that, as referenced... Figure 16 View BB' shows that the upper gate structure 236 has a flat bottom surface, rather than a curved bottom surface.

[0068] According to some embodiments of the present invention, a non-volatile memory element manufactured by the above method is provided, the structure of which is compatible with... Figure 8 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 15 and Figure 16The structures shown in the figures are the same, similar, or derived from these structures. The non-volatile memory element includes at least one stacked gate structure disposed on a substrate 200, and includes at least a gate dielectric layer 202, an auxiliary gate 204, an insulating layer 206, and an upper gate structure 236 stacked sequentially. The non-volatile memory element further includes a tunneling dielectric layer 218 disposed on the substrate 200 on one side of the stacked gate structure. The non-volatile memory element further includes at least one floating gate 224. The floating gate 224 is disposed on the tunneling dielectric layer 218 and includes a top edge 226, curved sidewalls 224-3, and two lateral sidewalls 224-2. The top edge 226 of the floating gate 224 is embedded in the upper gate structure 236, and the bottom surface of the upper gate structure 236, extending beyond the lateral sidewalls 224-2 of the floating gate 224, is separated from the tunneling dielectric layer 218. In some embodiments, reference is made to… Figure 10 , Figure 11 , Figure 13 , Figure 15 and Figure 16 An additional intermediate gate structure 240 can be provided to cover the curved sidewall 224-3 of the floating gate 224. The purpose of the intermediate gate structure 240 is to increase the gate coupling with the floating gate 224, thereby further optimizing the operation of non-volatile memory elements.

[0069] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a non-volatile memory element, characterized in that, include: Provide a substrate; At least one stacked structure is formed on the substrate, wherein the at least one stacked structure includes a gate dielectric layer, an auxiliary gate, an insulating layer and a sacrificial layer stacked sequentially; An insulating material layer is formed on the sidewall of the at least one stacked structure; A tunneling dielectric layer is formed on the substrate on one side of the at least one stacked structure; At least one floating gate is formed on the sidewall of the insulating material layer and on the tunneling dielectric layer, wherein the at least one floating gate includes: An inner sidewall facing the sidewall of the insulating material layer; A transverse sidewall; and A curved sidewall connects the edge of the inner sidewall and the edge of the transverse sidewall; Etch the at least one stacked structure until the uppermost edge of the at least one floating gate is above the top surface of the insulating layer; After etching the at least one stacked structure, a dielectric material layer is formed to cover the inner sidewall, the lateral sidewall, and the curved sidewall of the at least one floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the at least one floating gate; and After etching the dielectric material layer, at least one upper gate structure is formed on the etched dielectric material layer, wherein a portion of the etched dielectric material layer is disposed between the at least one upper gate structure and the substrate.

2. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, The etching process of the at least one stacked structure further includes etching the insulating material layer to expose the inner wall of the at least one floating gate.

3. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, During the formation of the dielectric material layer, a portion of the inner wall of the at least one floating gate comes into direct contact with the dielectric material layer.

4. The method for manufacturing a non-volatile memory element as described in claim 3, characterized in that, The etching process further includes exposing a portion of the inner sidewall of the at least one floating gate to the dielectric material layer.

5. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, The at least one stacked structure includes the sidewall and another sidewall opposite to the sidewall, and the etched dielectric material layer includes a first portion and a second portion, respectively covering the sidewall and the other sidewall of the at least one stacked structure.

6. The method for manufacturing a non-volatile memory element as described in claim 5, characterized in that, The first portion of the etched dielectric material layer further covers the curved sidewall of the at least one floating gate.

7. The method for manufacturing a non-volatile memory element as described in claim 5, characterized in that, The height of the first portion of the etched dielectric material layer is lower than the height of the at least one floating gate.

8. The method for manufacturing a non-volatile memory element as described in claim 5, characterized in that, The outer surfaces of the first portion and the second portion of the etched dielectric material layer are lower than a bottom surface of the at least one upper gate structure.

9. The method for manufacturing a non-volatile memory element as described in claim 5, characterized in that, The first and second portions of the etched dielectric material layer are separated from the sidewall of the at least one upper gate structure.

10. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, The portion of the etched dielectric material layer disposed between the at least one upper gate structure and the substrate covers the lateral sidewall of the at least one floating gate.

11. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, Further includes: The dielectric material layer is planarized before etching it; as well as The dielectric material layer is etched to form the etched dielectric material layer with a flat top surface.

12. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, The dielectric material layer is a conformal layer.

13. The method for manufacturing a non-volatile memory element as described in claim 12, characterized in that, The etched dielectric material layer includes a gap wall structure that covers the curved sidewall of the at least one floating gate.

14. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, The width of at least one upper gate structure is smaller than the width of the auxiliary gate.

15. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, A portion of the etched dielectric material layer is disposed between the auxiliary gate and the at least one upper gate structure.

16. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, Further, it includes removing the etched dielectric material layer to expose a bottom surface of the at least one upper gate structure.

17. The method for manufacturing a non-volatile memory element as described in claim 16, characterized in that, After forming the at least one upper gate structure, the process further includes forming an intermediate gate structure on the at least one floating gate, wherein a portion of the intermediate gate structure is disposed between the at least one upper gate structure and the substrate.

18. The method for manufacturing a non-volatile memory element as described in claim 17, characterized in that, The curved sidewall of the at least one floating gate is covered by the intermediate gate structure.

19. The method for manufacturing a non-volatile memory element as described in claim 17, characterized in that, The intermediate gate structure includes an inter-gate dielectric and a control gate, and the inter-gate dielectric is continuously disposed on the bottom surface of the at least one upper gate structure and the transverse sidewall of the at least one floating gate.

20. The method for manufacturing a non-volatile memory element as described in claim 1, characterized in that, After forming the at least one stacked structure, the process further includes forming a shared source region in the substrate. The at least one stacked structure includes two stacked structures, the at least one floating gate includes two floating gates, and the at least one upper gate structure includes two upper gate structures. The non-volatile memory element includes two memory cells, each including at least one stacked structure, at least one floating gate, at least one upper gate structure, and a shared source region, and the two memory cells are mirror-symmetric to each other.

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