A processing method of a GPP process chip

Abstract

The present application relates to chip processing technical field, specifically to a kind of GPP process chip processing method, including the following steps: to incoming material silicon wafer sequentially through double-sided oxidation treatment, once photoetching development processing, shallow etching groove, after secondary photoetching development processing, deep etching groove, deposit polysilicon protective film, deposit glass passivation layer in groove, deposit oxide layer, after third photoetching development processing, rinse and remove surface excess film, groove outer plating metal layer, i.e. GPP process chip is obtained;Wherein, the depth of shallow etching groove is 10 μm±2 μm;The depth of deep etching groove is 45~48% of the thickness of silicon wafer.The processing method of the present application first carries out pre-etching shallow etching groove, is conducive to subsequent etching alignment accuracy, and the overall process of silicon wafer warping deformation is small, can avoid pressing etching mask to correct skew, offset and other problems, can improve etching precision, reduce the broken piece rate, improve the consistency and reliability of product pattern.

Description

Technical Field

[0001] This invention relates to the field of chip fabrication technology, and more specifically to a method for fabricating GPP process chips. Background Technology

[0002] GPP (Glass-Passivated Panel) chips, also known as GPP devices, are indispensable components in power electronic equipment. The term broadly refers to all active devices that incorporate or utilize junction film protection technology; it is a general term for glass-passivated devices. Because glass passivation is particularly effective for planar diodes with exposed junction interfaces and has been widely adopted, GPP has gradually become synonymous with "glass-passivated diode." GPP diodes are highly favored due to their superior resistance to external stress and thermal shock, high-temperature performance, excellent overall performance, and suitability for mass production. They are currently widely used in household appliances, electronic instruments, precision equipment, rail transportation, data transmission, and communication systems.

[0003] The GPP process can be summarized as follows: high-temperature oxidation of silicon wafers → first photolithography → etching and grooving → deposition of SIPOS polysilicon protective film → glass coating at the grooving area → passivation sintering → second photolithography → removal of SIPOS and glass passivation outside the grooving area → metal plating. However, this process frequently encounters overlay misalignment and abnormal overlay patterns. The industry has high requirements for linewidth, which necessitates continuously improving overlay accuracy during photolithography, especially for multi-layered, high-precision lithography. Figure One Generally, multiple exposures are required to complete the fabrication process, and each exposure requires a different mask. Before using each mask for exposure, it must be precisely aligned with the previously exposed pattern before proceeding with subsequent operations. Only in this way can the correct relative position of each layer be guaranteed; this is called overlay. Therefore, to avoid overlay misalignment and abnormal overlay patterns, the overlay mask is often pressed during the current overlay process to correct misalignment and prevent pattern abnormalities. However, frequent pressing of the overlay mask can easily cause silicon wafer deformation, edge warping, or breakage. If the misalignment is not corrected, it will affect the consistency and reliability of the final chip product. Summary of the Invention

[0004] To address the technical problem of poor product consistency and reliability caused by overlay misalignment leading to pattern abnormalities, this invention provides a method for processing chips using GPP (Glass Plate Processing). This method avoids the problem of misalignment and deviation during secondary overlay caused by chip deformation after the first slotting, thus improving product consistency and reliability.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution:

[0006] A method for processing GPP process chips includes the following steps: the incoming silicon wafer is subjected to double-sided oxidation treatment, a first photolithography and development treatment, shallow etching trenching, a second photolithography and development treatment followed by deep etching trenching, deposition of a polysilicon protective film layer, deposition of a glass passivation layer in the trench, deposition of an oxide layer, a third photolithography and development treatment followed by rinsing to remove excess film layer on the surface, and plating of a metal layer outside the trench to obtain the GPP process chip.

[0007] The shallow etching groove has a depth of 10μm±2μm; the deep etching groove has a depth of 45-48% of the silicon wafer thickness.

[0008] Furthermore, the fabrication method of the GPP process chip specifically includes the following steps:

[0009] S1. Double-sided oxidation: A silicon wafer having P-regions and N-regions is subjected to double-sided oxidation to obtain a first oxide layer on both surfaces of the silicon wafer;

[0010] S2. First photolithography and development process: Photoresist is coated on both sides, baked, aligned and exposed to ultraviolet light, developed, and thermally cured to complete the first photolithography and development process and obtain the pre-grooved pattern.

[0011] S3. Shallow etching trenching: Shallow etching trenching is performed on the surface of the P-type region of the silicon wafer obtained after step S2 to obtain a pre-formed trench. The depth of the shallow etching trenching is 10μm±2μm.

[0012] S4. Deep etching trenching after secondary photolithography and development: Photoresist is coated on one side of the silicon wafer surface to obtain the pre-formed trench. After baking, it is aligned and exposed to ultraviolet light and developed. Then, deep etching trenching is performed. After thermal curing, the formed trench is obtained. The depth of the deep etching trench is 45-48% of the thickness of the silicon wafer.

[0013] S5, Deposition of polycrystalline silicon protective film: Double-sided vapor phase deposition of polycrystalline silicon protective film;

[0014] S6. Deposit a glass passivation layer: Electrophoretically deposit a glass layer in the forming trench and sinter it to obtain a glass passivation layer;

[0015] S7. Deposition yields a second oxide layer;

[0016] S8. After three photolithography and development processes, rinse to remove excess film layer on the surface: Photoresist is coated on one side of the silicon wafer with the polycrystalline silicon protective film layer, the glass passivation layer and the second oxide layer. After baking, it is aligned and exposed to ultraviolet light, developed, rinsed and etched to remove excess film layer on the outer surface of the trench.

[0017] S9. A metal layer is plated on the outside of the trench to obtain the GPP process chip.

[0018] Furthermore, the conditions for the double-sided oxidation are as follows: the temperature of the thermal oxidation furnace is raised from room temperature to 600–850°C, then the silicon wafer is pushed into the furnace, the oxygen flow rate is set at 100–200 sccm, and then the temperature is further raised to 1200°C. After reacting at a constant temperature for 30–40 minutes, the oxygen is turned off, and the temperature is lowered to 600°C at a rate of 3–5°C / min before the wafer is removed from the furnace. Oxygen diffuses and reacts on the surface of the silicon wafer to obtain a silicon dioxide film. This film performs gettering on the silicon wafer during its formation, especially removing metal ion impurities. It also isolates external impurities and improves the adhesion of subsequent photoresist.

[0019] Furthermore, the baking temperature in steps S2, S4, and S8 is 85–110°C, and the time is 10–30 min; the thermal curing temperature in steps S2 and S4 is 120–130°C, and the time is 10–30 min. The former baking process is to evaporate the organic solvent in the photoresist, increasing the precision of subsequent alignment exposure. After development, the photoresist needs to be cured to ensure a firm bond between the photoresist and the silicon wafer and prevent deformation.

[0020] Furthermore, the corrosion solution used for the shallow corrosion trench is a first mixed acid, the corrosion temperature is -2 to -4℃, and the corrosion time is 1 to 2 minutes. The first mixed acid is prepared by mixing nitric acid, hydrofluoric acid, and glacial acetic acid in a volume ratio of 18:1:1.

[0021] The corrosion solution used for the deep corrosion trench is a second mixed acid, with a corrosion temperature of -2 to -4℃ and a corrosion time of 6 to 30 minutes. The second mixed acid is prepared by mixing nitric acid, hydrofluoric acid, glacial acetic acid and sulfuric acid in a volume ratio of 9:10:12:5.

[0022] Furthermore, the conditions for depositing the polycrystalline silicon protective film are as follows: using silane as a reactant and nitrous oxide as a dopant, reacting for 80 min at an LPCVD furnace temperature of 650–700 °C and a gas pressure of 0.9–1.0 Pa, wherein the silane flow rate is 200–250 sccm and the nitrous oxide flow rate is 40–50 sccm.

[0023] Furthermore, the conditions for depositing the glass passivation layer are as follows: the silicon wafer and the counter electrode are placed in an electrophoresis tank, and the glass powder is deposited in the trench under the action of a DC electric field in the electrophoresis solution containing glass powder. After being taken out and dried, it is pre-formed at 500-650°C for 30 minutes, and then heated to 750-850°C for thermoforming and sintering for 20 minutes to obtain the glass passivation layer in the trench.

[0024] Furthermore, the process of depositing the oxide layer in the trench is as follows: silane and oxygen are introduced into the LPCVD furnace at a temperature of 350-450℃ and a pressure of 0.1-0.3Pa for 40 minutes to react.

[0025] Furthermore, in step S8, the rinsing corrosion is carried out by a third mixed acid corrosion to remove the excess film layer on the surface. The third mixed acid is prepared by ammonium fluoride and hydrofluoric acid in a volume ratio of 7:1. The rinsing temperature is 38±2℃ and the rinsing time is 100~140s. In step S9, the material of the metal layer is nickel and / or gold.

[0026] Beneficial technical effects: The method of this invention first performs double-sided oxidation on the incoming silicon wafer, followed by a single photolithography process. This involves shallow etching to create trenches, followed by a second photolithography process for deep etching to create trenches. A polysilicon protective film is then deposited, followed by a glass layer and sintering to obtain a glass passivation layer. During sintering, the photoresist remaining from the previous process detaches along with the outer surface film of the trench. At this point, the structure inside the trench, from the inside out, consists of a polysilicon protective film and a glass passivation layer, while the outer surface is a first oxide layer. Next, a second oxide layer is deposited. The structure inside the trench, from the inside out, consists of a polysilicon protective film, a glass passivation layer, and a second oxide layer, while the outer surface consists of the first oxide layer and the second oxide layer. Finally, three photolithography washes are performed to remove the surface oxide layer, exposing the silicon wafer outside the trench. A metal layer is then deposited on the surface to obtain ohmic contacts, resulting in a GPP process chip. The processing method of the present invention first performs pre-overlay shallow etching and slotting, which is beneficial to the accuracy of subsequent overlay alignment. In addition, the silicon wafer warping deformation is small in the whole process, which can avoid the use of mask templates to correct skew and misalignment during pressing overlay. This can improve overlay accuracy, reduce wafer breakage rate, and improve the consistency and reliability of product patterns. Attached Figure Description

[0027] Figure 1 This is a cross-sectional view of the chip after processing in step S1;

[0028] Figure 2 This is a cross-sectional view of the chip after the S2 step.

[0029] Figure 3 This is a cross-sectional view of the chip after processing in step S3;

[0030] Figure 4 This is a cross-sectional view of the chip after processing in step S4;

[0031] Figure 5 This is a cross-sectional view of the chip after processing in step S5;

[0032] Figure 6 This is a cross-sectional view of the chip after processing in step S6;

[0033] Figure 7 This is a cross-sectional view of the chip after processing in step S7;

[0034] Figure 8 This is a cross-sectional view of the chip after development in step S8;

[0035] Figure 9 This is a cross-sectional view of the chip after the subsequent rinsing and etching process in step S8.

[0036] Figure 10 This is a cross-sectional view of the final chip structure.

[0037] Wherein 1-silicon wafer, 2-first oxide layer, 31-first photoresist layer, 32-second photoresist layer, 33-third photoresist layer, 4-pre-formed trench, 5-formed trench, 6-polysilicon protective film layer, 7-glass passivation layer, 8-second oxide layer, 9-metal layer. Detailed Implementation

[0038] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present invention or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] Unless otherwise specifically stated, the numerical values ​​set forth in these embodiments do not limit the scope of the invention. Techniques and methods known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques and methods should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0040] Experimental methods not specifically described in the following examples are generally determined according to national standards; if no corresponding national standard exists, they are performed according to generally accepted international standards or the standards proposed by relevant enterprises. Unless otherwise stated, all parts are parts by weight, and all percentages are weight percentages.

[0041] Example 1

[0042] A method for fabricating a GPP process chip includes the following steps: the incoming silicon wafer is subjected to double-sided oxidation treatment, a first photolithography and development treatment, shallow etching trenching, a second photolithography and development treatment followed by deep etching trenching, deposition of a polycrystalline silicon protective film layer, deposition of a glass passivation layer in the trench, deposition of an oxide layer, a third photolithography and development treatment followed by rinsing to remove excess film layer from the surface, and plating of a metal layer on the outside of the trench, thereby obtaining the GPP process chip.

[0043] The specific processing method includes the following steps:

[0044] S1. Double-sided oxidation: The silicon wafer 1, which has P+ and N+ regions, is subjected to double-sided oxidation to obtain a first oxide layer 2 (approximately 3000 angstroms thick) on both surfaces of the silicon wafer; the cross-sectional view of the chip after step S1 is shown below. Figure 1 As shown;

[0045] The temperature of the thermal oxidation furnace is raised from room temperature to 800°C. The silicon wafer is then pushed into the furnace. Under nitrogen protection, the oxygen flow rate is set to 166 sccm. The temperature is then raised to 1200°C and kept at a constant temperature for 30 minutes. After that, the oxygen is turned off and the temperature is lowered to 600°C at a rate of 4°C / min before the wafer is removed from the furnace.

[0046] S2, First Photolithography and Development Process: Photoresist is coated on both sides, baked at 100℃ for 20 minutes, then aligned and exposed to ultraviolet light, developed in developer, and thermally cured at 120℃ for 20 minutes to complete the first photolithography and development process, obtaining the first photoresist layer 31 with a pre-grooved pattern; the chip cross-section after step S2 is shown below. Figure 2 As shown;

[0047] S3. Shallow etching trenching: Shallow etching trenching is performed on the surface of the P-type region of the silicon wafer obtained after step S2 to obtain pre-formed trench 4. The depth of the shallow etching trenching is 10μm±2μm.

[0048] The corrosion solution used for the shallow corrosion trenching is a first mixed acid, with a corrosion temperature of -2 to -4℃ and a corrosion time of 1 to 2 minutes. The first mixed acid is prepared by mixing nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 18:1:1.

[0049] The chip cross-section diagram after processing in step S3 is as follows: Figure 3 As shown;

[0050] S4. Deep etching trenching after secondary photolithography and development: Photoresist is coated on one side of the silicon wafer surface that has obtained the pre-formed trench 4. After baking at 100°C for 20 minutes, it is aligned and exposed to ultraviolet light and developed to obtain the second photoresist layer 32. Then, deep etching trenching is performed, and the pre-formed trench 5 is obtained after thermal curing at 120°C for 20 minutes. The depth of the deep etching trench is controlled to be 45-48% of the thickness of the silicon wafer by the etching time.

[0051] The corrosion solution used for the deep corrosion trenching is a second mixed acid, with a corrosion temperature of -2 to -4℃ and a corrosion time of 10 to 20 minutes. The second mixed acid is prepared by mixing nitric acid, hydrofluoric acid, glacial acetic acid and sulfuric acid in a volume ratio of 9:10:12:5.

[0052] The chip cross-section diagram after processing in step S4 is as follows. Figure 4 As shown;

[0053] S5. Deposition of a polycrystalline silicon protective film: Using silane as a reactant and nitrous oxide as a dopant, the reaction is carried out for 80 minutes at an LPCVD furnace temperature of 700℃ and a pressure of 0.9Pa, wherein the silane flow rate is 215 sccm and the nitrous oxide flow rate is 45 sccm, to obtain a polycrystalline silicon protective film 6 on the surface; the chip cross-section after step S5 is shown below. Figure 5 As shown;

[0054] S6. Depositing a glass passivation layer: A glass layer is electrophoretically deposited in the forming trench and sintered to obtain the glass passivation layer 7; the chip cross-section after step S6 is shown below. Figure 6 As shown;

[0055] The silicon wafer and the counter electrode are placed in an electrophoresis tank. The electrophoretic solution containing glass powder is used to deposit the glass powder in the forming groove 5 under the action of a DC electric field. After drying, the wafer is pre-formed at 500℃ for 20 minutes, and then heated to 800℃ for thermal forming and sintering for 30 minutes to obtain a glass passivation layer 7 in the forming groove 5. During the sintering process, the photoresist is removed and its surface layer falls off.

[0056] S7. Deposition of oxide layer: Silane and oxygen are introduced into the LPCVD furnace at 400℃ and 0.2Pa for 40 minutes to obtain the second oxide layer 8; the cross-sectional view of the chip after step S7 is shown below. Figure 7 As shown;

[0057] S8. Rinsing to remove excess film layer after three photolithography and development processes: Photoresist is coated on one side of the silicon wafer surface containing the polycrystalline silicon protective film layer 6, the glass passivation layer 7, and the second oxide layer 8. After baking at 100°C for 20 minutes, it is aligned and exposed to ultraviolet light and developed to obtain the third photoresist layer 33. The chip cross-section after development in step S8 is shown below. Figure 8 As shown, rinsing and etching remove excess film from the outer surface of the trench;

[0058] The rinsing etching process involves a third mixed acid etching step to remove excess film from the surface. This third mixed acid is prepared by mixing ammonium fluoride and hydrofluoric acid at a volume ratio of 7:1. The rinsing temperature is 38±2℃, and the rinsing time is 100–140 s. The cross-sectional view of the chip after the subsequent rinsing etching step S8 is shown below. Figure 9 As shown;

[0059] S9. Deposit a metal layer 9 outside the trench to obtain the GPP process chip. The final chip structure cross-sectional view is shown below. Figure 10 As shown.

[0060] Comparative Example 1

[0061] The GPP process for chip fabrication is as follows: fabrication of a first oxide layer on the silicon wafer surface → first photolithography and development process → etching and trenching (the trench depth is consistent with the deep etching trenching in Example 1) → deposition of a polysilicon protective film → fabrication of a glass passivation layer → fabrication of a second oxide layer → second photolithography → removal of the film layer outside the trench area → metal plating; the process parameters are consistent with those in Example 1.

[0062] The chips fabricated above were tested, and the results are shown in Table 1.

[0063] Table 1 Comparison of Chip Manufacturing Processes

[0064]

[0065] As shown in Table 1, the method of the present invention first performs shallow etching and then deep etching. The shallow etching and pre-etching is beneficial to the accuracy of subsequent overlay alignment. In addition, the silicon wafer warping deformation is small in the whole process, which can avoid the use of mask templates to correct skewness and misalignment during pressing and overlay, thereby reducing the breakage rate and improving the consistency and reliability of product patterns.

[0066] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a GPP (Glass Process Technology) chip, characterized in that, The GPP process chip fabrication method specifically includes the following steps: S1. Double-sided oxidation: A silicon wafer having P-regions and N-regions is subjected to double-sided oxidation to obtain a first oxide layer on both surfaces of the silicon wafer; S2. First photolithography and development process: Photoresist is coated on both sides, baked, aligned and exposed to ultraviolet light, developed, and thermally cured to complete the first photolithography and development process and obtain the pre-grooved pattern. S3. Shallow etching trenching: Shallow etching trenching is performed on the surface of the P-type region of the silicon wafer obtained after step S2 to obtain a pre-formed trench. The depth of the shallow etching trenching is 10μm±2μm. S4. Deep etching trenching after secondary photolithography and development: Photoresist is coated on one side of the silicon wafer surface that has obtained the pre-formed trench. After baking, it is aligned and exposed to ultraviolet light and developed. Then, deep etching trenching is performed. After thermal curing, the formed trench is obtained. The depth of the deep etched trench is 45-48% of the thickness of the silicon wafer; S5, Deposition of polycrystalline silicon protective film: Double-sided vapor phase deposition of polycrystalline silicon protective film; S6. Deposit a glass passivation layer: Electrophoretically deposit a glass layer in the forming trench and sinter it to obtain a glass passivation layer; S7. Deposition yields a second oxide layer; S8. After three photolithography and development processes, rinse to remove excess film layer on the surface: Photoresist is coated on one side of the silicon wafer with the polycrystalline silicon protective film layer, the glass passivation layer and the second oxide layer. After baking, it is aligned and exposed to ultraviolet light, developed, rinsed and etched to remove excess film layer on the outer surface of the trench. S9. A metal layer is plated on the outside of the trench to obtain the GPP process chip.

2. The method for fabricating a GPP process chip according to claim 1, characterized in that, The conditions for the double-sided oxidation are as follows: the temperature of the thermal oxidation furnace is raised from room temperature to 600-850°C, then the silicon wafer is pushed into the furnace, the oxygen flow rate is set at 100-200 sccm, and then the temperature is raised to 1200°C. After the reaction is kept at a constant temperature for 30-40 minutes, the oxygen is turned off, and the temperature is lowered to 600°C at a rate of 3-5°C / min before the wafer is removed from the furnace.

3. The method for fabricating a GPP process chip according to claim 1, characterized in that, The baking temperature in steps S2, S4, and S8 is 85–110°C and the time is 10–30 min; the heat curing temperature in steps S2 and S4 is 120–130°C and the time is 10–30 min.

4. The method for fabricating a GPP process chip according to claim 1, characterized in that, The corrosion solution used for the shallow corrosion trench is a first mixed acid, with a corrosion temperature of -2 to -4℃ and a corrosion time of 1 to 2 minutes. The first mixed acid is prepared by mixing nitric acid, hydrofluoric acid and glacial acetic acid in a volume ratio of 18:1:

1. The corrosion solution used for the deep corrosion trench is a second mixed acid, with a corrosion temperature of -2 to -4℃ and a corrosion time of 6 to 30 minutes. The second mixed acid is prepared by mixing nitric acid, hydrofluoric acid, glacial acetic acid and sulfuric acid in a volume ratio of 9:10:12:

5.

5. The method for fabricating a GPP process chip according to claim 1, characterized in that, The conditions for depositing the polycrystalline silicon protective film are as follows: using silane as a reactant and nitrous oxide as a dopant, reacting for 80 min at an LPCVD furnace temperature of 650–700 °C and a gas pressure of 0.9–1.0 Pa, wherein the silane flow rate is 200–250 sccm and the nitrous oxide flow rate is 40–50 sccm.

6. The method for fabricating a GPP process chip according to claim 1, characterized in that, The conditions for depositing the glass passivation layer are as follows: the silicon wafer and the counter electrode are placed in an electrophoresis tank, and the glass powder is deposited in the trench under the action of a DC electric field in the electrophoresis solution containing glass powder. After drying, the glass powder is pre-formed at 500-650°C for 30 minutes, and then heated to 750-850°C for thermoforming and sintering for 20 minutes to obtain the glass passivation layer in the trench.

7. The method for fabricating a GPP process chip according to claim 1, characterized in that, The process of depositing the oxide layer in the trench is as follows: silane and oxygen are introduced into the LPCVD furnace at a temperature of 350-450℃ and a pressure of 0.1-0.3Pa for 40 minutes.

8. The method for fabricating a GPP process chip according to claim 1, characterized in that, The rinsing corrosion in step S8 uses a third mixed acid corrosion to remove excess film from the surface. The third mixed acid is ammonium fluoride and hydrofluoric acid prepared in a volume ratio of 7:

1. The rinsing temperature is 38±2℃ and the rinsing time is 100~140s. The material of the metal layer in step S9 is nickel and / or gold.

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