A full-gate nanosheet CMOS device integration method

Abstract

The application discloses a kind of full gate-all-around nanosheet CMOS device integration methods, belong to super large scale integrated circuit manufacturing technical field.The application is after forming pseudo gate and outer spacer, form second outer spacer, by filling the same dielectric material as second outer spacer in inner spacer recess, using cyclic etching process, second outer spacer and the Si / inner spacer under it are etched and removed along the same interface, to form the final inner spacer.Compared with the existing method of forming inner spacer by single outer spacer, the second outer spacer method proposed in the application, the structural parameters of the inner spacer and the gate length are completely determined by the pseudo gate length, the first outer spacer thickness and the SiGe etching amount.Moreover, the structure formed in N / P type area remains consistent, effectively avoiding process differences and wafer-to-wafer fluctuations between N / P type devices.

Description

Technical Field

[0001] This invention belongs to the field of ultra-large-scale integrated circuit manufacturing technology, and in particular relates to a method for integrating CMOS devices with fully enclosed gate nanosheets. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, nanosheet devices with a gate-all-around (GAA) structure have become a new generation of highly promising semiconductor devices.

[0003] With the continuous miniaturization of semiconductor devices, the fabrication process directly impacts device performance and reliability. However, the fabrication of fully enclosed gate nanosheet devices is becoming increasingly challenging, with bottlenecks remaining in some key process steps.

[0004] The formation process of the inner sidewalls in a fully enclosed gate nanosheet device structure is one of the key steps in device integration. The inner sidewalls have a direct impact on the parasitic resistance and parasitic capacitance of the device.

[0005] Currently, the mainstream fabrication method for GAA inner sidewall formation involves first performing source-drain etch-back after the dummy gate and outer sidewalls are formed to expose the silicon (Si) / silicon germanium (SiGe) superlattice sidewalls. Next, dry etching is used to selectively etch SiGe, creating localized depressions. Then, chemical vapor deposition (CVD) is used to fill the dielectric material. Finally, dry anisotropic etching is used to remove excess dielectric covering the sidewalls, leaving the dielectric filling the depressions as the inner sidewalls.

[0006] However, if this method is used to form the inner wall of GAA nanosheet devices, the following problem will occur:

[0007] (1) To ensure successful source-drain epitaxy, this method requires the removal of the natural oxide layer on the sidewalls. This step results in dielectric loss for the inner sidewall structure, and when the inner sidewall thickness is small, it can easily cause a source-drain-gate electrode short circuit.

[0008] (2) To form the NP epitaxial source and drain, this method requires covering the N-type region with an epitaxial protective layer. After the P-type device epitaxy is completed, the protective layer needs to be completely removed, which may cause complete destruction of the inner sidewall of the N-type device. Therefore, a secondary inner sidewall process is required for the N-type device, resulting in process differences and inter-wafer fluctuations between N / P type devices.

[0009] Therefore, the industry urgently needs a method for forming the inner walls of grid-enclosed nanosheet devices. Summary of the Invention

[0010] To address the shortcomings of existing technologies, this invention provides a method for integrating fully enclosed gate nanosheet CMOS devices. The core of this method lies in the fact that the structural parameters of the inner sidewall + gate length of the device are completely determined by the pseudo-gate length, sidewall thickness, and SiGe selective etching amount.

[0011] The technical solution provided by this invention is as follows:

[0012] A method for integrating a fully enclosed gate nanosheet CMOS device includes the following steps:

[0013] A. Provide a semiconductor substrate and fabricate it according to existing processes to form a pseudo-gate of a GAA nanosheet device, wherein the pseudo-gate width defines the channel length of the GAA nanosheet device;

[0014] B. Two outer walls, 1 and 2, are formed on both sides of the pseudo-gate; the specific implementation steps are as follows:

[0015] B1. Deposit a dielectric layer as the outer wall 1, the thickness of which and the width of the dummy gate are jointly defined in the superlattice structure retention width of the source-drain etch-back step;

[0016] B2. Deposit a dielectric layer as the outer wall 2; wherein, the dielectric in B2 should have an etching selectivity ratio greater than 5:1 with the dielectric in B1, and the dielectric in B2 should have a smaller selectivity ratio with the Si channel. Furthermore, the deposition thickness of the outer wall 2 should be moderate; if the thickness is too thin, the removal of the outer wall 2 and the inner wall cannot be stably controlled; if the thickness is too thick, it may result in a slow removal rate and incomplete material removal.

[0017] C. Remove the superlattice of the source / drain regions exposed outside the outer wall; the specific implementation steps are as follows:

[0018] C1. Deposit a dielectric layer as an etching mask to protect the dummy gate and sidewall structure;

[0019] C2. The source drain back-etching window is exposed by photolithography etching;

[0020] C3. The exposed Si / SiGe superlattice stack is removed by anisotropic etching, and the source-drain back etching is completed.

[0021] C4. Selectively remove the dielectric layer described in C1;

[0022] D. Selectively etch SiGe using isotropic etching to form an inner wall recess; the depth of this recess is greater than the thickness of the outer wall 2, and the distance between the recess depth and the edge of the outer wall 1 defines the width of the inner wall.

[0023] The etching process should ensure that the SiGe to Si selection ratio is greater than 5:1;

[0024] E. Fill the depressions with a deposition medium material to serve as the inner wall;

[0025] The dielectric material described in E is the same as the dielectric material described in B2;

[0026] F. Remove the material from the outer wall 2 of the P-type device region and its vertically downward portion to expose the Si channel;

[0027] The specific implementation steps are as follows:

[0028] F1. Deposit a layer of hard mask dielectric, etch the hard mask dielectric of the P-type device region by photolithography, and retain the hard mask dielectric of the N-type region;

[0029] F2. The inner and outer walls 2 in the P-type device region are removed by photolithography etching to expose the Si channel;

[0030] G. Forming the source / drain region and its protective layer for the P-type device;

[0031] The specific implementation steps are as follows:

[0032] G1. Remove the natural oxide layer on the sidewall by wet etching;

[0033] G2. Electrode layers are epitaxially grown on both sides of the exposed Si channel to form the source and drain of the device, and the source and drain impurities of the N / PMOS are activated by annealing process;

[0034] G3. A protective dielectric layer is deposited through chemical vapor deposition.

[0035] H. Remove the outer wall 2 of the N-type device region to form an inner wall structure consistent with the PMOS structure;

[0036] The specific implementation steps are as follows:

[0037] H1. Remove the surface dielectric protective layer of the N-type device region by dry etching;

[0038] H2. Deposit a layer of hard mask dielectric, etch the hard mask dielectric in the N-type device region by photolithography, and retain the hard mask dielectric in the P-type region;

[0039] H3. The outer wall 2 and its vertically downward portion in the N-type device region are removed by photolithography etching to expose the Si channel;

[0040] H4. Remove the natural oxide layer on the sidewalls by wet etching;

[0041] H5. Electrode layers are epitaxially grown on both sides of the exposed Si channel to form the source and drain of N-type devices, and the source and drain impurities of N / PMOS are activated by annealing process.

[0042] H6. A dielectric protective layer is deposited by chemical vapor deposition to form an inner sidewall structure consistent with the PMOS structure;

[0043] I. The device integration will be completed using the existing back-end processes.

[0044] Furthermore, the structural parameters described in this invention (such as the thickness and material of outer wall 1 and outer wall 2, corrosion depth, thickness and material of hard mask and protective layer, etc.) are all set according to the specific device performance requirements.

[0045] Furthermore, the semiconductor substrate described in A includes bulk silicon substrates, SOI substrates, bulk germanium substrates, GOI substrates, compound substrates, etc.

[0046] Furthermore, in the deposition step described in E, to ensure good interfacial properties, good thermal stability, and good chemical stability between the dielectric materials, the preferred deposition method is atomic layer deposition (ALD), which has good conformal properties.

[0047] The advantages and positive effects of this invention are as follows:

[0048] The specific advantages of using the preparation process of this invention are as follows:

[0049] 1) Compared with existing methods that form inner walls using a single-layer outer wall, the proposed secondary outer wall method can precisely control the size of the inner wall and the grid length. The structural parameters of the inner wall and the grid length are entirely determined by the pseudo-grid length, the thickness of outer wall 1, and the SiGe etching amount;

[0050] 2) When the selective etching amount of SiGe is greater than the thickness of the second outer wall, the present invention has a very stable process window and the structure formed in the N / P type region is consistent, which will not cause process differences and inter-wafer fluctuations between N / P type devices, thus solving one of the difficulties that are difficult to overcome in the process. Attached Figure Description

[0051] The figures show a schematic diagram of the process for forming the inner sidewall of the proposed gated nanosheet device. In each figure, (a) is a top view, (b) is a cross-sectional view along A-A' in (a), and (c) is a cross-sectional view along B-B' in (a).

[0052] in:

[0053] Figure 1 Forming a pseudogate for GAA nanosheet devices;

[0054] Figure 2 Forming a secondary outer wall;

[0055] Figure 3 Remove the source and drain components;

[0056] Figure 4 This creates a recess in the inner wall.

[0057] Figure 5 Fill the depressions to form the inner wall;

[0058] Figure 6 Form a hard mask;

[0059] Figure 7 Hard mask covers N-type regions;

[0060] Figure 8 The second outer wall of the P-type GAA nanosheet device was removed by photolithography;

[0061] Figure 9 Forming source and drain sources for P-type GAA nanosheet devices;

[0062] Figure 10 Form a source / drain protection layer;

[0063] Figure 11 Remove the hard mask from the N-type region;

[0064] Figure 12 Forming a hard mask for P-type devices;

[0065] Figure 13 Hard mask covers the P-type region;

[0066] Figure 14 The second outer wall of the N-type GAA nanosheet device was removed by photolithography;

[0067] Figure 15 Forming source and drain sources for N-type GAA nanosheet devices;

[0068] Figure 16 Forming source and drain protection layers for N-type devices;

[0069] Figure 17 Remove the hard mask from the P-type device region;

[0070] Figure 18 For Figures 1 to 17 Legend of the diagram. Detailed Implementation

[0071] The present invention will now be described in detail with reference to the accompanying drawings and specific examples.

[0072] N / P integration of GAA nanosheet devices can be achieved by following these steps:

[0073] 1) A three-cycle Si / SiGe superlattice and shallow trench isolation (STI) of SiO2 are formed on a (100) bulk silicon substrate using a disclosed bulk silicon process. The surface is planarized by chemical-mechanical polishing (CMP), and a 6nm thick pseudo-gate is formed by one-step photolithography. Figure 1 As shown; the pseudo-gate width defines the channel length of the GAA nanosheet device.

[0074] 2) A 9nm thick Si3N4 first layer outer wall 1 is formed on both sides of the dummy gate by PECVD deposition; the thickness of the outer wall 1 and the width of the dummy gate together define the superlattice structure retention width in the source-drain etch-back step.

[0075] 3) A 3nm thick SiOC layer is formed on the surface of the first outer wall 1 by PECVD deposition as the second outer wall 2. Figure 2 As shown, the dielectric material used in the outer wall 2 has an etching selectivity ratio greater than 5:1 compared to the dielectric material used in the outer wall 1, and the dielectric material used in the outer wall 2 has a smaller selectivity ratio compared to the Si channel.

[0076] 4) The Si / SiGe superlattice exposed outside the second outer wall 2 and located in the source / drain region is removed by photolithography and anisotropic etching, such as... Figure 3 As shown.

[0077] 5) Selective etching of the superlattice material SiGe using isotropic etching to a depth of 6 nm creates inner sidewall depressions, such as... Figure 4 As shown; the etching process should ensure that the SiGe to Si selection ratio is greater than 5:1, the recess depth is greater than the thickness of the outer wall 2, and the recess depth and the edge distance of the outer wall 1 define the width of the inner wall.

[0078] 6) A 6nm thick SiOC is deposited via ALD to fill the depressions and form inner sidewalls, such as... Figure 5 As shown.

[0079] 1) SiCN is deposited via PECVD to cover the entire device surface as a hard mask, such as... Figure 6 As shown;

[0080] 2) Remove SiCN from the surface of the P-type device region by photolithography etching, such as... Figure 7 As shown;

[0081] 3) By photolithography and anisotropic etching, the 3nm thick outer wall of the SiOC in the P-type device and its vertically downward portion are removed to expose the Si channel, such as... Figure 8 As shown;

[0082] 4) After removing the natural oxide layer on the sidewalls by wet etching, epitaxial growth is performed to grow 6nm thick N-type doped SiGe layers on both sides of the exposed Si channel, forming the source and drain of the P-type device, such as... Figure 9 As shown;

[0083] 5) Activate the source and drain impurities of N / PMOS through annealing process;

[0084] 6) A 2nm thick Si layer is deposited on the source and drain surfaces using LPCVD to form source and drain protection for P-type devices, such as... Figure 10 As shown;

[0085] 7) Remove the SiCN hard mask on the surface of the N-type device by dry etching, such as... Figure 11 As shown;

[0086] 8) SiCN is deposited via PECVD to cover the entire device surface as a hard mask, such as... Figure 12 As shown;

[0087] 9) The SiCN on the surface of the N-type device region is removed by photolithography etching, and a hard mask is applied to the surface of the P-type region as a protective layer, such as... Figure 13 As shown;

[0088] 10) By photolithography and anisotropic etching, the 3nm thick outer wall of the SiOC in the N-type device and its vertically downward portion are removed to expose the Si channel, such as... Figure 14 As shown;

[0089] 11) After removing the natural oxide layer on the sidewalls by wet etching, epitaxial growth is performed to grow 6 nm thick P-type doped SiGe layers on both sides of the exposed Si channel, forming the source and drain of the N-type device, such as... Figure 15 As shown;

[0090] 12) Activate the source and drain impurities of N / PMOS through annealing process;

[0091] 13) A 2nm thick Si layer is deposited on the source and drain surfaces using LPCVD to form source and drain protection for P-type devices, such as... Figure 16 As shown;

[0092] 14) Remove the SiCN hard mask on the surface of the N-type device by dry etching, such as... Figure 17 As shown; forming an inner wall structure consistent with the PMOS structure;

[0093] 15) The device integration will be completed according to the publicly disclosed back-end process.

[0094] The embodiments of this invention are not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this invention, or modify them into equivalent embodiments, without departing from the scope of the invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this invention, without departing from the scope of the invention, shall still fall within the protection scope of this invention.

Claims

1. A method for integrating a fully enclosed gate nanosheet CMOS device, comprising the following steps: A. Provide a semiconductor substrate and fabricate it according to existing processes to form a pseudo-gate of a GAA nanosheet device, wherein the pseudo-gate width defines the channel length of the GAA nanosheet device; B. Two outer walls are formed by depositing dielectric material on both sides of the pseudo-gate, namely outer wall 1 and outer wall 2; C. Remove the superlattice of the source / drain regions exposed outside the outer wall; D. Selectively etch SiGe using isotropic etching to form an inner wall recess; the depth of this recess is greater than the thickness of the outer wall 2, and the distance between the recess depth and the edge of the outer wall 1 defines the width of the inner wall. E. The depression is filled with a deposition medium material to serve as the inner wall; the medium material is the same as that used for the outer wall 2; F. Remove the material from the outer wall 2 of the P-type device region and its vertically downward portion to expose the Si channel; G. Forming the source / drain region and its protective layer for the P-type device; H. Remove the outer wall 2 of the N-type device region to form an inner wall structure consistent with the PMOS structure; I. The device integration will be completed using the publicly available back-end process.

2. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The specific steps for step B are as follows: B1. Deposit a dielectric layer as the outer wall 1, the thickness of which and the width of the dummy gate are jointly defined in the superlattice structure retention width of the source-drain etch-back step; B2. Deposit a layer of dielectric material as the outer wall 2; wherein the dielectric material described in B2 should have an etching selectivity ratio greater than 5:1 with the dielectric material described in B1.

3. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The specific steps for step C are as follows: C1. Deposit a dielectric layer as an etching mask to protect the dummy gate and sidewall structure; C2. The source drain back-etching window is exposed by photolithography etching; C3. The exposed Si / SiGe superlattice stack is removed by anisotropic etching, and the source-drain back etching is completed. C4. Selectively remove the dielectric layer described in C1.

4. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The specific steps for step F are as follows: F1. Deposit a layer of hard mask dielectric, etch the hard mask dielectric of the P-type device region by photolithography, and retain the hard mask dielectric of the N-type region; F2. The inner and outer walls 2 in the P-type device region are removed by photolithography etching to expose the Si channel.

5. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, Step G) The specific implementation steps are as follows: G1. Remove the natural oxide layer on the sidewall by wet etching; G2. Electrode layers are epitaxially grown on both sides of the exposed Si channel to form the source and drain of the device, and the source and drain impurities of the N / PMOS are activated by annealing process; G3. A protective dielectric layer is deposited through chemical vapor deposition.

6. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The specific implementation steps for step H are as follows: H1. Remove the surface dielectric protective layer of the N-type device region by dry etching; H2. Deposit a layer of hard mask dielectric, etch the hard mask dielectric in the N-type device region by photolithography, and retain the hard mask dielectric in the P-type region; H3. The outer wall 2 and its vertically downward portion in the N-type device region are removed by photolithography etching to expose the Si channel; H4. Remove the natural oxide layer on the sidewalls by wet etching; H5. Electrode layers are epitaxially grown on both sides of the exposed Si channel to form the source and drain of N-type devices, and the source and drain impurities of N / PMOS are activated by annealing process. H6. A dielectric protective layer is deposited through chemical vapor deposition to form an inner sidewall structure consistent with the PMOS structure.

7. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The semiconductor substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, a GOI substrate, or a compound substrate.

8. The method for integrating a fully enclosed gate nanosheet CMOS device as described in claim 1, characterized in that, The deposition in step E is performed using the atomic layer deposition (ALD) method.

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