semiconductor element

Abstract

A semiconductor device includes a gate structure disposed on a substrate and an epitaxial layer disposed adjacent to the gate structure. The epitaxial layer includes a first buffer layer, a second buffer layer disposed on the first buffer layer, a body layer disposed on the second buffer layer, a first cap layer disposed on the body layer, and a second cap layer disposed on the first cap layer. The first buffer layer includes a planar bottom surface, the second buffer layer includes a curved bottom surface, and the second buffer layer includes a linear sidewall.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a metal-oxide-semiconductor transistor having an epitaxial layer. Background Technology

[0002] To increase the carrier mobility of a semiconductor structure, either compressive or tensile stress can be applied to the gate channel. For example, if compressive stress is required, existing technologies often utilize selective epitaxial growth (SEG) to form an epitaxial structure with the same lattice arrangement as the silicon substrate, such as a silicon-germanium (SiGe) epitaxial structure. Taking advantage of the fact that the lattice constant of the SiGe epitaxial structure is greater than that of the silicon substrate, stress is generated in the channel region of the P-type metal-oxide-semiconductor (MOS) transistor, increasing the carrier mobility in the channel region and thus increasing the speed of the MOS transistor. Conversely, for N-type semiconductor transistors, a silicon-carbon (SiC) epitaxial structure can be formed within the silicon substrate to generate tensile stress in the gate channel region.

[0003] In current transistor fabrication processes using epitaxial growth, grooves are typically formed on both sides of the gate structure before the epitaxial layer is formed within these grooves. However, epitaxial layers formed through epitaxial growth often lack a smooth surface profile, affecting device operation. Therefore, improving existing fabrication processes to overcome these bottlenecks is a crucial challenge. Summary of the Invention

[0004] One embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate and an epitaxial layer disposed next to the gate structure. The epitaxial layer includes a first buffer layer, a second buffer layer disposed on the first buffer layer, a main layer disposed on the second buffer layer, a first cover layer disposed on the main layer, and a second cover layer disposed on the first cover layer. The bottom surface of the first buffer layer includes a flat surface, the bottom surface of the second buffer layer includes a curved surface, and the second buffer layer includes a straight sidewall.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a gate structure disposed on a substrate and an epitaxial layer disposed next to the gate structure. The epitaxial layer includes a first buffer layer, a second buffer layer disposed on the first buffer layer, a host layer disposed on the second buffer layer, a first cover layer disposed on the host layer, and a second cover layer disposed on the first cover layer. The first buffer layer includes an undoped layer, and the second buffer layer includes a germanium concentration gradient. Attached Figure Description

[0006] Figures 1 to 4 This is a schematic diagram of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: Gate Structure

[0010] 16: Gate Structure

[0011] 18: Gate dielectric layer

[0012] 20: Gate material layer

[0013] 22: Hard Mask

[0014] 24: Spacer wall

[0015] 26: Lightly doped drain

[0016] 28: Groove

[0017] 30: Epitaxial layer

[0018] 32: First Buffer Layer

[0019] 34: Second Buffer Layer

[0020] 36: Main body layer

[0021] 38: First covering layer

[0022] 40: Second covering layer

[0023] 42: Source / Drain Region

[0024] 44: Contact hole etching stop layer

[0025] 46: Interlayer dielectric layer

[0026] 48: Dielectric layer

[0027] 50: High dielectric constant dielectric layer

[0028] 52: Work function metal layer

[0029] 54: Low-resistivity metal layer

[0030] 56: Hard Mask

[0031] 58: Contact plug Detailed Implementation

[0032] Please refer to Figures 1 to 4 , Figures 1 to 4 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to a preferred embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, and then at least one gate structure 14, 16 is formed on the substrate. In this embodiment, the gate structures 14, 16 are preferably formed by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer fabrication process, removing part of the hard mask, part of the gate material layer, and part of the gate dielectric layer in a single etch or successive etch step, and then stripping the patterned photoresist to form at least one gate structure 14, 16 on the substrate 12, which is composed of a patterned gate dielectric layer 18, a patterned gate material layer 20, and a patterned hard mask 22. In this embodiment, the number of gate structures 14 and 16 is two, but it is not limited to this. In order to highlight the buffer layer and epitaxial layer formed between the two gate structures 14 and 16, this embodiment only shows part of the gate structures 14 and 16, for example, only the right half of the gate structure 14 and the left half of the gate structure 16.

[0033] In this embodiment, the substrate 12 is, for example, a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The gate dielectric layer 18 may comprise silicon dioxide (SiO2), silicon nitride (SiN), or a high dielectric constant (high-k) material; the gate material layer 20 may comprise conductive materials such as metal materials, polycrystalline silicon, or metal silicides; the hard mask 22 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC), and silicon oxynitride (SiON), but is not limited thereto.

[0034] Furthermore, in one embodiment, it is also possible to pre-form multiple doped wells (not shown) or multiple shallow trench isolations (STIs) for electrical isolation in the substrate 12. Also, although this embodiment uses a planar transistor as an example, in other variations, the semiconductor fabrication process of the present invention can also be applied to non-planar transistors, such as fin-FETs. Figure 1 The indicated base 12 corresponds to a fin-like structure formed on a base 12.

[0035] Then, at least one spacer wall 24 is formed on the sidewalls of the gate structures 14 and 16, respectively. Before or after the formation of the spacer wall 24, a lightly doped ion implantation can be selectively performed, and the dopants in the implanted substrate 12 can be activated by a rapid heating annealing process at approximately 930°C, so as to form a lightly doped drain 26 on both sides and below the spacer wall 24 in the substrate 12. In this embodiment, the spacer wall 24 can be a single spacer wall or a composite spacer wall. For example, it can include a bias spacer wall (not shown) and a main spacer wall (not shown). The bias spacer wall and the main spacer wall preferably contain different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, but are not limited thereto.

[0036] Next, a dry etching and / or wet etching process is performed, using the gate structures 14, 16 and the spacer wall 24 as an etching mask to etch the substrate 12 downwards along the spacer wall 24 in one or more steps to form a groove 28 in the substrate 12 on both sides of the gate structures 14, 16. For example, this etching process may include first performing a dry etching step to pre-form an initial trench (not shown) in the substrate 12 on both sides of the gate structures 14, 16, and then performing a wet etching process to isotropically enlarge the initial trench to form the groove 28. In one embodiment of the present invention, the wet etching process may use an etching liquid such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH). It is worth noting that the method of forming the groove 28 is not limited to the aforementioned dry etching combined with wet etching method, but can also be formed by one or more dry etching and / or wet etching steps. For example, in one embodiment, the groove 28 may have different cross-sectional shapes, such as circular arc, hexagon (also known as sigmaΣ) or octagon. This embodiment is described with a hexagonal cross-sectional shape as an example, but it is not limited thereto.

[0037] Subsequently, as Figure 2 As shown, a selective epitaxial growth (SEG) fabrication process is performed, using a gas such as dichlorosilane (DCS) to form an epitaxial layer 30 in each groove 28. The epitaxial layer 30 includes a first buffer layer 32 disposed on the surface of the groove 28, a second buffer layer 34 disposed on the surface of the first buffer layer 32, a bulk layer 36 disposed on the second buffer layer 34, a first cover layer 38 disposed on the bulk layer 36, and a second cover layer 40 disposed on the first cover layer 38.

[0038] In this embodiment, the top surface of the epitaxial layer 30 is preferably slightly higher than the top surface of the substrate 12, and preferably has the same cross-sectional shape as the groove 28, such as an arc, a hexagon (also known as sigmaΣ), or an octagon, but other cross-sectional shapes are also possible. In a preferred embodiment of the present invention, the epitaxial layer 30 may be made of different materials depending on the type of metal-oxide-semiconductor (MOS) transistor. For example, if the MOS transistor is a P-type transistor (PMOS), the epitaxial layer 30 may be selected to contain silicon germanide (SiGe), silicon germanide doped boron (SiGeB), or silicon germanium tin alloy (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type transistor (NMOS), the epitaxial layer 30 may be selected to contain silicon carbide (SiC), silicon carbide phosphide (SiCP), or silicon phosphide (SiP). Furthermore, selective epitaxial fabrication can be performed in a single-layer or multi-layer manner, and the heteroatoms (such as germanium atoms or carbon atoms) can be changed in a gradual manner. However, it is preferable to make the surface of the epitaxial layer 30 lighter or free of germanium atoms to facilitate the formation of the subsequent metal silicide layer.

[0039] A subsequent ion implantation process is performed to form a source / drain region 42 in part or all of the epitaxial layer 30. In another embodiment, the formation of the source / drain region 42 can also be performed in-situ during a selective epitaxial growth process. For example, when the metal-oxide semiconductor is PMOS, a silicon germanium epitaxial layer, a silicon germanium boron epitaxial layer, or a silicon germanium tin epitaxial layer is formed, which may be accompanied by the implantation of P-type dopants; or when the metal-oxide semiconductor is NMOS, a silicon carbide epitaxial layer, a silicon carbide phosphide epitaxial layer, or a silicon phosphide epitaxial layer is formed, which may be accompanied by the implantation of N-type dopants. This eliminates the need for subsequent additional ion implantation steps to form the source / drain regions of P-type / N-type transistors. Furthermore, in another embodiment, the dopants in the source / drain region 42 can also be formed in a gradient manner.

[0040] In detail, the first buffer layer 32 preferably comprises silicon germanide (SiGe), and the thickness of the first buffer layer 32 is approximately 60-80 angstroms or more preferably approximately 70 angstroms. The first buffer layer 32 preferably does not contain any dopants or is an undoped silicon-germanium layer. The germanium concentration distribution of the first buffer layer 32 is preferably between 0% and 25%, and the germanium concentration preferably increases from the substrate 12 toward the second buffer layer 34, or more specifically, the germanium concentration of the first buffer layer 32 near the lower substrate 12 is approximately 0%, while the germanium concentration of the second buffer layer 34 near the upper substrate 12 is approximately 25%.

[0041] The second buffer layer 34 preferably comprises silicon germanide (SiGe), and its thickness is approximately 150–170 angstroms or more preferably approximately 160 angstroms. The second buffer layer 34 preferably comprises boron or is a boron-doped silicon-germanium layer. The thickness of the second buffer layer 34 may be defined as the maximum depth into the substrate 12 extending downwards from near the surface of the substrate 12. Furthermore, the boron atoms in the second buffer layer 34 preferably have a concentration gradient, with the boron concentration preferably increasing from the bottom to the top of the second buffer layer 34, or more specifically, the boron concentration near the lower first buffer layer 32 is preferably less than the boron concentration near the upper main layer 36. Additionally, the germanium concentration distribution of the second buffer layer 34 is preferably between 25% and 31%, with the germanium concentration preferably increasing from the first buffer layer 32 towards the main layer 36, or more specifically, the germanium concentration in the second buffer layer 34 near the lower first buffer layer 32 is approximately 25%, while the germanium concentration near the upper main layer 36 is approximately 31%. It should also be noted that the sidewalls of the second buffer layer 34 formed by boron implantation in this stage preferably include linear or vertical sidewalls. In addition, compared with the bottom surface of the first buffer layer 32 which includes a flat surface, the bottom surface of the second buffer layer 34 preferably includes a curved surface. The sidewalls and bottom surface of the second buffer layer 34 preferably divide the first buffer layer 32 into three parts and prevent these three parts from contacting each other. Furthermore, the second buffer layer 34 contacts the substrate 12 in addition to contacting the first buffer layer 32.

[0042] The host layer 36 preferably comprises silicon germanide (SiGe), and the thickness of the host layer 36 is approximately 110–130 angstroms or more preferably approximately 120 angstroms. The host layer 36 also contains boron or is a boron-doped silicon-germanium layer. It should be noted that, compared to the boron atom concentration gradient in the second buffer layer 34, the boron atom concentration in the host layer 36 is preferably fixed or has no concentration gradient; that is, the boron concentration near the lower second buffer layer 34 is preferably equal to the boron concentration near the upper first masking layer 38, and the boron concentration in the host layer 36 is preferably equal to or greater than the maximum boron concentration in the second buffer layer 34. In this embodiment, the boron concentration of the host layer 36 is preferably approximately 3.0 × 10⁻⁶. 20 Atoms per cubic centimeter. Furthermore, the germanium concentration distribution of the main body layer 36 is preferably between 30% and 38.5%, with the germanium concentration preferably increasing from the second buffer layer 34 toward the first cover layer 38, or more specifically, the germanium concentration of the main body layer 36 near the lower second buffer layer 34 is approximately 30%, while the germanium concentration near the upper first cover layer 38 is approximately 38.5%. Structurally, the top surface of the main body layer 36 is preferably slightly higher than the top surfaces of the two side substrates 12. The main body layer 36 protruding from the top surface of the substrate 12 may include a curved surface, and the sidewalls of the main body layer 36 may converge with and contact the sidewalls of the lower second buffer layer 34 and the surface of the substrate 12.

[0043] The first masking layer 38 preferably comprises silicon germanide (SiGe), and the first masking layer 38 contains boron or is a boron-doped silicon-germanium layer. Similar to the main layer 36, which has a concentration gradient of boron atoms compared to the second buffer layer 34, the boron atoms in the first masking layer 38 are preferably fixedly distributed or have no concentration gradient; that is, the boron concentration near the lower main layer 36 is preferably equal to the boron concentration near the upper second masking layer 40, and the boron concentration in the first masking layer 38 is preferably less than the boron concentration in the lower main layer 36. In this embodiment, the boron concentration of the first masking layer 38 is preferably about 1.0 × 10⁻⁶. 20 Atoms per cubic centimeter. In addition, the germanium concentration distribution of the first masking layer 38 is preferably between 38.5% and 0%, and the germanium concentration preferably decreases from the main body layer 36 toward the second masking layer 40, or more specifically, the germanium concentration of the first masking layer 38 near the lower main body layer 36 is about 38.5% and the germanium concentration of the second masking layer 40 near the upper part is about 0%.

[0044] Unlike the first buffer layer 32, second buffer layer 34, main layer 36, and first cover layer 38, which are all composed of silicon germanide, the second cover layer 40 preferably comprises silicon (Si), and also contains boron or is a boron-doped silicon layer. Similar to the main layer 36, where the boron atoms in the second buffer layer 38 have a concentration gradient, the boron atoms in the second cover layer 40 are preferably fixedly distributed or have no concentration gradient. In this embodiment, the boron concentration of the second cover layer 40 is preferably about 1.8 × 10⁻⁶. 21 Atoms per cubic centimeter.

[0045] like Figure 3 As shown, a contact etch stop layer (CESL) 44 made of silicon nitride is then selectively formed on the substrate 12, covering the gate structures 14 and 16 and the second masking layer 40. An interlayer dielectric layer 46 is then formed on the contact etch stop layer 44. Next, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 46 and part of the contact etch stop layer 36, making the upper surface of the hard mask 22 flush with the upper surface of the interlayer dielectric layer 46.

[0046] Subsequently, a metal gate replacement fabrication process is performed to convert the gate structures 14 and 16 into metal gates. For example, a selective dry or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the hard mask 22, gate material layer 20, and even the gate dielectric layer 18 in the gate structures 14 and 16 to form a groove (not shown) in the interlayer dielectric layer 46. Then, a dielectric layer 48, a high dielectric constant dielectric layer 50, and a conductive layer including at least a work function metal layer 52 and a low impedance metal layer 54 are sequentially formed in the groove, and a planarization process is then performed to make the surfaces of the U-shaped high dielectric constant dielectric layer 50, the U-shaped work function metal layer 52, and the low impedance metal layer 54 flush with the surface of the interlayer dielectric layer 46.

[0047] In this embodiment, the high dielectric constant dielectric layer 50 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0048] The work function metal layer 52 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low impedance metal layer 54. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since the conversion of the dummy gate to a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the high dielectric constant dielectric layer 50, a portion of the work function metal layer 52, and a portion of the low impedance metal layer 54 may be removed to form a groove (not shown). Then, a hard mask 56 is filled into the groove and made flush with the surface of the interlayer dielectric layer 46. The hard mask 56 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0049] like Figure 4 As shown, a pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 46 and a portion of the contact hole etching stop layer 44 adjacent to the gate structures 14 and 16 to form multiple contact holes (not shown) and expose the underlying second masking layer 40. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs 58 in each contact hole to electrically connect the source / drain regions 42. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0050] Generally, in existing epitaxial layer structures, the buffer layer is either undoped or an undoped silicon-germanium layer, while the host layer above it is a boron-doped silicon-germanium layer. However, the boron dopant in the host layer is usually evenly distributed within the host layer, making it prone to film cracking when the boron dopant diffuses into the silicon substrate. To improve this problem, the present invention preferably provides an additional buffer layer between the buffer layer and the host layer, such as a second buffer layer 34 as described in the previous embodiment. This buffer layer contains a boron concentration gradient, wherein the concentration of boron atoms preferably increases from the bottom to the top of the second buffer layer 34, or more specifically, the boron concentration near the lower first buffer layer 32 is preferably less than the boron concentration near the upper host layer 36. The second buffer layer 34 preferably has vertical and flat sidewalls and a curved bottom surface. With this configuration, the epitaxial layer structure of the present invention can provide better stress distribution, thereby avoiding film cracking.

[0051] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Include: The gate structure is disposed on the substrate; An epitaxial layer is disposed adjacent to the gate structure, the epitaxial layer comprising: A first buffer layer, wherein the first buffer layer is an undoped layer; A second buffer layer, disposed on the first buffer layer, includes a boron concentration gradient, wherein the concentration of boron atoms increases from the bottom to the top of the second buffer layer. The second buffer layer includes straight sidewalls, wherein the sidewalls and the bottom surface of the second buffer layer divide the first buffer layer into a first portion, a second portion, and a third portion that do not contact each other. The first and second portions of the first buffer layer directly contact the straight sidewalls of the second buffer layer, and the third portion directly contacts the bottom surface of the second buffer layer, the bottom surface of the second buffer layer comprising a curved surface. The main body layer is disposed on the second buffer layer; and A first masking layer is disposed on the main body layer, wherein the boron atoms in the first masking layer are fixedly distributed, and the boron concentration in the first masking layer is less than the boron concentration in the main body layer.

2. The semiconductor device of claim 1, further comprising: The second covering layer is disposed on the first covering layer.

3. The semiconductor device of claim 2, wherein the host layer comprises a germanium concentration gradient.

4. The semiconductor device of claim 2, wherein the first masking layer comprises a germanium concentration gradient.

5. The semiconductor device of claim 2, wherein the second masking layer comprises silicon.

6. The semiconductor device of claim 1, wherein the second buffer layer contacts the substrate.

7. The semiconductor device of claim 1, wherein the bottom surface of the first buffer layer comprises a flat surface.

8. A semiconductor element, characterized in that, Include: The gate structure is disposed on the substrate; An epitaxial layer is disposed adjacent to the gate structure, the epitaxial layer comprising: A first buffer layer, wherein the first buffer layer is an undoped layer; A second buffer layer, disposed on the first buffer layer, includes a boron concentration gradient, wherein the concentration of boron atoms increases from the bottom to the top of the second buffer layer. The second buffer layer includes straight sidewalls, wherein these sidewalls and the bottom surface of the second buffer layer divide the first buffer layer into a first portion, a second portion, and a third portion that do not contact each other. The third portion of the first buffer layer directly contacts the bottom surface of the second buffer layer, and the bottom surface of the second buffer layer includes a curved surface. The main body layer is disposed on the second buffer layer; and A first masking layer is disposed on the main body layer, wherein the boron atoms in the first masking layer are fixedly distributed, and the boron concentration in the first masking layer is less than the boron concentration in the main body layer.

9. The semiconductor element of claim 8, further comprising: The second covering layer is disposed on the first covering layer.

10. The semiconductor device of claim 9, wherein the host layer comprises a concentration gradient of germanium.

11. The semiconductor device of claim 9, wherein the first masking layer comprises a concentration gradient of germanium.

12. The semiconductor device of claim 9, wherein the second masking layer comprises silicon.

13. The semiconductor device of claim 8, wherein the second buffer layer comprises a germanium concentration gradient.

14. The semiconductor device of claim 8, wherein the bottom surface of the first buffer layer comprises a flat surface.

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