A multi-layer field plate LDMOS device structure and a manufacturing method thereof
By using a multi-layer field plate structure and a combination of tungsten silicon and tungsten materials, the problems of high RF loss and weak hot carrier injection effect in existing LDMOS devices are solved, achieving low loss and strong suppression.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU WATECH ELECTRONICS CO LTD
- Filing Date
- 2022-02-23
- Publication Date
- 2026-08-04
AI Technical Summary
In existing LDMOS devices, the high grounding resistance of the tungsten silicon field plate leads to high radio frequency loss, while the large oxide layer thickness of the tungsten field plate is not conducive to suppressing the hot carrier injection effect, making it difficult to achieve both low radio frequency loss and strong hot carrier injection suppression capability.
A multi-layer field plate structure is adopted, in which the first layer closest to the drift region is a tungsten-silicon field plate, and the second and above layers are tungsten field plates. By thinning the silicon dioxide layer below the first field plate and using low resistivity tungsten material, the top field plate completely covers the gate and extends to enhance the isolation effect.
It achieves a balance between low RF loss and strong suppression of hot carrier injection effect, reduces the resistivity of the field plate and reduces parasitic coupling.
Smart Images
Figure CN116504829B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a multilayer field plate LDMOS device structure and its fabrication method, belonging to the field of semiconductor devices. Background Technology
[0002] In LDMOS devices, the field plate serves to enhance surface depletion, increase breakdown voltage, suppress hot carrier injection effects, and isolate the direct coupling between the drain and gate.
[0003] In existing LDMOS devices, multilayer field plates are typically used. Each field plate is individually connected to the metal layer through a field plate bridge and via a via. In one approach, tungsten silicon is used as the field plate material. However, the grounding resistance of the tungsten silicon field plate is relatively large, resulting in high RF loss and affecting device efficiency. Another approach is to use tungsten as the field plate material. However, since the etching selectivity of tungsten and silicon dioxide is relatively poor, the oxide layer thickness under the field plate needs to be sufficiently thick. Generally, the thinner the oxide layer between the first field plate and silicon, the better the effect of suppressing the hot carrier injection effect. Therefore, a thicker oxide layer results in a poorer ability of the field plate to suppress the hot carrier injection effect.
[0004] It is particularly important to provide an LDMOS device junction that can balance low RF loss and strong suppression of hot carrier injection. Summary of the Invention
[0005] The main objective of this invention is to provide a multilayer field plate LDMOS device structure and its fabrication method to overcome the shortcomings of the prior art.
[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:
[0007] One aspect of the present invention provides a multilayer field plate LDMOS device structure, which includes an epitaxial layer, an insulating layer formed on the epitaxial layer, and a gate disposed in the insulating layer. A drift region and a body region are formed in the epitaxial layer, a drain region is formed in the drift region, and an active region and a body contact region are formed in the body region.
[0008] Furthermore, the LDMOS device structure also includes two or more field plates, which are arranged sequentially within the insulating layer in a direction that gradually moves away from the epitaxial layer. The first field plate is close to the drift region and is a tungsten-silicon field plate, while the second to the last field plate (i.e., the topmost field plate) are tungsten field plates.
[0009] Furthermore, at least a partial region of the gate is covered by the orthographic projection of the first field plate.
[0010] In a preferred embodiment, the length of the region of the gate covered by the orthographic projection of the first field plate is 5 to 50% of the gate length, where the length refers to the dimension of the region of the gate covered by the orthographic projection of the first field plate in the direction from the source region to the drain region.
[0011] Furthermore, the orthographic projection of the last field plate has a first portion that completely covers the gate and a second portion that extends outward from the edge of the gate, the second portion covering a local area of the source region.
[0012] In a preferred embodiment, the length of the second portion of the orthographic projection of the last field plate extending outward from the gate edge is 0.05 to 0.4 μm, where the length refers to the dimension of the second portion of the orthographic projection of the last field plate extending outward from the gate edge in the direction from the source region to the drain region.
[0013] In one embodiment, two or more of the field plates are spaced apart from each other in a direction that gradually moves away from the epitaxial layer.
[0014] In one embodiment, the insulating layer may be a silicon dioxide layer.
[0015] In one embodiment, a local area of at least one field plate is in electrical contact with a local area of an adjacent field plate.
[0016] In one embodiment, at least one field plate is electrically connected to a metal layer through corresponding conductive vias, the vias being disposed in the insulating layer, and the metal layer being disposed on the insulating layer.
[0017] In one embodiment, at least one field plate is electrically connected to the metal layer via corresponding connecting bridges and conductive vias, wherein the connecting bridges and vias are disposed in the insulating layer, and the metal layer is disposed on the insulating layer.
[0018] Furthermore, a gate oxide layer is formed between the gate and the epitaxial layer.
[0019] In a preferred embodiment, the gate oxide layer is made of silicon dioxide.
[0020] Furthermore, the epitaxial layer is formed on the substrate.
[0021] Another aspect of the present invention provides a method for fabricating the above-described multi-field plate LDMOS device structure, comprising:
[0022] The step of fabricating the gate on the epitaxial layer,
[0023] The steps of forming drift regions, volume regions, drain regions, source regions and volume region contact regions in the epitaxial layer;
[0024] Furthermore, the manufacturing method further includes:
[0025] The step of fabricating two or more field plates on the epitaxial layer involves the two or more field plates being disposed within the insulating layer and arranged sequentially in a direction gradually moving away from the epitaxial layer, wherein the first field plate is close to the drift region and is a tungsten-silicon field plate, and the second to the last field plates are tungsten field plates.
[0026] In one embodiment, the manufacturing method specifically includes:
[0027] S1. A first insulating layer is formed on the epitaxial layer, and then a first field plate and a first connecting bridge connected to the first field plate are formed on the first insulating layer.
[0028] S2. A second insulating layer is formed on the first insulating layer, and then a second field plate and a second connecting bridge connected to the second field plate are formed on the second insulating layer.
[0029] S3. Repeat step S2 until the last field plate and the last connecting bridge connected to the last field plate are formed.
[0030] S4. Form conductive vias that are connected to each connecting bridge, and make the conductive vias connected to the metal layer.
[0031] In another embodiment, the manufacturing method specifically includes:
[0032] S1. A first insulating layer is formed on the epitaxial layer, and then a first field plate is formed on the first insulating layer;
[0033] S2. A second insulating layer is formed on the first insulating layer, and the second insulating layer is etched to form a first groove structure in the second insulating layer, and a local area of the first field plate is exposed from the first groove structure. Then, a second field plate is formed on the second oxide layer, and a local area of the second field plate is electrically contacted with a local area of the first field plate through the first groove structure.
[0034] S3. Repeat step S2 until the last layer of the field plate is formed;
[0035] S4. Form a connecting bridge connected to the last layer of the field plate and a through hole connected to the connecting bridge, and connect the through hole to the metal layer.
[0036] Furthermore, the fabrication method further includes: forming a gate oxide layer on the epitaxial layer, and then forming a gate on the gate oxide layer, wherein the gate oxide layer is made of silicon dioxide.
[0037] Furthermore, the fabrication method further includes forming the epitaxial layer on a substrate.
[0038] Compared with the prior art, the advantages of the present invention include:
[0039] (1) The LDMOS device provided by the present invention includes a multilayer field plate structure, wherein the first field plate closest to the drift region is made of tungsten silicon. Tungsten silicon and silicon dioxide have a high etching selectivity, which can minimize the thickness of the silicon dioxide layer below the first field plate and enhance the suppression effect of the field plate on the hot carrier injection effect. At the same time, the second and above field plates are made of tungsten. The resistivity of tungsten is much lower than that of tungsten silicon, which can reduce the RF loss of the field plate.
[0040] (2) The LDMOS device provided by the present invention has a top-level field plate that completely covers the gate and has a certain distance of extension, which enhances the isolation effect of the field plate and reduces parasitic gate-drain coupling. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a cross-sectional schematic diagram of a multilayer field plate LDMOS device structure provided in Embodiment 1 of the present invention;
[0043] Figure 2 yes Figure 1 A top view of the LDMOS device structure in the diagram;
[0044] Figure 3 This is a cross-sectional schematic diagram of a multilayer field plate LDMOS device structure provided in Embodiment 2 of the present invention;
[0045] Figure 4 yes Figure 3 A top view of the LDMOS device structure in the diagram;
[0046] Figures 5a to 5b This is a schematic diagram of the LDMOS device structure of the multilayer field plate in Embodiment 2 of the present invention during fabrication. Detailed Implementation
[0047] In view of the deficiencies of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. Addressing the problems of high resistance leading to high RF loss in multilayer tungsten-silicon field plates and the large oxide layer thickness in multilayer tungsten field plates hindering the suppression of hot carrier injection, and considering that a thinner oxide layer between the first field plate and the silicon epitaxial layer results in better suppression of hot carrier injection, the multilayer field plate LDMOS device provided by this invention comprises a multilayer field plate structure. The first field plate, closest to the drift region, is made of tungsten-silicon. The high etching selectivity of tungsten-silicon compared to silicon dioxide allows for maximum reduction in the thickness of the silicon dioxide layer beneath the first field plate, enhancing the field plate's suppression of hot carrier injection. Simultaneously, the second and subsequent field plates are made of tungsten, whose resistivity is significantly lower than that of tungsten-silicon, reducing the RF loss of the field plate.
[0048] In addition, the topmost field plate completely covers the gate and extends a certain distance, which can enhance the isolation effect of the field plate between the drain and the gate and reduce the parasitic coupling between the gate and the drain.
[0049] The technical solution, its implementation process, and its principle will be further explained below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0050] Example 1:
[0051] Please see Figure 1-2 As shown in the figure, this embodiment provides a multilayer field plate LDMOS device structure, which includes a silicon substrate 18 and a silicon epitaxial layer 17 formed on the silicon substrate 18. A gate oxide layer 11 and a polysilicon gate 10 are formed on the silicon epitaxial layer 17. A drift region 16 and a body region 15 are formed in the silicon epitaxial layer 17. A drain region 13 is formed in the drift region 16, and an active region 12 and a body contact region 14 are formed in the body region 15. The gate oxide layer 11 is made of silicon dioxide.
[0052] Specifically, an insulating layer 111 is formed on the silicon epitaxial layer 17. The gate oxide layer 11 and the polysilicon gate 10 are both disposed in the insulating layer 111, and two field plates are formed within the insulating layer 111. These two field plates are arranged sequentially in a direction gradually moving away from the epitaxial layer 17. The first field plate 19 is close to the drift region 16 and is a tungsten-silicon field plate, while the second field plate 110 (which is the top field plate in this embodiment) is a tungsten field plate. The insulating layer is a silicon dioxide layer.
[0053] Specifically, a local area of the polysilicon gate 10 is covered by the orthographic projection of the first field plate 19, and the length of the area of the polysilicon gate 10 covered by the orthographic projection of the first field plate 19 is 5% of the gate length. Here, the length refers to the size of the area of the polysilicon gate 10 covered by the orthographic projection of the first field plate 19 in the direction from the source region 12 to the drain region 13.
[0054] Specifically, the orthographic projection of the second field plate 110 has a first portion that completely covers the polysilicon gate 10 and a second portion that extends outward from the edge of the polysilicon gate 10, the second portion covering a local area of the source region 12. The length of the second portion extending outward from the edge of the polysilicon gate 10 is 0.05 μm, where length refers to the dimension of the second portion extending outward from the edge of the polysilicon gate 10 in the direction from the source region 12 to the drain region 13.
[0055] Specifically, the first field plate 19 and the second field plate 110 are spaced apart from each other in a direction gradually moving away from the epitaxial layer 17, and the first field plate 19 is connected to the first connecting bridge 112 and the first conductive via 113 connected to the first connecting bridge 112, and the metal layer (not in the middle) formed on the insulating layer 111. Figure 3 and Figure 4 (As shown in the figure) The second layer field plate 110 is connected to the metal layer in sequence via the second connecting bridge 114 and the second conductive through hole 115 connected to the second connecting bridge 114. The first connecting bridge 112, the second connecting bridge 114, the first through hole 113, and the second through hole 115 are all disposed in the insulating layer 111.
[0056] Furthermore, the method for fabricating a multilayer field plate LDMOS device structure provided in this embodiment specifically includes the following steps:
[0057] Step 1) Provide a silicon substrate 18 and epitaxially grow a silicon epitaxial layer 17 on the silicon substrate 18.
[0058] Step 2) A gate oxide layer 11 and a polysilicon gate 10 are sequentially formed on the silicon epitaxial layer 17.
[0059] Step 3) A drift region 16 and a body region 15 are formed in the silicon epitaxial layer 17 by ion implantation. A drain region 13 is formed in the drift region 16, and a source region 12 and a body contact region 14 are formed in the body region 15.
[0060] Step 4) A first silicon dioxide layer is formed on the surface of the silicon epitaxial layer 17, and then a first field plate 19 is formed on the silicon dioxide layer using tungsten silicon material, and a first connecting bridge 112 is formed to connect with the first field plate 19.
[0061] Step 5) A second silicon dioxide layer is formed on the first silicon dioxide layer, and then a second field plate 110 is formed on the second silicon dioxide layer using tungsten material, and a second connecting bridge 114 is formed to connect with the second field plate 110.
[0062] Step 6) Form a first conductive via 113 and a second conductive via 115 that are connected to the first connecting bridge 112 and the second connecting bridge 114, respectively, and ensure that both the first conductive via 113 and the second conductive via 115 are connected to the metal layer. Specifically, the first conductive via 113 penetrates the first silicon dioxide layer and the second silicon dioxide layer in a vertical direction, and the second conductive via 115 penetrates the second silicon dioxide layer in a vertical direction.
[0063] Example 2:
[0064] Please see Figure 3-4 The LDMOS device structure with a multilayer field plate provided in this embodiment is basically similar to the device structure in Embodiment 1. It includes a silicon substrate 28 and a silicon epitaxial layer 27 formed on the silicon substrate 28. A gate oxide layer 21 and a polysilicon gate 20 are formed on the silicon epitaxial layer 27. A drift region 26 and a body region 25 are formed in the silicon epitaxial layer 27. A drain region 23 is formed in the drift region 26, and an active region 22 and a body contact region 24 are formed in the body region 25. The gate oxide layer 21 is made of silicon dioxide.
[0065] Specifically, an insulating layer 211 is formed on the silicon epitaxial layer 27. The gate oxide layer 21 and the polysilicon gate 20 are both disposed in the insulating layer 211, and two field plates are formed within the insulating layer 211. These two field plates are arranged sequentially in a direction gradually moving away from the epitaxial layer 27. The first field plate 29 is close to the drift region 26 and is a tungsten-silicon field plate, while the second field plate 210 (which is the top field plate in this embodiment) is a tungsten field plate. The insulating layer is a silicon dioxide layer.
[0066] Specifically, a local area of the polysilicon gate 20 is covered by the orthographic projection of the first field plate 29, and the length of the area of the polysilicon gate 20 covered by the orthographic projection of the first field plate 29 is 50% of the gate length. Here, the length refers to the size of the area of the polysilicon gate 20 covered by the orthographic projection of the first field plate 29 in the direction from the source region 22 to the drain region 23.
[0067] Specifically, the orthographic projection of the second field plate 210 has a first portion that completely covers the polysilicon gate 20 and a second portion that extends outward from the edge of the polysilicon gate 20, the second portion covering a local area of the source region 22. The length of the second portion extending outward from the edge of the polysilicon gate 20 is 0.4 μm, where length refers to the dimension of the second portion extending outward from the edge of the polysilicon gate 20 in the direction from the source region 22 to the drain region 23.
[0068] Specifically, a local area of the first field plate 29 is electrically in contact with a local area of the second field plate 210, and the second field plate 210 is connected to the metal layer (not in the insulating layer 211) formed on the insulating layer 211 via the first connecting bridge 212, the second connecting bridge 214, and the first conductive via 213 and the second conductive via 215 respectively connected to the first connecting bridge 212 and the second connecting bridge 214. Figure 3 and Figure 4 (As shown in the figure) connection, wherein the first connecting bridge 212, the second connecting bridge 214, the first conductive through hole 213, and the second conductive through hole 215 are all disposed in the insulating layer 211.
[0069] In some embodiments, the second field plate 210 may also be connected to the metal layer via only a connecting bridge and a through hole connected to the connecting bridge.
[0070] Furthermore, the method for fabricating a multilayer field plate LDMOS device structure provided in this embodiment specifically includes the following steps:
[0071] Step 1) Provide a silicon substrate 28 and epitaxially grow a silicon epitaxial layer 27 on the silicon substrate 28.
[0072] Step 2) A gate oxide layer 21 and a polysilicon gate 20 are sequentially formed on the silicon epitaxial layer 27.
[0073] Step 3) Drift region 26 and body region 25 are formed in silicon epitaxial layer 27 by ion implantation, drain region 23 is formed in drift region 26, and source region 22 and body contact region 24 are formed in body region 25.
[0074] Step 4) A first silicon dioxide layer is formed on the surface of the silicon epitaxial layer 27, and then a first field plate 29 is formed on the silicon dioxide layer using tungsten silicon material, as shown below. Figure 5a As shown.
[0075] Step 5) Form a second silicon dioxide layer on the first silicon dioxide layer, and then etch a first groove structure 216 in the second silicon dioxide layer, thereby exposing a local area of the first field plate 29 from the first groove structure 216, such as... Figure 5b As shown.
[0076] Step 6) A second field plate 210 is formed on the second silicon dioxide layer using tungsten material, so that a local area of the second field plate 210 is electrically contacted with a local area of the first field plate 29 through the first groove structure 216, and then a first connecting bridge 212 and a second connecting bridge 214 are formed to connect with the second field plate 210.
[0077] Step 7) Form a first conductive via 113 and a second conductive via 215 that are connected to the first connecting bridge 212 and the second connecting bridge 214, respectively, and ensure that both the first conductive via 213 and the second conductive via 215 are connected to the metal layer. Both the first conductive via 213 and the second conductive via 215 penetrate the second silicon dioxide layer in a vertical direction.
[0078] In addition, the inventors of this case also conducted experiments with other raw materials, process operations, and process conditions described in this specification, referring to the aforementioned embodiments, and obtained relatively ideal results in all cases.
[0079] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.
Claims
1. A multilayer field plate LDMOS device structure, comprising an epitaxial layer, an insulating layer formed on the epitaxial layer, and a gate disposed within the insulating layer, wherein a drift region and a body region are formed in the epitaxial layer, a drain region is formed in the drift region, and an active region and a body contact region are formed in the body region; Its features are: The LDMOS device structure further includes two or more field plates, which are arranged sequentially within the insulating layer in a direction gradually moving away from the epitaxial layer. The first field plate is close to the drift region and is a tungsten-silicon field plate, while the second to the last field plates are tungsten field plates. At least a partial area of the gate is covered by the orthographic projection of the first field plate, and the orthographic projection of the last field plate has a first portion that completely covers the gate and a second portion that extends outward from the edge of the gate. The second portion covers a partial area of the source region.
2. The LDMOS device structure according to claim 1, characterized in that: The length of the area of the gate covered by the orthographic projection of the first field plate is 5 to 50% of the gate length.
3. The LDMOS device structure according to claim 1, characterized in that: The length of the second portion of the orthographic projection of the last field plate extending outward from the gate edge is 0.05~0.4µm.
4. The LDMOS device structure according to any one of claims 1-3, characterized in that: The two or more field plates are spaced apart from each other in a direction that gradually moves away from the epitaxial layer.
5. The LDMOS device structure according to any one of claims 1-3, characterized in that: At least one field plate has a local area in electrical contact with a local area of an adjacent field plate.
6. The LDMOS device structure according to any one of claims 1-3, characterized in that: At least one field plate is electrically connected to the metal layer through corresponding conductive vias, the vias being disposed in the insulating layer, and the metal layer being disposed on the insulating layer.
7. The LDMOS device structure according to any one of claims 1-3, characterized in that: At least one field plate is electrically connected to the metal layer through corresponding connecting bridges and conductive vias. The connecting bridges and vias are all disposed in the insulating layer, and the metal layer is disposed on the insulating layer.
8. The LDMOS device structure according to claim 1, characterized in that: A gate oxide layer is also disposed between the gate and the epitaxial layer.
9. The LDMOS device structure according to claim 1, characterized in that: The epitaxial layer is formed on the substrate.
10. A method for fabricating an LDMOS device structure with a multilayer field plate according to any one of claims 1-9, comprising: The step of fabricating the gate on the epitaxial layer, The steps of forming drift region, volume region, drain region, source region and volume region contact region in the epitaxial layer; The manufacturing method is characterized by further comprising: In the step of fabricating two or more field plates on the epitaxial layer, the two or more field plates are sequentially arranged in the insulating layer in a direction gradually moving away from the epitaxial layer. The first field plate is close to the drift region and is a tungsten-silicon field plate. The second to the last field plates are tungsten field plates. At least a partial area of the gate is covered by the orthographic projection of the first field plate. The orthographic projection of the last field plate has a first portion that completely covers the gate and a second portion that extends outward from the edge of the gate. The second portion covers a partial area of the source region.
11. The manufacturing method according to claim 10, characterized in that, Specifically, it includes: S1. A first insulating layer is formed on the epitaxial layer, and then a first field plate and a first connecting bridge connected to the first field plate are formed on the first insulating layer. S2. A second insulating layer is formed on the first insulating layer, and then a second field plate and a second connecting bridge connected to the second field plate are formed on the second insulating layer. S3. Repeat step S2 until the last field plate and the last connecting bridge connected to the last field plate are formed. S4. Form conductive vias that are connected to each connecting bridge, and make the conductive vias connected to the metal layer located on the first insulating layer or the second insulating layer.
12. The manufacturing method according to claim 10, characterized in that, Specifically, it includes: S1. A first insulating layer is formed on the epitaxial layer, and then a first field plate is formed on the first insulating layer; S2. A second insulating layer is formed on the first insulating layer, and the second insulating layer is etched to form a first groove structure in the second insulating layer, and a local area of the first field plate is exposed from the first groove structure. Then, a second field plate is formed on the second insulating layer, and a local area of the second field plate is electrically contacted with a local area of the first field plate through the first groove structure. S3. Repeat step S2 until the last layer of the field plate is formed; S4. Form a connecting bridge connected to the last field plate and a conductive via connected to the connecting bridge, and connect the conductive via to a metal layer located on the first insulating layer or the second insulating layer.
13. The manufacturing method according to claim 10, characterized in that, Also includes: A gate oxide layer is formed on the epitaxial layer, and then a gate is formed on the gate oxide layer.
14. The manufacturing method according to claim 10, characterized in that, The fabrication method further includes forming the epitaxial layer on a substrate.