Epitaxial structure of ldmos, manufacturing method and device thereof

Abstract

This invention discloses an epitaxial structure of an LDMOS, its fabrication method, and a device thereof. The epitaxial structure includes: a first epitaxial layer disposed on a first surface of a semi-insulating substrate; a second epitaxial layer disposed on the first epitaxial layer, including a body region and a drift region, wherein a source region and a body contact region are disposed within the body region, and a drain region is disposed within the drift region; an insulating layer disposed on the second epitaxial layer, wherein a gate is disposed; a source region metal electrically connected to both the source region and the body contact region, and a drain region metal electrically connected to the drain region; a second metal layer disposed on a second surface of the substrate, wherein the source region metal is electrically connected to the second metal layer through a third conductive via that continuously penetrates the second epitaxial layer, the first epitaxial layer, and the substrate along the thickness direction. The epitaxial structure provided by this invention significantly increases the breakdown voltage of the device, reduces the capacitance of the device, and improves the performance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, especially the field of power semiconductor devices, and particularly relates to an epitaxial structure of LDMOS, its fabrication method and device. Background Technology

[0002] Current LDMOS devices are mainly silicon LDMOS devices. Due to the characteristics of the material, LDMOS devices cannot break through the material limits of silicon.

[0003] Si-based LDMOS devices are currently the mainstream LDMOS devices. The bandgap of Si material is 1.1 eV, which is less than that of SiC material (3.2 eV). Therefore, the specific on-resistance and breakdown voltage of SiC-based LDMOS devices are much higher than those of Si-based LDMOS devices. Considering the same breakdown voltage design, the drift region length of SiC devices is significantly reduced, resulting in superior output capacitance density, output power density, and other performance characteristics compared to Si-based LDMOS devices. Simultaneously, the overall device size is also significantly reduced, leading to higher chip integration and lower cost per chip. The thermal conductivity of SiC material is (4 W / cm·K). -1 The thermal conductivity is higher than that of Si (1.3 W / cm·K). -1 Furthermore, SiC-based LDMOS utilizes a homoepitaxial process, avoiding heterogeneous interface thermal resistance. Therefore, SiC-based LDMOS devices exhibit excellent chip heat dissipation capabilities, offering significant advantages in high-power, high-current chip applications. Simultaneously, the high lattice quality achieved through homoepitaxial growth greatly improves the yield and reliability of SiC-based LDMOS device applications.

[0004] With the maturity of SiC technology, people have gradually begun to study SiC LDMOS devices. Most SiC devices use n-type substrates, and using this type of substrate to prepare SiC LDMOS devices will face serious leakage risks. Summary of the Invention

[0005] Current research on SiC-LDMOS fabrication on semi-insulating substrates is limited. To address the shortcomings of existing technologies, this invention proposes a device topology for growing p-type epitaxy on a semi-insulating substrate, which can effectively and conveniently fabricate high-performance SiC LDMOS with low leakage current and low loss. The purpose of this invention is to provide an epitaxial structure for LDMOS, its fabrication method, and a device thereof.

[0006] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0007] In a first aspect, the present invention provides an epitaxial structure for LDMOS, comprising:

[0008] A first epitaxial layer is disposed on a first surface of a semi-insulating substrate, and the first epitaxial layer is of a first conductivity type.

[0009] A second epitaxial layer is disposed on the first epitaxial layer. The second epitaxial layer includes a body region and a drift region. A source region and a body contact region are disposed in the body region. The source region is in contact with the body contact region. A drift buffer region and a drain region are disposed in the drift region. The drift buffer region is disposed between the drain region and the drift region.

[0010] An insulating layer is further disposed on the second epitaxial layer, a gate is disposed within the insulating layer, and a first metal layer is further disposed on the insulating layer. The first metal layer includes a source region metal and a drain region metal that are electrically isolated from each other. The source region metal is electrically connected to both the source region and the body contact region through a first conductive via penetrating the insulating layer, and the drain region metal is electrically connected to the drain region through a second conductive via penetrating the insulating layer.

[0011] A second metal layer is further disposed on the second surface of the substrate opposite to the first surface. The source region metal is electrically connected to the second metal layer through a third conductive via that continuously penetrates the second epitaxial layer, the first epitaxial layer, and the substrate along the thickness direction.

[0012] Secondly, the present invention also provides a method for manufacturing the above-mentioned epitaxial structure, comprising:

[0013] The step of fabricating the first epitaxial layer on the first surface of the semi-insulating substrate.

[0014] The step of fabricating a second epitaxial layer on the first epitaxial layer.

[0015] The step of fabricating the gate on the epitaxial layer,

[0016] The steps of forming a volume region, a drift region, a source region, a volume contact region, a drift buffer zone, and a drain region in the second epitaxial layer.

[0017] The step of forming an insulating layer on the second epitaxial layer,

[0018] The steps of fabricating a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via in the insulating layer.

[0019] The step of forming the first metal layer on the insulating layer,

[0020] The step of forming a second metal layer on the second surface of the substrate.

[0021] Thirdly, the present invention also provides an LDMOS device comprising the above-described epitaxial structure.

[0022] Based on the above technical solution, compared with the prior art, the beneficial effects of the present invention include at least the following:

[0023] The LDMOS epitaxial structure provided by this invention is based on a semi-insulating high-resistivity substrate and uses p-type epitaxy. The p-type epitaxy serves as a buffer region for high voltage in the device, which increases the breakdown voltage of the device on the one hand, and the semi-insulating substrate can reduce the capacitance of the device on the other hand, thereby improving the performance of the device. Furthermore, by electrically connecting the source metal and the back metal of the substrate through conductive vias, the ground loss of the device can be effectively reduced, thus realizing a high-performance n-type LDMOS device on a semi-insulating substrate.

[0024] The above description is merely an overview of the technical solution of the present invention. In order to enable those skilled in the art to better understand the technical means of this application and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described below in conjunction with detailed drawings. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of an epitaxial structure of LDMOS provided in a typical embodiment of the present invention;

[0026] Figure 2 This is a partial flowchart illustrating a method for fabricating an epitaxial structure of LDMOS, provided in a typical embodiment of the present invention.

[0027] Figure 3 This is a partial flowchart illustrating a method for fabricating an epitaxial structure of LDMOS, provided in a typical embodiment of the present invention.

[0028] Figure 4 This is a partial flowchart illustrating a method for fabricating an epitaxial structure of LDMOS, provided in a typical embodiment of the present invention.

[0029] Figure 5 This is a partial flowchart illustrating a method for fabricating an epitaxial structure of LDMOS, provided in a typical embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the epitaxial structure of an LDMOS provided in another typical embodiment of the present invention;

[0031] Explanation of reference numerals in the attached figures: 1. Semi-insulating substrate; 2. First epitaxial layer; 3. Drift region; 4. Body region; 5. Source region; 6. Body contact region; 7. Drain region; 8. Drift buffer zone; 9. Gate; 10. Drift field plate; 11. First conductive via; 12. Second conductive via; 13. Third conductive via; 14. Fourth conductive via; 15. Buried layer; 16. Source region metal; 17. Drain region metal; 18. Second metal layer; 19. Gate dielectric layer. Detailed Implementation

[0032] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0034] Moreover, relational terms such as “first” and “second” are used merely to distinguish one component or method step from another that has the same name, and do not necessarily require or imply any such actual relationship or order between these components or method steps.

[0035] The full names and Chinese definitions of some of the English abbreviations mentioned in this invention are as follows:

[0036] LDMOS: lateral double diffusion metal oxide semiconductor;

[0037] TSV: Through silicon VIA (In this invention, it can also refer to a through-hole that penetrates other materials, such as SiO2, SiC, SiN, and other materials used in SiC LDMOS).

[0038] BV: Breakdown Voltage (i.e., the maximum voltage that the drain can withstand when the gate and source of the device are grounded. When the drain voltage exceeds this, the source and drain of the device are broken down to form a conductive channel, and the device will no longer be controlled by the gate).

[0039] See Figures 1-5 An embodiment of the present invention provides an epitaxial structure of LDMOS comprising:

[0040] The first epitaxial layer 2 is disposed on the first surface of the semi-insulating substrate 1, and the first epitaxial layer 2 is of the first conductivity type.

[0041] The second epitaxial layer is disposed on the first epitaxial layer 2. The second epitaxial layer includes a body region 4 and a drift region 3. The body region 4 is provided with a source region 5 and a body contact region 6. The source region 5 is in contact with the body contact region 6. The drift region 3 is provided with a drift buffer 8 and a drain region 7. The drift buffer 8 is disposed between the drain region 7 and the drift region 3.

[0042] An insulating layer is also disposed on the second epitaxial layer, a gate 9 is disposed within the insulating layer, and a first metal layer is also disposed on the insulating layer.

[0043] The first metal layer includes a source region metal 16 and a drain region metal 17 that are electrically isolated from each other. The source region metal 16 is electrically connected to both the source region 5 and the body contact region 6 through a first conductive via 11 penetrating the insulating layer. The drain region metal 17 is electrically connected to the drain region 7 through a second conductive via 12 penetrating the insulating layer.

[0044] A second metal layer 18 is further disposed on the second surface of the substrate 1 opposite to the first surface, and the source metal 16 is electrically connected to the second metal layer 18 through a third conductive via 13 that continuously penetrates the second epitaxial layer, the first epitaxial layer 2 and the substrate 1 along the thickness direction.

[0045] In this embodiment, the first conductivity type can be p-type.

[0046] In this embodiment, the semi-insulating substrate 1 may include a SiC substrate 1.

[0047] See also Figure 1 In this embodiment, the epitaxial structure further includes a buried layer 15 of a first conductivity type, the buried layer 15 being disposed on a first surface of the substrate 1 and buried by the first epitaxial layer 2, and the third conductive via 13 passing through the buried layer 15.

[0048] In this embodiment of the LDMOS device, a typical semi-insulating substrate 1 is selected. A p-type first epitaxial layer 2 is grown on the semi-insulating substrate 1. Depending on the voltage limit (BV) and capacitance reduction requirements, a p-type buried layer 15 can be formed below the first epitaxial layer 2 using ion implantation or secondary epitaxy. The thickness and doping concentration of the p-type epitaxial layer are designed according to the voltage application requirements of the device. For example, for a device with a BV requirement of 120V, a 2µm p-type doping layer with a doping concentration of 10^14 cm⁻¹ is used. -3 The requirements can be met by using epitaxial layers on the left and right sides. To achieve a higher BV, the design requirements can be met by thickening the epitaxial layer and / or increasing the P-type doping concentration.

[0049] In some embodiments, the buried layer 15 is formed in a region of the first epitaxial layer 2 near the first surface of the substrate 1.

[0050] When a high voltage is applied to the drain region 7, the voltage drop mainly occurs in the region of the P-type first epitaxial layer 2. The first epitaxial layer 2 effectively increases the BV and prevents leakage from the drain region 7 to the TSV (i.e., the third conductive via 13). The p-type buried layer 15 acts as a lower field plate, ensuring that the electric field lines terminate at the p-type buried layer 15. Based on the above principles, this invention realizes an n-type LDMOS epitaxial device structure on a semi-insulating substrate 1. The semi-insulating substrate 1 effectively reduces device losses and increases the device operating frequency.

[0051] In some embodiments, a drift field plate 10 is further disposed within the insulating layer, and the drift field plate 10 is electrically connected to the source region metal 16 through a fourth conductive via 14 penetrating the insulating layer.

[0052] In some embodiments, a first portion of the drift field plate 10 is disposed above the drift region 3, and a second portion connected to the first portion extends above the gate 9 along a direction surrounding the side and top surface of the gate 9. The second portion is electrically connected to the source region metal 16 through the fourth conductive via 14. The drift field plate 10 partially surrounds the gate 9, increasing the area of ​​the drift field plate 10 that "wraps" the gate 9 and effectively reducing the coupling capacitance between the gate 9 and the drain region metal 17.

[0053] In some embodiments, a gate dielectric layer 19 is formed at least below the gate 9, the gate dielectric layer 19 isolating the gate 9 from the body region 4.

[0054] See Figures 2-5 This embodiment also provides a method for fabricating the above-mentioned LDMOS epitaxial structure, including the following steps:

[0055] The step of fabricating the first epitaxial layer 2 on the first surface of the semi-insulating substrate 1.

[0056] The step of fabricating a second epitaxial layer on the first epitaxial layer 2.

[0057] The step of fabricating the gate 9 on the epitaxial layer.

[0058] The steps of forming a body region 4, a drift region 3, a source region 5, a body contact region 6, a drift buffer zone 8, and a drain region 7 in the second epitaxial layer.

[0059] The step of forming an insulating layer on the second epitaxial layer.

[0060] The steps of fabricating a first conductive via 11, a second conductive via 12, a third conductive via 13, and a fourth conductive via 14 in the insulating layer.

[0061] The step of forming a first metal layer on the insulating layer.

[0062] The step of forming a second metal layer 18 on the second surface of the substrate 1.

[0063] In some embodiments, a first conductive type of buried layer 15 is first formed on a first surface of the substrate 1, and then a first epitaxial layer 2 is formed on the first surface of the substrate 1, and the buried layer 15 is buried by the first epitaxial layer 2.

[0064] In some embodiments, a first epitaxial layer 2 is first formed on a first surface of the substrate 1, and then a local region of the first epitaxial layer 2 near the first surface of the substrate 1 is subjected to ion implantation to form a buried layer 15 of a first conductivity type.

[0065] In some implementations, a body region 4, a drift region 3, a source region 5, a body contact region 6, a drift buffer zone 8, and a drain region 7 are formed in the second epitaxial layer by ion implantation.

[0066] In some embodiments, during the process of forming the body region 4, drift region 3, source region 5, body contact region 6, drift buffer 8 and drain region 7 in the second epitaxial layer by ion implantation, a buried layer 15 of a first conductivity type is also formed in a local region of the first epitaxial layer 2 near the first surface of the substrate 1.

[0067] In some embodiments, the fabrication method may further include the step of fabricating a drift field plate 10 on the second epitaxial layer.

[0068] As a typical application example, the method for fabricating the epitaxial structure of LDMOS provided by this invention specifically includes the following key steps:

[0069] Step 1: As Figure 2 As shown, on a substrate 1 having a p-type epitaxial region, either a p-type buried layer 15 is first epitaxially grown on the substrate 1 and then a p-type body region 4 is epitaxially grown again, or the buried layer 15 is first epitaxially grown and then ion implanted into the buried layer 15 to continue epitaxial growth of the p-type body region 4. Then an oxide layer (as the gate dielectric layer 19) is grown, a polysilicon gate is deposited, and the gate 9 is etched to form it.

[0070] Step Two: As Figure 3 As shown, various regions of the LDMOS device are formed by ion implantation using the gate 9 and the associated photomask layer; alternatively, a p-type buried layer 15 can be formed by ion implantation in this step.

[0071] Step 3: As Figure 4 As shown, deposition and etching are performed to form a field plate.

[0072] Step Four: As Figure 5As shown, an interlayer dielectric is formed, planarized (as the insulating layer), etched and filled to form deep vias and contact vias, and an interconnecting metal layer (i.e., the drain metal 17, source metal 16, second metal layer 18, and first conductive vias 11 to fourth conductive vias 14) is formed.

[0073] After using the buried layer 15, the p-type buried layer 15 below the gate 9 and the drift region 3 actually acts as a field plate, so that some electric field lines terminate at the buried layer 15 instead of the device surface. This reduces the surface electric field intensity when the device is working, reduces the hot carrier injection effect, and thus improves the reliability of the device.

[0074] See Figure 6 The present invention also provides a second embodiment. Figure 1 This reflects the first embodiment of the epitaxial structure provided by the present invention. Figure 6 This reflects a second embodiment of the epitaxial structure provided by the present invention. The difference between the first and second embodiments lies in the presence or absence of the p-type buried layer 15. The p-type buried layer 15 can be obtained by secondary epitaxy or ion implantation, or by first epitaxially eplasting the buried layer 15 and then ion implanting the buried layer 15, and then continuing to epitaxially eplastinate the p-type body region 4.

[0075] The method for fabricating the epitaxial structure in the second embodiment is similar to that in the first embodiment, except that it does not include the step of forming the buried layer 15.

[0076] Without a buried layer, the device process is relatively simple and the cost is reduced, but the hot carrier injection effect under the gate will be appropriately worsened, which reduces the maximum power density that can be achieved within the standard for safe use of the device. However, due to the combined effect of the first epitaxial layer and the semi-insulating substrate, the breakdown voltage performance and device performance of the second embodiment are still significantly better than those of the prior art.

[0077] Embodiments of the present invention also provide a device comprising the epitaxial structure described in any of the above embodiments.

[0078] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. An epitaxial structure of LDMOS, characterized in that, include: A first epitaxial layer is disposed on a first surface of a semi-insulating substrate. The first epitaxial layer is of a first conductivity type. The semi-insulating substrate includes a SiC substrate. The first conductivity type is p-type. A second epitaxial layer is disposed on the first epitaxial layer. The second epitaxial layer includes a body region and a drift region. A source region and a body contact region are disposed in the body region. The source region is in contact with the body contact region. A drift buffer region and a drain region are disposed in the drift region. The drift buffer region is disposed between the drain region and the drift region. An insulating layer is further disposed on the second epitaxial layer, a gate is disposed within the insulating layer, and a first metal layer is further disposed on the insulating layer. The first metal layer includes a source region metal and a drain region metal that are electrically isolated from each other. The source region metal is electrically connected to both the source region and the body contact region through a first conductive via penetrating the insulating layer, and the drain region metal is electrically connected to the drain region through a second conductive via penetrating the insulating layer. A second metal layer is further disposed on the second surface of the substrate opposite to the first surface. The source region metal is electrically connected to the second metal layer through a third conductive via that continuously penetrates the second epitaxial layer, the first epitaxial layer, and the substrate along the thickness direction.

2. The epitaxial structure according to claim 1, characterized in that, It also includes a buried layer of a first conductivity type, the buried layer being disposed on a first surface of the substrate and buried by a first epitaxial layer, and the third conductive via also passing through the buried layer.

3. The epitaxial structure according to claim 2, characterized in that, The buried layer is formed in the region of the first epitaxial layer near the first surface of the substrate.

4. The epitaxial structure according to claim 1, characterized in that, A drift field plate is also provided within the insulating layer, and the drift field plate is electrically connected to the source region metal through a fourth conductive via penetrating the insulating layer.

5. The epitaxial structure according to claim 4, characterized in that, The first part of the drift field plate is disposed above the drift region, and the second part connected to the first part extends above the gate along the direction surrounding the side and top surface of the gate. The second part is electrically connected to the source region metal through the fourth conductive via.

6. The epitaxial structure according to claim 1, characterized in that, A gate dielectric layer is formed at least below the gate, the gate dielectric layer isolating the gate from the body region.

7. A method for fabricating an epitaxial structure of LDMOS according to any one of claims 1-6, characterized in that, include: The step of fabricating the first epitaxial layer on the first surface of the semi-insulating substrate. The step of fabricating a second epitaxial layer on the first epitaxial layer. The step of fabricating the gate on the second epitaxial layer, The steps of forming a volume region, a drift region, a source region, a volume contact region, a drift buffer zone, and a drain region in the second epitaxial layer. The step of forming an insulating layer on the second epitaxial layer, The steps of fabricating a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via in the insulating layer. The step of forming the first metal layer on the insulating layer, The step of forming a second metal layer on the second surface of the substrate.

8. The manufacturing method according to claim 7, characterized in that, First, a buried layer of a first conductivity type is formed on the first surface of the substrate. Then, a first epitaxial layer is formed on the first surface of the substrate, and the buried layer is buried by the first epitaxial layer. Alternatively, a first epitaxial layer may be formed on the first surface of the substrate, and then ion implantation may be performed on a local area of ​​the first epitaxial layer near the first surface of the substrate to form a buried layer of the first conductivity type.

9. The manufacturing method according to claim 7, characterized in that, A body region, a drift region, a source region, a body contact region, a drift buffer zone, and a drain region are formed in the second epitaxial layer by ion implantation.

10. The manufacturing method according to claim 9, characterized in that, During the process of forming a body region, drift region, source region, body contact region, drift buffer zone, and drain region in the second epitaxial layer by ion implantation, a buried layer of a first conductivity type is also formed in a local area of ​​the first epitaxial layer near the first surface of the substrate.

11. The manufacturing method according to claim 7, characterized in that, The manufacturing method further includes the step of fabricating a drift field plate on the second epitaxial layer.

12. An LDMOS device, characterized in that... The epitaxial structure comprising any one of claims 1-6.

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