LDMOS device and method of manufacturing the same

Abstract

This application provides an LDMOS device and its fabrication method. The device includes a substrate and a well structure. The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The epitaxial layer is located on the substrate. The body region and the drift region are in contact and both are located within the epitaxial layer. The source region is located within the body region. The substrate, epitaxial layer, and body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. The well structure is located within the epitaxial layer and is situated on the side of the body region and drift region closest to the substrate. The well structure is in contact with the body region, drift region, and substrate, respectively. The well structure has the same doping type as the epitaxial layer, and its doping concentration is higher than that of the epitaxial layer. The well structure allows hole currents generated by avalanche phenomena to leave the substrate, ensuring high avalanche withstand capability and good reliability and stability of the LDMOS device.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically, to an LDMOS device and a method for fabricating the same. Background Technology

[0002] For power or switching LDMOS (Laterally Diffused Metal Oxide Semiconductor) FETs, due to the presence of inductive load and stray inductance, the energy stored in the inductor is released through the device at the moment of device turn-off, forcing the device to undergo avalanche breakdown. The resulting high voltage and high current surge can easily cause device failure. For RF LDMOS FETs, impedance mismatch during operation can also cause the device to enter an avalanche state, and low withstand capability can also lead to device failure. Therefore, improving the survivability of LDMOS FETs in avalanche mode, i.e., the ability to withstand high avalanche breakdown energy, is beneficial to improving the reliability, stability, and application range of the device. The avalanche breakdown energy withstand capability of a device is generally evaluated by Energy Avalanche Single Pulse (EAS) or Energy Avalanche Repetitive Pulse (EAR). Improving the avalanche breakdown energy withstand capability means improving EAS or EAR.

[0003] Currently, the main methods to improve the high avalanche breakdown energy of LDMOS FET devices are to adopt reasonable layout, better cell design, and optimized epitaxial materials. However, these methods only optimize and improve the external conditions and cannot improve the internal factors affecting EAS capability. This is because there is an unchangeable parasitic NPN transistor inside the cell. The internal parasitic NPN transistor is formed by the N-type source region, the P-type body region, and the N-type drift region. Although mature layouts short-circuit the N-type drift region and the P-type body region during lead hole routing, theoretically the device will not have secondary breakdown characteristics. However, during instantaneous switching, current will still flow through the body region. If the forward voltage drop generated by the lateral current flowing through the body region exceeds the forward turn-on voltage threshold of the parasitic NPN transistor (usually 0.7V), the parasitic NPN transistor will turn on. Once the parasitic NPN transistor turns on, it often enters a positive feedback state, thus causing secondary breakdown. Once secondary breakdown occurs, the device is prone to failure.

[0004] A higher avalanche withstand capability means better robustness. For switching devices, this translates to higher EAS (Electronic Avalanche Surcharge) and better Unclamped Inductive Switching (UIS) capability, resulting in better stability and a wider range of applications.

[0005] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0006] The main objective of this application is to provide an LDMOS device and its fabrication method to solve the problem of poor reliability and stability of the device due to its low avalanche withstand capability in the prior art.

[0007] According to one aspect of the present invention, an LDMOS device is provided, the LDMOS device including a substrate and a well structure, wherein the substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region, the epitaxial layer is located on the substrate, the body region is in contact with the drift region and is both located in the epitaxial layer, the source region is located in the body region, the substrate, the epitaxial layer, and the body region have the same doping type, the drift region has the same doping type as the source region but a different doping type than the epitaxial layer; the well structure is located in the epitaxial layer, and the well structure is located on the side of the body region and the drift region closer to the substrate, the well structure is in contact with the body region, the drift region, and the substrate, the well structure has the same doping type as the epitaxial layer, and the doping concentration of the well structure is higher than the doping concentration of the epitaxial layer.

[0008] Optionally, the substrate further includes a contact region, a buffer region, and a drain region, wherein the contact region is located in the body region and is located on the side of the source region away from the drift region, the contact region contacts the source region, the surface of the contact region away from the substrate is flush with the surface of the epitaxial layer away from the substrate, and the contact region and the epitaxial layer have the same doping type; the buffer region is located in the drift region, the surface of the buffer region away from the substrate is flush with the surface of the drift region away from the substrate; the drain region is located in the buffer region, the surface of the drain region away from the substrate is flush with the surface of the drift region away from the substrate.

[0009] Optionally, the epitaxial layer is located on a portion of a predetermined surface of the substrate. The LDMOS device further includes a source, a drain, and a metal layer. The source is located on a portion of the epitaxial layer away from the substrate, and the source contacts the source region and the contact region, respectively. The drain is located on a portion of the epitaxial layer away from the substrate, and the drain contacts the drain region. The metal layer is located on another portion of the predetermined surface of the substrate, and the surface of the metal layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The source also covers a portion of the surface of the metal layer away from the substrate, and the metal layer is used to electrically connect the source and the substrate.

[0010] Optionally, the LDMOS device further includes a gate oxide layer, a gate, and a field plate, wherein the gate oxide layer is located on the surface of the epitaxial layer away from the substrate, and the gate oxide layer covers a portion of the body region; the gate is located on the surface of the gate oxide layer away from the epitaxial layer; the field plate is located on the side of the gate away from the gate oxide layer, and the projection of the field plate in the epitaxial layer covers a portion of the body region and a portion of the drift region.

[0011] Optionally, the LDMOS device further includes a dielectric layer that covers the gate, the field plate, and the surface of the epitaxial layer away from the substrate, and the surface of the dielectric layer away from the epitaxial layer is planar.

[0012] Optionally, the well region structure includes a plurality of well regions stacked sequentially along the thickness direction of the substrate. Among the plurality of well regions, the well region closest to the substrate is in contact with the substrate, and the well region farthest from the substrate is in contact with the body region and the drift region, respectively.

[0013] Optionally, the epitaxial layer is doped with P-type doping and the drift region is doped with N-type doping.

[0014] According to another aspect of this application, a method for fabricating an LDMOS device is also provided. The method includes: providing a substrate; forming an epitaxial layer on the exposed surface of the substrate, and performing ion implantation on the epitaxial layer to obtain a well structure, wherein the well structure, the epitaxial layer, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer; performing ion implantation on the epitaxial layer to obtain a body region, a drift region, and a source region, wherein the body region is in contact with the drift region, the source region is located in the body region, the body region and the drift region are located on the side of the well structure away from the substrate, the well structure is in contact with the body region, the drift region, and the substrate, respectively, wherein the doping type of the epitaxial layer and the body region is the same, and the doping type of the drift region and the source region is the same but different from the doping type of the epitaxial layer.

[0015] Optionally, after ion implantation of the epitaxial layer to obtain a body region, a drift region, and a source region, the method further includes: ion implantation of the body region to obtain a contact region, the contact region being located on the side of the source region away from the drift region, the contact region contacting the source region, the surface of the contact region away from the substrate being flush with the surface of the epitaxial layer away from the substrate, and the contact region having the same doping type as the epitaxial layer; ion implantation of the drift region to obtain a buffer zone, the surface of the buffer zone away from the substrate being flush with the surface of the drift region away from the substrate; and ion implantation of the buffer zone to obtain a drain region, the surface of the drain region away from the substrate being flush with the surface of the drift region away from the substrate.

[0016] Optionally, after ion implantation into the buffer to obtain a drain region, the method further includes: removing a portion of the epitaxial layer to expose a portion of the substrate surface; forming a metal layer on the exposed surface of the substrate, wherein the surface of the metal layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate.

[0017] Optionally, forming an epitaxial layer on the exposed surface of the substrate and performing ion implantation on the epitaxial layer to obtain a well region structure includes: forming the epitaxial layer of a first predetermined thickness on the exposed surface of the substrate; forming a first oxide layer on the exposed surface of the epitaxial layer; performing at least one ion implantation on the epitaxial layer to obtain a plurality of well regions sequentially stacked along the thickness direction of the substrate, the plurality of well regions forming the well region structure; and removing the first oxide layer.

[0018] Optionally, forming an epitaxial layer on the exposed surface of the substrate and performing ion implantation on the epitaxial layer to obtain a well region structure includes: forming a first pre-epiaxial layer of a second predetermined thickness on the exposed surface of the substrate; forming a second oxide layer on the exposed surface of the first pre-epiaxial layer; performing ion implantation on the first pre-epiaxial layer to obtain a plurality of well regions sequentially stacked along the thickness direction of the substrate, the plurality of well regions forming the well region structure; removing the second oxide layer to expose the first pre-epiaxial layer; and forming a second pre-epiaxial layer of a third predetermined thickness on the exposed surface of the first pre-epiaxial layer, wherein the first pre-epiaxial layer and the second pre-epiaxial layer constitute the epitaxial layer.

[0019] Optionally, after obtaining the well region structure, the method further includes: forming a pre-gate oxide layer and a pre-gate layer sequentially stacked on the exposed surface of the epitaxial layer; removing a portion of the pre-gate oxide layer and a portion of the pre-gate layer to obtain a gate oxide layer and a gate.

[0020] Optionally, the material of the metal layer includes tungsten.

[0021] According to the technical solution of this application, the LDMOS device includes a substrate and a well structure. The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The epitaxial layer is located on the substrate. The body region and the drift region are in contact and both are located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. The well structure is located within the epitaxial layer and is located on the side of the body region and the drift region closest to the substrate. The well structure is in contact with the body region, the drift region, and the substrate, respectively. The well structure has the same doping type as the epitaxial layer, and the doping concentration of the well structure is higher than that of the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device of this application addresses this issue by incorporating a well structure within the epitaxial layer. This well structure contacts the body region, drift region, and substrate. Furthermore, the well structure shares the same doping type as the epitaxial layer, but with a higher doping concentration. This allows the well structure to provide hole paths during electron avalanche in the drift region, body region, and source region, guiding the avalanche-generated hole current away from the substrate. This mitigates the intensity of the avalanche current flowing through the body and source regions, ensuring high avalanche withstand capability and resolving the issue of poor reliability and stability caused by low avalanche withstand capability in existing technologies. The LDMOS device thus exhibits superior reliability and stability. Attached Figure Description

[0022] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0023] Figure 1 A schematic flowchart of a method for fabricating an LDMOS device according to an embodiment of this application is shown;

[0024] Figures 2 to 9 The diagrams show the structural schematics obtained after each process step in the fabrication method of an LDMOS device according to an embodiment of this application.

[0025] Figures 10 to 12 The diagrams show the structural schematics obtained after each process step of the fabrication method of an LDMOS device according to another embodiment of this application.

[0026] The above figures include the following reference numerals:

[0027] 10. Substrate; 20. Well structure; 30. Source; 40. Drain; 50. Metal layer; 60. Gate oxide layer; 70. Gate; 80. Field plate; 90. Dielectric layer; 100. First oxide layer; 101. Substrate; 102. Epitaxial layer; 103. Body region; 104. Drift region; 105. Source region; 106. Contact region; 107. Buffer zone; 108. Drain region; 110. First pre-epitaxial layer; 120. Second oxide layer; 130. Second pre-epitaxial layer; 140. Pre-gate oxide layer; 150. Pre-gate; 160. Back metal layer; 170. Connector layer; 201. Well region. Detailed Implementation

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0029] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0032] As mentioned in the background section, the existing technology suffers from poor reliability and stability due to the low avalanche withstand capability of the devices. In order to solve the above problems, a typical embodiment of this application provides an LDMOS device and a method for fabricating the same.

[0033] According to a typical embodiment of this application, an LDMOS device is provided, such as... Figure 9 As shown, the LDMOS device includes a substrate 10 and a well structure 20. The substrate 10 includes a substrate 101, an epitaxial layer 102, a body region 103, a drift region 104, and a source region 105. The epitaxial layer 102 is located on the substrate 101. The body region 103 and the drift region 104 are in contact and both are located within the epitaxial layer 102. The source region 105 is located within the body region 103. The substrate 101, the epitaxial layer 102, and the body region 103 have the same doping type. The drift region 104 and the source region 20 are in contact and both are located within the body region 103. The doping type of region 105 is the same as that of the epitaxial layer 102. The well structure 20 is located in the epitaxial layer 102 and is located on the side of the body region 103 and the drift region 104 that is close to the substrate 101. The well structure 20 is in contact with the body region 103, the drift region 104 and the substrate 101, respectively. The doping type of the well structure 20 is the same as that of the epitaxial layer 102, and the doping concentration of the well structure 20 is higher than that of the epitaxial layer 102.

[0034] The aforementioned LDMOS device includes a substrate and a well structure. The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The epitaxial layer is located on the substrate. The body region and the drift region are in contact and both are located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. The well structure is located within the epitaxial layer and is located on the side of the body region and the drift region closest to the substrate. The well structure is in contact with the body region, the drift region, and the substrate, respectively. The well structure has the same doping type as the epitaxial layer, and the doping concentration of the well structure is higher than that of the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device of this application addresses this issue by incorporating a well structure in the epitaxial layer. This well structure contacts the body region, drift region, and substrate. Furthermore, the well structure shares the same doping type as the epitaxial layer, but with a higher doping concentration. This allows the well structure to provide hole paths during electron avalanche in the drift region, body region, and source region, guiding the avalanche-generated hole current away from the substrate. This mitigates the intensity of the avalanche current flowing through the body and source regions, ensuring high avalanche withstand capability and resolving the issue of poor reliability and stability caused by low avalanche withstand capability in existing technologies. This results in superior reliability and stability for the LDMOS device.

[0035] Specifically, the well structure is located on the side of the drift region closest to the substrate, and the well structure is in contact with the drift region, reducing the surface electric field and surface collision ionization intensity. By mitigating the avalanche current intensity flowing through the body region and the source region, the turn-on of the parasitic NPN transistor is delayed. In addition, the well structure makes the current generated by avalanche charge exhibit a discrete distribution, which can mitigate the local temperature rise caused by avalanche current, further ensuring that the device has high avalanche withstand capability, and further ensuring that the LDMOS device has good reliability and stability.

[0036] In one specific embodiment, the well structure described above enables the LDMOS device to operate in a larger mismatch mode. For a switching mode MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the device can withstand greater avalanche energy, ensuring better robustness and allowing it to be used under more stringent conditions, thus expanding the application range of the device.

[0037] Specifically, the drift region is the pressure-bearing region of the LDMOS device, and the surface of the drift region and the source region away from the substrate is flush with the surface of the epitaxial layer away from the substrate.

[0038] According to a specific embodiment of this application, such as Figure 9 As shown, the substrate 10 further includes a contact region 106, a buffer zone 107, and a drain region 108. The contact region 106 is located in the body region 103 and is located on the side of the source region 105 away from the drift region 104. The contact region 106 is in contact with the source region 105. The surface of the contact region 106 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The contact region 106 and the epitaxial layer 102 have the same doping type. The buffer zone 107 is located in the drift region 104. The surface of the buffer zone 107 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The drain region 108 is located in the buffer zone 107. The surface of the drain region 108 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The aforementioned buffer can buffer the electric field concentration in the aforementioned drain region, thereby resulting in a higher breakdown voltage of the aforementioned LDMOS device. The aforementioned contact region can achieve a short circuit between the aforementioned source region and the aforementioned body region, avoiding the turn-on of the parasitic NPN transistor of the aforementioned device, further ensuring the good reliability and stability of the aforementioned LDMOS device.

[0039] According to another specific embodiment of this application, the epitaxial layer is located on a predetermined surface of the substrate, wherein the predetermined surface is the surface of the substrate adjacent to the epitaxial layer, such as... Figure 9As shown, the LDMOS device further includes a source 30, a drain 40, and a metal layer 50. The source 30 is located on a portion of the epitaxial layer 102 away from the substrate 101, and is in contact with both the source region 105 and the contact region 106. The drain 40 is located on a portion of the epitaxial layer 102 away from the substrate 101, and is in contact with the drain region 108. The metal layer 50 is located on another portion of the predetermined surface of the substrate 101, and the surface of the metal layer 50 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The source 30 also covers a portion of the surface of the metal layer 50 away from the substrate 101. The metal layer 50 is used to electrically connect the source 30 and the substrate 101. By electrically connecting the source and the substrate, the metal layer grounds the source, further ensuring the reliability and stability of the LDMOS device.

[0040] Specifically, such as Figure 9 As shown, the LDMOS device further includes a connection layer 170 and a back metal layer 160. The connection layer 170 is located on the side of the metal layer 50 near the epitaxial layer 102. The connection layer 170 is in contact with the metal layer 50, the source electrode 30, the substrate 101 and the epitaxial layer 102 respectively. The connection layer 170 is used to electrically connect the body region 103 and the substrate 101. The back metal layer is located on the surface of the substrate 101 away from the epitaxial layer 102.

[0041] According to another specific embodiment of this application, such as Figure 9 As shown, the LDMOS device further includes a gate oxide layer 60, a gate 70, and a field plate 80. The gate oxide layer 60 is located on the surface of the epitaxial layer 102 away from the substrate 101, and covers a portion of the body region 103. The gate 70 is located on the surface of the gate oxide layer 60 away from the epitaxial layer 102. The field plate 80 is located on the side of the gate 70 away from the gate oxide layer 60, and its projection in the epitaxial layer 102 covers a portion of the body region 103 and a portion of the drift region 104. By forming the gate oxide layer, the gate, and the field plate, the LDMOS device achieves good performance.

[0042] According to a specific embodiment of this application, such as Figure 9 As shown, the LDMOS device further includes a dielectric layer 90, which covers the gate 70, the field plate 80, and the surface of the epitaxial layer 102 away from the substrate 101, and the surface of the dielectric layer 90 away from the epitaxial layer 102 is planar.

[0043] To further ensure the good performance of the aforementioned LDMOS device, according to another specific embodiment of this application, such as... Figure 9 As shown, the well structure 20 includes a plurality of well regions 201 stacked sequentially along the thickness direction of the substrate 101. Among the plurality of well regions 201, the well region 201 closest to the substrate 101 is in contact with the substrate 101, and the well region 201 farthest from the substrate 101 is in contact with the body region 103 and the drift region 104, respectively. By setting the well region farthest from the substrate in contact with the body region, the hole current in the body region can be shunted and the hole current can be introduced into the substrate, thereby mitigating the avalanche current intensity flowing through the body region and the source region. This further ensures that the device has a high avalanche withstand capability, solving the problem of poor reliability and stability of the device due to the low avalanche withstand capability in the prior art, and further ensuring that the LDMOS device has good reliability and stability.

[0044] Specifically, the aforementioned well structure is formed through at least one ion implantation, and the doping concentration of the multiple well regions can be adjusted according to actual needs, and the doping concentration of the multiple well regions can be different. In one specific embodiment, the well regions in the aforementioned well structure that are in contact with the aforementioned substrate have a higher doping concentration.

[0045] In one specific embodiment, the P-type doped well region structure and the N-type doped drift region form a PN junction. In this case, the well region structure acts as a side field plate, which can reduce the surface electric field intensity of the device and pull the collision ionization center of the device into the device body, thereby reducing the surface collision ionization intensity and improving the reliability of the device. The multi-layered well region acts as a hole path. MOSFETs are unipolar devices. When the device is working, electrons generated by impact ionization can leave the device from the drain. Holes leave the device more often through the path between the body region and the contact region of the P-type transistor. Under high output power, the impact ionization intensity of the device gradually increases. When the MOSFET is turned off, the induced electromotive force can easily cause the device to enter avalanche mode. Although the body region is grounded together with the source through the contact region, as the hole current flowing through the body region gradually increases, when the forward voltage drop generated by the lateral current flowing through the body region exceeds the forward turn-on voltage threshold of the PN junction of the body region and the source region of the parasitic NPN transistor, the parasitic NPN transistor will turn on. The resulting high current will burn out the device. The impact ionization of the device often leads to the turn-on of the parasitic NPN transistor, and high electric field strength and high current strength will produce even higher impact ionization intensity. The side field plate effect of the PN junction formed by the top-layer well region and the drift region reduces the surface electric field intensity, thereby pulling the collisional ionization center of the device into the device body. This facilitates the exit of hole current from the bottom-layer well region. The well region structure itself extends to the substrate, forming a hole current path. In this way, the holes generated by collisional ionization can leave directly from the substrate. The multi-layer well region simultaneously acts as a side field plate and shunts the hole current generated by collisional ionization. The current density flowing through the path of the body region and the source region is reduced, thereby delaying the turn-on of the parasitic NPN transistor of the device and ensuring that the device has high avalanche withstand capability. The discrete current distribution can also reduce local thermal effects, and the device has better stability.

[0046] According to a specific embodiment of this application, the doping type of the epitaxial layer is P-type, and the doping type of the drift region is N-type.

[0047] Specifically, the doping type of the aforementioned well structure is P-type.

[0048] In one specific embodiment, the avalanche phenomenon refers to the phenomenon in a PN junction with a low doping concentration where, as the reverse voltage of the PN junction increases, the electric field in the space charge region strengthens. As a result, electrons passing through the space charge region gain more energy under the influence of the electric field. Electrons moving in the crystal will continuously collide with crystal atoms. Through these collisions, valence electrons bound in covalent bonds can be ejected, generating free electrons and holes. The newly generated free electrons, under the influence of the electric field, knock out other valence electrons, generating even more free electrons and holes. This chain reaction causes the number of charge carriers in the barrier layer to increase avalanche-like, and the current flowing through the PN junction increases sharply, leading to the breakdown of the PN junction. This collisional ionization leading to breakdown is called avalanche breakdown, also known as electron avalanche.

[0049] According to an embodiment of this application, a method for fabricating an LDMOS device is also provided.

[0050] Figure 1 This is a flowchart illustrating a method for fabricating an LDMOS device according to an embodiment of this application. For example... Figure 1 As shown, the method includes the following steps:

[0051] Step S101, as follows Figure 2 As shown, a substrate 101 is provided;

[0052] Step S102, as follows Figure 4 As shown, an epitaxial layer 102 is formed on the exposed surface of the substrate 101, and ion implantation is performed on the epitaxial layer 102 to obtain a well structure 20. The well structure 20, the epitaxial layer 102 and the substrate 101 have the same doping type, and the doping concentration of the well structure 20 is higher than that of the epitaxial layer 102.

[0053] Step S103, as follows Figure 7 As shown, ion implantation is performed on the epitaxial layer 102 to obtain a body region 103, a drift region 104, and a source region 105. The body region 103 is in contact with the drift region 104, and the source region 105 is located in the body region 103. The body region 103 and the drift region 104 are located on the side of the well structure 20 away from the substrate 101. The well structure 20 is in contact with the body region 103, the drift region 104, and the substrate 101, respectively. The epitaxial layer 102 and the body region 103 have the same doping type, while the drift region 104 and the source region 105 have the same doping type but a different doping type from the epitaxial layer 102.

[0054] In the above-described method for fabricating an LDMOS device, firstly, a substrate is provided; then, an epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well structure. The well structure, the epitaxial layer, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer. Finally, ion implantation is performed on the epitaxial layer to obtain a body region, a drift region, and a source region. The body region is in contact with the drift region, the source region is located in the body region, and the body region and the drift region are located on the side of the well structure away from the substrate. The well structure is in contact with the body region, the drift region, and the substrate, respectively. The epitaxial layer and the body region have the same doping type, and the drift region and the source region have the same doping type but different doping type from the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device fabrication method of this application provides a substrate, forms an epitaxial layer on the surface of the substrate, and then performs ion implantation on the epitaxial layer to obtain a well structure. The well structure, the epitaxial layer, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer. Finally, the body region, the drift region, and the source region are obtained through ion implantation. The well structure is identical to the body region, the drift region, and the substrate. The doping types of the epitaxial layer and the body region are the same, while the doping types of the drift region and the source region are the same but different from those of the epitaxial layer. This allows the well structure to provide hole paths when electron avalanche occurs in the drift region, the body region, and the source region, guiding the hole current generated by the avalanche away from the substrate. This alleviates the intensity of the avalanche current flowing through the body region and the source region, ensuring that the device has high avalanche withstand capability. This solves the problem of poor reliability and stability of the device due to low avalanche withstand capability in the prior art, and ensures good reliability and stability of the LDMOS device.

[0055] According to a specific embodiment of this application, after ion implantation is performed on the epitaxial layer to obtain the bulk region, drift region, and source region, the method further includes: as follows: Figure 7As shown, ion implantation is performed on the body region 103 to obtain a contact region 106. The contact region 106 is located on the side of the source region 105 away from the drift region 104. The contact region 106 is in contact with the source region 105. The surface of the contact region 106 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The contact region 106 and the epitaxial layer 102 have the same doping type. Ion implantation is performed on the drift region 104 to obtain a buffer zone 107. The surface of the buffer zone 107 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. Ion implantation is performed on the buffer zone 107 to obtain a drain region 108. The surface of the drain region 108 away from the substrate 101 is flush with the surface of the drift region 104 away from the substrate 101. The aforementioned buffer can buffer the electric field concentration in the aforementioned drain region, thereby resulting in a higher breakdown voltage of the aforementioned LDMOS device. The aforementioned contact region can achieve a short circuit between the aforementioned source region and the aforementioned body region, avoiding the turn-on of the parasitic NPN transistor of the aforementioned device, further ensuring the good reliability and stability of the aforementioned LDMOS device.

[0056] According to another specific embodiment of this application, after ion implantation is performed on the above-mentioned buffer to obtain the drain region, the above method further includes: as follows Figure 7 As shown, a portion of the epitaxial layer 102 is removed, exposing a portion of the surface of the substrate 101; as Figure 8 As shown, a metal layer 50 is formed on the exposed surface of the substrate 101, and the surface of the metal layer 50 away from the substrate 101 is flush with the surface of the epitaxial layer 102 away from the substrate 101. The metal layer connects the source electrode and the substrate, grounding the source electrode and further ensuring the reliability and stability of the LDMOS device.

[0057] According to another specific embodiment of this application, an epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well region structure, including: as... Figure 2 As shown, an epitaxial layer 102 of a first predetermined thickness is formed on the exposed surface of the substrate 101; a first oxide layer 100 is formed on the exposed surface of the epitaxial layer 102; as... Figure 3 As shown, the epitaxial layer 102 is subjected to at least one ion implantation to obtain a plurality of well regions 201 sequentially stacked along the thickness direction of the substrate 101, and the plurality of well regions 201 form the well region structure 20; as Figure 4As shown, the first oxide layer 100 is removed. By first forming the first oxide layer on the exposed surface of the epitaxial layer, and then ion implanting the epitaxial layer to form multiple well regions stacked sequentially along the thickness direction of the substrate, the first oxide layer can serve as a protective layer for the multiple well regions. This allows the well regions to allow holes generated by avalanches to leave through the substrate, further ensuring that the device has a high avalanche withstand capability. This solves the problem of poor reliability and stability of the device due to low avalanche withstand capability in the prior art, and ensures that the LDMOS device has good reliability and stability.

[0058] In one specific embodiment, if the epitaxial layer is relatively thin, the well structure is mainly obtained by the above method, that is, by directly growing the epitaxial layer of a first predetermined thickness and then forming the well structure.

[0059] When the epitaxial layer is relatively thick, the well structure can also be formed in other ways. According to a specific embodiment of this application, an epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well structure, including: Figure 10 As shown, a first pre-epitaxial layer 110 of a second predetermined thickness is formed on the exposed surface of the substrate 101; a second oxide layer 120 is formed on the exposed surface of the first pre-epitaxial layer 110; as shown... Figure 11 As shown, ion implantation is performed on the first pre-epithetical layer 110 to obtain a plurality of well regions 201 sequentially stacked along the thickness direction of the substrate 101, and the plurality of well regions 201 form the well region structure 20; as Figure 12 As shown, the second oxide layer 120 is removed to expose the first pre-epipolar layer 110; as Figure 12 As shown, a second pre-epiaxial layer 130 of a third predetermined thickness is formed on the exposed surface of the first pre-epiaxial layer 110. The first pre-epiaxial layer 110 and the second pre-epiaxial layer 130 constitute the epitaxial layer 102. When the epitaxial layer is relatively thick, by first forming the first pre-epiaxial layer of the second predetermined thickness, and then forming the second oxide layer on the exposed surface of the first pre-epiaxial layer, it is ensured that the second oxide layer can protect the subsequently formed well structure. Then, the well structure is obtained by ion implantation of the first pre-epiaxial layer. Finally, the second oxide layer is removed, and the second pre-epiaxial layer of the third predetermined thickness is formed. The first pre-epiaxial layer and the second pre-epiaxial layer constitute the epitaxial layer. This ensures that the ion implantation energy is low, and at the same time, it ensures that the ion implantation process causes less damage to the epitaxial layer, further ensuring the good reliability and stability of the LDMOS device.

[0060] Specifically, after removing the second oxide layer using a standard cleaning method, the second preparatory epitaxial layer is grown using a wet oxygen method.

[0061] According to another specific embodiment of this application, after obtaining the well region structure, the above method further includes: as follows Figure 5 As shown, a pre-gate oxide layer 140 and a pre-gate electrode 150 are sequentially stacked on the exposed surface of the epitaxial layer 102; as Figure 6 As shown, by removing part of the above-mentioned pre-gate oxide layer 140 and part of the above-mentioned pre-gate 150, gate oxide layer 60 and gate 70 are obtained.

[0062] Specifically, after forming the above-mentioned pre-gate, doping is performed at the target concentration, and the gate is etched to obtain the above-mentioned gate.

[0063] According to another specific embodiment of this application, the material of the metal layer includes tungsten.

[0064] In the above embodiments of the present invention, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0065] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0066] 1) The LDMOS device described above in this application includes a substrate and a well structure. The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The epitaxial layer is located on the substrate. The body region is in contact with the drift region and is located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. The well structure is located within the epitaxial layer and is located on the side of the body region and the drift region closest to the substrate. The well structure is in contact with the body region, the drift region, and the substrate. The well structure has the same doping type as the epitaxial layer, and the doping concentration of the well structure is higher than that of the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device of this application addresses this issue by incorporating a well structure in the epitaxial layer. This well structure contacts the body region, drift region, and substrate. Furthermore, the well structure shares the same doping type as the epitaxial layer, but with a higher doping concentration. This allows the well structure to provide hole paths during electron avalanche in the drift region, body region, and source region, guiding the avalanche-generated hole current away from the substrate. This mitigates the intensity of the avalanche current flowing through the body and source regions, ensuring high avalanche withstand capability and resolving the issue of poor reliability and stability caused by low avalanche withstand capability in existing technologies. This results in superior reliability and stability for the LDMOS device.

[0067] 2) In the fabrication method of the LDMOS device described above in this application, firstly, a substrate is provided; then, an epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well structure. The doping types of the well structure, the epitaxial layer, and the substrate are the same, and the doping concentration of the well structure is higher than that of the epitaxial layer. Finally, ion implantation is performed on the epitaxial layer to obtain a body region, a drift region, and a source region. The body region is in contact with the drift region, the source region is located in the body region, and the body region and the drift region are located on the side of the well structure away from the substrate. The well structure is in contact with the body region, the drift region, and the substrate, respectively. The doping types of the epitaxial layer and the body region are the same, and the doping types of the drift region and the source region are the same but different from the doping type of the epitaxial layer. Compared to existing technologies where low avalanche withstand capability leads to poor reliability and stability, the LDMOS device fabrication method of this application provides a substrate, forms an epitaxial layer on the surface of the substrate, and then performs ion implantation on the epitaxial layer to obtain a well structure. The well structure, the epitaxial layer, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer. Finally, the body region, the drift region, and the source region are obtained through ion implantation. The well structure is identical to the body region, the drift region, and the substrate. The doping types of the epitaxial layer and the body region are the same, while the doping types of the drift region and the source region are the same but different from those of the epitaxial layer. This allows the well structure to provide hole paths when electron avalanche occurs in the drift region, the body region, and the source region, guiding the hole current generated by the avalanche away from the substrate. This alleviates the intensity of the avalanche current flowing through the body region and the source region, ensuring that the device has high avalanche withstand capability. This solves the problem of poor reliability and stability of the device due to low avalanche withstand capability in the prior art, and ensures good reliability and stability of the LDMOS device.

[0068] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An LDMOS device, characterized in that, include: The substrate includes a substrate, an epitaxial layer, a body region, a drift region, and a source region. The epitaxial layer is located on the substrate. The body region is in contact with the drift region and is located within the epitaxial layer. The source region is located within the body region. The substrate, the epitaxial layer, and the body region have the same doping type. The drift region has the same doping type as the source region but a different doping type than the epitaxial layer. A well region structure is located in the epitaxial layer, and the well region structure is located on the side of the body region and the drift region close to the substrate. The well region structure is in contact with the body region, the drift region and the substrate, respectively. The doping type of the well region structure is the same as that of the epitaxial layer, and the doping concentration of the well region structure is higher than that of the epitaxial layer.

2. The LDMOS device according to claim 1, characterized in that, The substrate also includes: A contact region is located in the body region and is located on the side of the source region away from the drift region. The contact region is in contact with the source region. The surface of the contact region away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The contact region and the epitaxial layer have the same doping type. A buffer zone is located within the drift region, wherein the surface of the buffer zone away from the substrate is flush with the surface of the drift region away from the substrate; A drain region, located in the buffer zone, has a surface of the drain region away from the substrate that is flush with the surface of the drift region away from the substrate.

3. The LDMOS device according to claim 2, characterized in that, The epitaxial layer is located on a predetermined surface of the substrate, and the LDMOS device further includes: The source electrode is located on the portion of the epitaxial layer away from the substrate, and the source electrode is in contact with both the source region and the contact region. The drain electrode is located on the portion of the epitaxial layer away from the substrate, and the drain electrode is in contact with the drain region. A metal layer is located on another portion of the predetermined surface of the substrate, and the surface of the metal layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The source also covers a portion of the surface of the metal layer away from the substrate, and the metal layer is used to electrically connect the source to the substrate.

4. The LDMOS device according to claim 1, characterized in that, The LDMOS device also includes: A gate oxide layer is located on the surface of the epitaxial layer away from the substrate, and the gate oxide layer covers a portion of the body region; The gate is located on the surface of the gate oxide layer that is away from the epitaxial layer; A field plate is located on the side of the gate away from the gate oxide layer, and the projection of the field plate in the epitaxial layer covers a portion of the body region and a portion of the drift region.

5. The LDMOS device according to claim 4, characterized in that, The LDMOS device also includes: A dielectric layer covers the gate, the field plate, and the surface of the epitaxial layer away from the substrate, and the surface of the dielectric layer away from the epitaxial layer is planar.

6. The LDMOS device according to claim 1, characterized in that, The well region structure includes a plurality of well regions stacked sequentially along the thickness direction of the substrate. Among the plurality of well regions, the well region closest to the substrate is in contact with the substrate, and the well region farthest from the substrate is in contact with the body region and the drift region, respectively.

7. The LDMOS device according to any one of claims 1 to 6, characterized in that, The epitaxial layer is doped with P-type, and the drift region is doped with N-type.

8. A method for fabricating an LDMOS device, characterized in that, The method includes: Provide substrate; An epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well structure. The well structure, the epitaxial layer, and the substrate have the same doping type, and the doping concentration of the well structure is higher than that of the epitaxial layer. Ion implantation is performed on the epitaxial layer to obtain a body region, a drift region, and a source region. The body region is in contact with the drift region, and the source region is located in the body region. The body region and the drift region are located on the side of the well region structure away from the substrate. The well region structure is in contact with the body region, the drift region, and the substrate, respectively. The epitaxial layer and the body region have the same doping type, and the drift region and the source region have the same doping type but different doping type from the epitaxial layer.

9. The method according to claim 8, characterized in that, After ion implantation of the epitaxial layer to obtain the bulk region, drift region, and source region, the method further includes: Ion implantation is performed on the body region to obtain a contact region. The contact region is located on the side of the source region away from the drift region. The contact region is in contact with the source region. The surface of the contact region away from the substrate is flush with the surface of the epitaxial layer away from the substrate. The doping type of the contact region and the epitaxial layer is the same. Ion implantation is performed on the drift region to obtain a buffer zone, wherein the surface of the buffer zone away from the substrate is flush with the surface of the drift region away from the substrate; Ion implantation is performed on the buffer zone to obtain a drain region, wherein the surface of the drain region away from the substrate is flush with the surface of the drift region away from the substrate.

10. The method according to claim 9, characterized in that, After performing ion implantation on the buffer to obtain a drain region, the method further includes: Remove a portion of the epitaxial layer, thereby exposing a portion of the substrate surface; A metal layer is formed on the exposed surface of the substrate, wherein the surface of the metal layer away from the substrate is flush with the surface of the epitaxial layer away from the substrate.

11. The method according to claim 8, characterized in that, An epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well region structure, including: An epitaxial layer of a first predetermined thickness is formed on the exposed surface of the substrate; A first oxide layer is formed on the exposed surface of the epitaxial layer; The epitaxial layer is subjected to at least one ion implantation to obtain a plurality of well regions that are sequentially stacked along the thickness direction of the substrate, and the plurality of well regions form the well region structure; Remove the first oxide layer.

12. The method according to claim 8, characterized in that, An epitaxial layer is formed on the exposed surface of the substrate, and ion implantation is performed on the epitaxial layer to obtain a well region structure, including: A first pre-epipolar layer of a second predetermined thickness is formed on the exposed surface of the substrate; A second oxide layer is formed on the exposed surface of the first prepared epitaxial layer; Ion implantation is performed on the first pre-epithetical layer to obtain a plurality of well regions that are sequentially stacked along the thickness direction of the substrate, and the plurality of well regions form the well region structure; Remove the second oxide layer to expose the first prepared epitaxial layer; A second pre-epitaxial layer of a third predetermined thickness is formed on the exposed surface of the first pre-epitaxial layer, wherein the first pre-epitaxial layer and the second pre-epitaxial layer constitute the epitaxial layer.

13. The method according to claim 8, characterized in that, After obtaining the well region structure, the method further includes: A pre-gate oxide layer and a pre-gate are formed sequentially on the exposed surface of the epitaxial layer; Remove a portion of the prepared gate oxide layer and a portion of the prepared gate to obtain the gate oxide layer and the gate.

14. The method according to claim 10, characterized in that, The material of the metal layer includes tungsten.

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