A composite GaN-based Schottky barrier diode and its fabrication method

Abstract

This invention discloses a composite GaN-based Schottky barrier diode and its fabrication method. The composite GaN-based Schottky barrier diode includes a substrate layer, several heterojunction layers, a transport layer, a drift layer, a dielectric layer, an anode, and a cathode. Several heterojunction layers are sequentially stacked on the substrate layer. The transport layer is disposed on the heterojunction layers. The drift layer is disposed on the transport layer. The dielectric layer is disposed on the inner surfaces of the transport layer and the drift layer. The anode is disposed on the top surface of the drift layer, the side surface of the dielectric layer, and the outer surface of the heterojunction layers. The cathode is disposed on the top surface of the transport layer, the outer surface of the dielectric layer, and the outer surface of the heterojunction layers. In the composite GaN-based Schottky barrier diode fabricated by this invention, the groove design allows the top of the anode to contact the GaN drift layer, and the sides and bottom of the anode to contact multiple heterojunction structures, resulting in lower on-resistance and stronger current driving capability of the device.

Description

Technical Field

[0001] This invention relates to the field of microelectronic device technology, specifically to a composite GaN-based Schottky barrier diode and its fabrication method. Background Technology

[0002] Compared to first-generation semiconductor material Si and second-generation semiconductor material GaAs, third-generation wide-bandgap semiconductors, represented by SiC and GaN, have advantages such as higher breakdown electric field strength and higher electron saturation velocity. Therefore, theoretically, GaN power devices can achieve lower on-resistance and higher breakdown voltage, significantly improving power density and power consumption efficiency. On the other hand, GaN material has a wider bandgap (3.44 eV) and lower intrinsic carrier concentration than traditional semiconductor materials. Therefore, GaN devices can operate at high temperatures above 200°C and under irradiation environments, resulting in higher reliability and stability.

[0003] Current GaN-based power diodes mainly consist of two types: lateral and vertical. Lateral devices are formed by epitaxially layering a heterojunction structure on the channel layer. Utilizing the polarization effect of the GaN-based material system, a two-dimensional electron gas (2DEG) is generated at the heterojunction interface as a conductive channel. Because the 2DEG areal density and mobility in the channel are both high, lateral devices can achieve extremely low on-resistance. In particular, multi-channel lateral GaN-based Schottky barrier diodes, which have been widely studied in recent years, significantly reduce on-resistance by stacking multiple heterojunctions between the anode and cathode to form multiple parallel 2DEG conductive paths, which is beneficial for realizing high-voltage, high-power devices. However, current collapse is a serious problem in lateral devices. Vertical devices conduct electricity through doped GaN bulk material. Due to the high cost of GaN self-supporting substrates, vertical devices are mostly heteroepitaxial quasi-vertical devices based on sapphire or Si substrates. For quasi-vertical devices, since the electrodes are on the same side, a current convergence effect will occur when conducting in the forward direction, which leads to uneven heat distribution and affects the current driving capability of the device.

[0004] Therefore, the development of a composite GaN-based Schottky barrier diode and its fabrication method has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to improve the forward current driving capability of GaN-based Schottky diodes, thereby enabling the fabrication of high-power devices.

[0006] To solve the above-mentioned technical problems, the technical solution provided by the present invention is: a composite GaN-based Schottky barrier diode, wherein the composite GaN-based Schottky barrier diode includes a substrate layer, several heterojunction layers, a transport layer, a drift layer, a dielectric layer, an anode, and a cathode;

[0007] The plurality of heterojunction layers are sequentially stacked on the substrate layer;

[0008] The transport layer is disposed on the heterojunction layer;

[0009] The drift layer is disposed on the transmission layer;

[0010] The dielectric layer is disposed on the inner surface of the transport layer and the drift layer;

[0011] The top surface of the anode contact drift layer, the side surface of the dielectric layer, and the inner surface of the heterojunction layer;

[0012] The top surface, outer surface, and outer surface of the cathode contact transport layer and the heterojunction layer.

[0013] Furthermore, the substrate layer may be made of materials including, but not limited to, sapphire and Si.

[0014] Furthermore, the heterojunction layer includes a GaN channel layer and an AlGaN barrier layer arranged from bottom to top; the GaN channel layer and the AlGaN barrier layer form an AlGaN / GaN heterojunction, the AlGaN layer has a thickness of 15~25nm, the molar fraction of Al is 25~35%, and the GaN layer has a thickness of 25-75nm.

[0015] Furthermore, the transport layer is an n-type heavily doped GaN transport layer, and the thickness of the n-type heavily doped GaN transport layer is 1-3 μm;

[0016] The drift layer is an n-type lightly doped GaN drift layer, and the thickness of the n-type lightly doped GaN drift layer is 1-9 μm.

[0017] Furthermore, the thickness of the dielectric layer is 50nm-100nm.

[0018] A method for fabricating a composite GaN-based Schottky barrier diode includes fabricating a composite GaN-based Schottky barrier diode, the method of which is as follows:

[0019] Step 1: Select sapphire or Si as the substrate layer;

[0020] Step 2: On the substrate, a GaN buffer layer and several heterojunction layers are grown sequentially;

[0021] Step 3: Grow n-type heavily doped GaN transport layers and n-type lightly doped GaN drift layers on several heterojunction layers.

[0022] Step 4: Set a mesa on the epitaxial layer structure for side cathode contact;

[0023] Step 5: Set a mesa on the epitaxial layer structure for top cathode contact;

[0024] Step 6: Fabricate cathodes on the sides of several heterojunction layers and the top surface of the transport layer;

[0025] Step 7: Use ICP etching technology to etch the drift layer and transport layer in the anode groove region;

[0026] Step 8: Deposit a dielectric layer on the etched area using PECVD process;

[0027] Step 9: Use ICP etching technology to etch the dielectric layer and several heterojunction layers in the anode groove region to ensure that the AlGaN layer in the anode groove region is completely removed;

[0028] Step 10: Fabricate the anode in the anode groove area.

[0029] The advantages of this invention compared to the prior art are as follows: In the composite GaN-based Schottky barrier diode prepared by this invention, the top of the anode is in contact with the GaN drift layer through the groove design, and the sides and bottom of the anode are in contact with multiple heterojunction structures. Through the mesa design, the cathode is in contact with the GaN transport layer and multiple heterojunction structures from the sides and top. Overall, multiple parallel conductive paths are formed between the anode and cathode of the device, resulting in lower on-resistance and stronger current driving capability of the device.

[0030] The composite GaN-based Schottky barrier diode prepared by this invention can effectively alleviate the current pooling effect in the quasi-vertical structure by introducing a multi-channel lateral structure in parallel with a quasi-vertical structure, making the current distribution more uniform when the device is working, which is beneficial to improving the reliability of the device. The design of this invention is reasonable and worthy of widespread promotion. Attached Figure Description

[0031] Figure 1 This is a schematic cross-sectional view of a composite GaN-based Schottky barrier diode according to the present invention.

[0032] Figure 2 This is a process flow diagram of the fabrication method of a composite GaN-based Schottky barrier diode according to the present invention.

[0033] As shown in the figure: 1. Substrate layer, 2. Heterojunction layer, 3. Transport layer, 4. Drift layer, 5. Dielectric layer, 6. Anode, 7. Cathode, 8. GaN channel layer, 9. AlGaN barrier layer. Detailed Implementation

[0034] The following detailed description, in conjunction with the accompanying drawings, illustrates a composite GaN-based Schottky barrier diode and its fabrication method according to the present invention.

[0035] Combined with appendix Figure 1-2 This invention will be described in detail below.

[0036] A composite GaN-based Schottky barrier diode, the composite GaN-based Schottky barrier diode comprising a substrate layer 1, several heterojunction layers 2, a transport layer 3, a drift layer 4, a dielectric layer 5, an anode 6, and a cathode 7;

[0037] The plurality of heterojunction layers 2 are sequentially stacked on the substrate layer 1;

[0038] The transport layer 3 is disposed on the heterojunction layer 2;

[0039] The drift layer 4 is disposed on the transmission layer 3;

[0040] The dielectric layer 5 is disposed on the inner surface of the transmission layer 3 and the drift layer 4;

[0041] The anode 6 is disposed on the top surface of the drift layer 4, the side surface of the dielectric layer 5, and the outer surface of the heterogeneous layer 2;

[0042] The cathode 7 is disposed on the top surface, outer surface, and outer surface of the transmission layer 3 and the heterojunction layer 2.

[0043] The substrate layer 1 is made of materials including, but not limited to, sapphire and Si.

[0044] The heterojunction layer 2 includes a GaN channel layer 8 and an AlGaN barrier layer 9 arranged from bottom to top; the GaN channel layer 8 and the AlGaN barrier layer 9 form an AlGaN / GaN heterojunction, the AlGaN layer has a thickness of 15~25nm, the molar fraction of Al is 25~35%, and the GaN layer has a thickness of 25-75nm.

[0045] The transport layer 3 is an n-type heavily doped GaN transport layer, and the thickness of the n-type heavily doped GaN transport layer is 1-3 μm;

[0046] The drift layer 4 is an n-type lightly doped GaN drift layer with a thickness of 1-9 μm.

[0047] The thickness of the dielectric layer 5 is 50nm-100nm.

[0048] A method for fabricating a composite GaN-based Schottky barrier diode includes fabricating a composite GaN-based Schottky barrier diode, the method of which is as follows:

[0049] Step 1: Select sapphire or Si as substrate layer 1;

[0050] Step 2: On substrate 1, a GaN buffer layer and several heterojunction layers 2 are grown sequentially.

[0051] Step 3: Grow n-type heavily doped GaN transport layers and n-type lightly doped GaN drift layers on several heterojunction layers 2.

[0052] Step 4: Set a mesa on the epitaxial layer structure for contact with the side cathode 7;

[0053] Step 5: Set a mesa on the epitaxial layer structure for contact with the top cathode 7;

[0054] Step 6: Fabricate cathodes on the sides of several heterojunction layers 2 and the top surface of transport layer 3;

[0055] Step 7: ICP etching is used to etch the drift layer 4 and transport layer 3 in the anode groove region;

[0056] Step 8: Using PECVD process, deposit a dielectric layer 5 on the etched area;

[0057] Step 9: Use ICP etching technology to etch the dielectric layer 5 and several heterojunction layers 2 in the anode groove region to ensure that the AlGaN layer in the anode groove region is completely removed.

[0058] Step 10: Fabricate anode 6 in the anode groove area.

[0059] The specific implementation process of the composite GaN-based Schottky barrier diode and its fabrication method of the present invention is as follows:

[0060] Example 1

[0061] Step 1: Select sapphire or Si as substrate layer 1;

[0062] Step 2: On a sapphire substrate or Si substrate layer 1, GaN channel layer 8 and AlGaN barrier layer 9 are repeatedly grown to form a double AlGaN / GaN heterojunction layer, wherein the AlGaN layer has a thickness of 15~25nm and the molar fraction of Al is 25~35%.

[0063] Step 3: Grow an n-type heavily doped GaN transport layer and an n-type lightly doped GaN drift layer on the heterojunction layer 2.

[0064] Step 4: Etch a mesa on the epitaxial layer structure to form a side cathode contact;

[0065] Step 5: Etch the GaN drift layer to form a mesa for the top cathode contact;

[0066] Step 6: Fabricate cathode 5 on the top surface, side surface, and side surface of the GaN transport layer and heterojunction layer;

[0067] Step 7: Etch the GaN drift layer and transport layer to form the anode groove region;

[0068] Step 8: Using PECVD process, deposit SiN dielectric layer 6 in the etched area, the thickness of SiN dielectric layer 6 is 50nm~100nm;

[0069] Step 9: Further etch the anode groove area to remove the dielectric layer and AlGaN barrier layer 3 in the deep groove area, exposing the anode area;

[0070] Step 10: Deposit an anode metal layer in the exposed anode area to form the anode.

[0071] Example 2: Taking different AlGaN barrier layer thicknesses and different Al compositions as examples, the specific process flow of the preparation method in Example 1 is described in detail.

[0072] 1. An epitaxial structure with a dual-channel layer, a three-channel layer with an AlGaN barrier layer thickness of 15 nm, wherein the Al component is 35%, the GaN transport layer thickness is 1 μm, and the GaN drift layer thickness is 1 μm. The specific preparation steps are as follows:

[0073] Step 1. Epitaxial material growth

[0074] 1.1) On a Si substrate, a GaN channel layer is grown using MOCVD technology;

[0075] 1.2) A 15 nm thick AlGaN barrier layer is grown on the GaN channel layer, wherein the Al content is 35%, and a two-dimensional electron gas 2DEG is formed at the contact position between the GaN channel layer and the AlGaN barrier layer.

[0076] 1.3) A second 25nm thick GaN channel layer is grown on the first AlGaN barrier layer;

[0077] 1.4) A second 15nm thick AlGaN barrier layer is grown on the second GaN buffer layer, wherein the Al content is 35%, forming a channel layer with a heterojunction material structure with dual channels.

[0078] 1.5) A 1 μm thick n-type heavily doped GaN transport layer is grown on the second AlGaN barrier layer;

[0079] 1.6) A 1 μm thick n-type lightly doped GaN drift layer is grown on the GaN transport layer to form the entire epitaxial material structure.

[0080] Step 2. Fabrication of the mesa for side cathode contact

[0081] 2.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0082] 2.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, transport layer and double heterojunction layer for forming side cathode contacts.

[0083] Step 3. Fabrication of the mesa for the top cathode contact

[0084] 3.1) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0085] 3.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, which is used to form the top cathode contact.

[0086] Step 4. Cathode Fabrication

[0087] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist at a speed of 5000 rpm.

[0088] Next, it was baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a cathode region mask pattern.

[0089] Then, the cathode electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The metals selected were Ti / Al / Ni / Au in sequence, with a thickness of 20 nm for Ti, 120 nm for Al, 45 nm for Ni, and 55 nm for Au. After the cathode metal evaporation was completed, the metal was stripped to obtain the complete source and drain electrodes.

[0090] Finally, the cathode metal is alloyed by using an RTP500 rapid thermal annealing furnace in an N2 atmosphere at 870℃ for 30 seconds to complete the cathode fabrication.

[0091] Step 5. Fabrication of the anode groove

[0092] 5.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the anode groove.

[0093] 5.2) The masked substrate is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the double heterojunction layer;

[0094] 5.3) SiN was deposited in the anode groove region using a PECVD790 deposition equipment, and the thickness of the deposited SiN dielectric layer was 100 nm.

[0095] 5.4) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form a mask pattern with anode deep grooves.

[0096] 5.5) The substrate with the mask prepared is first etched in F plasma to remove the SiN dielectric layer, and then etched in Cl2 plasma to remove all AlGaN barrier layers in the anode groove region.

[0097] Step 6. Fabrication of the anode electrode

[0098] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0099] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a mask pattern for the anode region.

[0100] Finally, the anode metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The anode metal was selected as Ni / Au, with a Ni thickness of 20 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete anode electrode.

[0101] 2. A three-channel AlGaN barrier layer with a thickness of 20 nm, wherein the Al component is 30%, the GaN transport layer has a thickness of 2 μm, and the GaN drift layer has a thickness of 4 μm. The specific preparation steps are as follows:

[0102] Step 1. Epitaxial material growth

[0103] 1.1) On a sapphire substrate, a GaN channel layer is grown using MOCVD technology;

[0104] 1.2) A 20 nm thick AlGaN barrier layer is grown on the GaN channel layer, wherein the Al content is 30%, and a two-dimensional electron gas 2DEG is formed at the contact position between the GaN channel layer and the AlGaN barrier layer.

[0105] 1.3) A second 50 nm thick GaN channel layer is grown on the first AlGaN barrier layer;

[0106] 1.4) A second 20 nm thick AlGaN barrier layer is grown on the second GaN buffer layer, wherein the Al content is 30%, forming a channel layer with a heterojunction material structure with dual channels.

[0107] 1.5) A 2 μm thick n-type heavily doped GaN transport layer is grown on the second AlGaN barrier layer;

[0108] 1.6) A 4 μm thick n-type lightly doped GaN drift layer is grown on the GaN transport layer to form the entire epitaxial material structure.

[0109] Step 2. Fabrication of the mesa for side cathode contact

[0110] 2.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0111] 2.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, transport layer and double heterojunction layer for forming side cathode contacts.

[0112] Step 3. Fabrication of the mesa for the top cathode contact

[0113] 3.1) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0114] 3.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, which is used to form the top cathode contact.

[0115] Step 4. Cathode Fabrication

[0116] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist at a speed of 5000 rpm.

[0117] Next, it was baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a cathode region mask pattern.

[0118] Then, the cathode electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The metals selected were Ti / Al / Ni / Au in sequence, with a thickness of 20 nm for Ti, 120 nm for Al, 45 nm for Ni, and 55 nm for Au. After the cathode metal evaporation was completed, the metal was stripped to obtain the complete source and drain electrodes.

[0119] Finally, the cathode metal is alloyed by using an RTP500 rapid thermal annealing furnace in an N2 atmosphere at 870℃ for 30 seconds to complete the cathode fabrication.

[0120] Step 5. Fabrication of the anode groove

[0121] 5.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the anode groove.

[0122] 5.2) The masked substrate is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the double heterojunction layer;

[0123] 5.3) SiO2 was deposited on the anode groove region using a PECVD790 deposition equipment, and the thickness of the deposited SiO2 dielectric layer was 50 nm.

[0124] 5.4) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form a mask pattern with anode deep grooves.

[0125] 5.5) The substrate with the mask prepared is first etched in F plasma to remove the SiO2 dielectric layer, and then etched in Cl2 plasma to remove all AlGaN barrier layers in the anode groove region.

[0126] Step 6. Fabrication of the anode electrode

[0127] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0128] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a mask pattern for the anode region.

[0129] Finally, the anode metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The anode metal was selected as Ni / Au, with a Ni thickness of 20 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete anode electrode.

[0130] 3. A dual-channel layer with an AlGaN barrier layer thickness of 25 nm, wherein the Al component is 25%, the GaN transport layer thickness is 3 μm, and the GaN drift layer thickness is 9 μm. The specific preparation steps are as follows:

[0131] Step 1. Epitaxial material growth

[0132] 1.1) On a sapphire substrate, a GaN channel layer is grown using MOCVD technology;

[0133] 1.2) A 25 nm thick AlGaN barrier layer is grown on the GaN channel layer, wherein the Al content is 25%, and a two-dimensional electron gas 2DEG is formed at the contact position between the GaN channel layer and the AlGaN barrier layer.

[0134] 1.3) A second 75nm thick GaN channel layer is grown on the first AlGaN barrier layer;

[0135] 1.4) A second 25nm thick AlGaN barrier layer is grown on the second GaN buffer layer, wherein the Al content is 25%, forming a channel layer with a heterojunction material structure with dual channels.

[0136] 1.5) A 3 μm thick n-type heavily doped GaN transport layer is grown on the second AlGaN barrier layer;

[0137] 1.6) A 9 μm thick n-type lightly doped GaN drift layer is grown on the GaN transport layer to form the entire epitaxial material structure.

[0138] Step 2. Fabrication of the mesa for side cathode contact

[0139] 2.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0140] 2.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, transport layer and double heterojunction layer for forming side cathode contacts.

[0141] Step 3. Fabrication of the mesa for the top cathode contact

[0142] 3.1) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form the mask pattern of the mesa.

[0143] 3.2) The substrate with the mask prepared is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the drift layer, which is used to form the top cathode contact.

[0144] Step 4. Cathode Fabrication

[0145] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist at a speed of 5000 rpm.

[0146] Next, it was baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a cathode region mask pattern.

[0147] Then, the cathode electrode was fabricated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The metals selected were Ti / Al / Ni / Au in sequence, with a thickness of 20 nm for Ti, 120 nm for Al, 45 nm for Ni, and 55 nm for Au. After the cathode metal evaporation was completed, the metal was stripped to obtain the complete source and drain electrodes.

[0148] Finally, the cathode metal is alloyed by using an RTP500 rapid thermal annealing furnace in an N2 atmosphere at 870℃ for 30 seconds to complete the cathode fabrication.

[0149] Step 5. Fabrication of the anode groove

[0150] 5.1) First, a spin coater is used to spin the photoresist at a speed of 3500 rpm to obtain a photoresist mask; then, an E-beam lithography machine is used for exposure to form the mask pattern of the anode groove.

[0151] 5.2) The masked substrate is etched in Cl2 plasma using an ICP98c inductively coupled plasma etching machine to expose the double heterojunction layer;

[0152] 5.3) Al2O3 was deposited on the anode groove region using a PECVD790 deposition equipment, and the thickness of the deposited SiN dielectric layer was 50 nm;

[0153] 5.4) A photoresist mask is obtained by spinning the photoresist at a speed of 3500 rpm using a spin coater; then an E-beam lithography machine is used for exposure to form a mask pattern with anode deep grooves.

[0154] 5.5) The substrate with the mask prepared is first etched in F plasma to remove the Al2O3 dielectric layer, and then etched in Cl2 plasma to remove all AlGaN barrier layers in the anode groove region.

[0155] Step 6. Fabrication of the anode electrode

[0156] First, a photoresist mask with a thickness of 0.8 μm was obtained by spinning the photoresist mask at a speed of 5000 rpm.

[0157] Next, it is baked in a high-temperature oven at 80°C for 10 minutes, and then exposed using an NSR1755I7A lithography machine to form a mask pattern for the anode region.

[0158] Finally, the anode metal was evaporated using an Ohmiker-50 electron beam evaporation stage at an evaporation rate of 0.1 nm / s. The anode metal was selected as Ni / Au, with a Ni thickness of 20 nm and an Au thickness of 200 nm. After evaporation, the metal was stripped to obtain a complete anode electrode.

[0159] In the composite GaN-based Schottky barrier diode prepared by this invention, the top of the anode is in contact with the GaN drift layer through the groove design, and the sides and bottom of the anode are in contact with multiple heterojunction structures. Through the mesa design, the cathode is in contact with the GaN transport layer and multiple heterojunction structures from the sides and top. Overall, multiple parallel conductive paths are formed between the anode and cathode of the device, resulting in lower on-resistance and stronger current driving capability of the device.

[0160] The composite GaN-based Schottky barrier diode prepared by this invention can effectively alleviate the current pooling effect in the quasi-vertical structure by introducing a multi-channel lateral structure in parallel with a quasi-vertical structure, making the current distribution more uniform when the device is working, which is beneficial to improving the reliability of the device. The design of this invention is reasonable and worthy of widespread promotion.

[0161] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A compound GaN-based Schottky barrier diode, characterized by: The composite GaN-based Schottky barrier diode includes a substrate layer (1), several heterojunction layers (2), a transport layer (3), a drift layer (4), a dielectric layer (5), an anode (6), and a cathode (7). The plurality of heterojunction layers (2) are sequentially stacked on the substrate layer (1); The transport layer (3) is disposed on the heterojunction layer (2); The drift layer (4) is disposed on the transmission layer (3); The dielectric layer (5) is disposed on the inner surface of the transmission layer (3) and the drift layer (4); The anode (6) contacts the top surface of the drift layer (4), the side surface of the dielectric layer (5), and the inner surface of the heterojunction layer (2); The cathode (7) contacts the top surface, outer surface, and outer surface of the transport layer (3) and the heterojunction layer (2); The heterojunction layer (2) includes a GaN channel layer (8) and an AlGaN barrier layer (9) arranged from bottom to top; the GaN channel layer (8) and the AlGaN barrier layer (9) form an AlGaN / GaN heterojunction; The transport layer (3) is an n-type heavily doped GaN transport layer; The drift layer (4) is an n-type lightly doped GaN drift layer.

2. The compound GaN-based Schottky barrier diode according to claim 1, wherein: The substrate layer (1) is made of sapphire or Si.

3. The composite GaN-based Schottky barrier diode according to claim 1, characterized in that: The AlGaN barrier layer (9) has a thickness of 15~25nm, the molar fraction of Al is 25~35%, and the GaN channel layer (8) has a thickness of 25-75nm.

4. The composite GaN-based Schottky barrier diode according to claim 1, characterized in that: The thickness of the n-type heavily doped GaN transport layer is 1-3 μm; The thickness of the n-type lightly doped GaN drift layer is 1-9 μm.

5. A composite GaN-based Schottky barrier diode according to claim 1, characterized in that: The thickness of the dielectric layer (5) is 50nm-100nm.

6. A method for fabricating a composite GaN-based Schottky barrier diode, comprising the composite GaN-based Schottky barrier diode as described in any one of claims 1-5, characterized in that: The fabrication method of the composite GaN-based Schottky barrier diode is as follows: Step 1: Select sapphire or Si as the substrate layer (1); Step 2: On the substrate layer (1), a GaN buffer layer and several heterojunction layers (2) are grown sequentially. Step 3: Grow an n-type heavily doped GaN transport layer and an n-type lightly doped GaN drift layer on several heterojunction layers (2); Step 4: Set a mesa on the epitaxial layer structure for contact with the side cathode (7); Step 5: Set a mesa on the epitaxial layer structure for contact with the top cathode (7); Step 6: Fabricate cathodes on the sides of several heterojunction layers (2) and the top surface of the transport layer (3); Step 7: ICP etching is used to etch the drift layer (4) and transport layer (3) in the anode groove region; Step 8: Using PECVD process, deposit a dielectric layer on the etched area (5). Step 9: Use ICP etching technology to etch the dielectric layer (5) and several heterojunction layers (2) in the anode groove region to ensure that the AlGaN barrier layer (9) in the anode groove region is completely removed; Step 10: Fabricate the anode in the anode groove area (6).

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