Specific harmonic cancellation modulation method to eliminate the superposition time effect of current source inverters

Abstract

This invention discloses a specific harmonic elimination modulation method for eliminating the superimposed current time effect in a current source inverter. The method modulates a current source inverter using an H7 topology and includes: setting the required harmonic order to be eliminated and determining the number of switching angles in the specific harmonic elimination modulation; constructing drive pulse models for power switches S1 to S7 based on the constraints of the specific harmonic elimination modulation and the drive pulse characteristics of power switch S7; solving for the switching angle sizes under different modulation ratios; realizing specific harmonic elimination modulation based on the drive pulse models and switching angle sizes of each power switch; and introducing superimposed current time based on set rules to ensure that the circuit of the current source inverter is always in a closed state. This invention achieves zero-current switching for power switches S1 to S6 in the subsequent H6 converter bridge by changing the pulse sequence of the power switches, eliminating the impact of superimposed current time on power quality and reducing the switching losses of power switches S1 to S6.

Description

Technical Field

[0001] This invention belongs to the field of current source inverter technology, and particularly relates to a specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] An inverter is a converter that transforms direct current (DC) energy (including batteries, accumulators, etc.) into constant-frequency, constant-voltage or frequency- and voltage-modulated alternating current (AC) (typically a 220V / 50Hz sine wave). It consists of an inverter bridge, control logic, and filter circuits, and is generally classified into current-source inverters and voltage-source inverters. As an interface device connecting renewable energy sources to the power grid, the inverter is an indispensable part of renewable energy power generation. Three-phase current-source inverters, due to their higher reliability and voltage boosting capabilities, can be applied to renewable energy power generation systems such as photovoltaic, wind, and ocean energy, and have good industrial value and application prospects.

[0004] High-power current source inverters (CSIs) typically operate at lower switching frequencies to reduce switching losses. However, this also leads to a significant increase in harmonics in the output power, particularly low-order harmonics, thus affecting the quality of the output power. Furthermore, to ensure proper operation, current source inverters require a slack current period between the drive signals of the switching transistors during modulation to maintain a closed circuit. However, this slack current period increases the harmonic distortion rate of the AC output current, further degrading power quality.

[0005] Currently, Selected Harmonic Elimination Pulse Width Modulation (SHEPWM) is one of the commonly used modulation methods in CSI. This technique, by selecting the switching timing, can achieve harmonic elimination at lower switching frequencies, effectively mitigating harmonic problems. For example, the journal article "Generalized techniques of selective harmonic elimination and current control in currentsource inverters / converters" proposes a general technique for selective harmonic elimination based on the H6 current source inverter, realizing the application of selective harmonic elimination technology in current source inverters. However, the above scheme does not consider the superposition time effect. That is, there is currently no method in the existing technology that uses selective harmonic elimination technology to solve the superposition time problem. Summary of the Invention

[0006] To address the shortcomings of the prior art, this invention provides a specific harmonic cancellation modulation method for eliminating the superposition time effect of current source inverters. Using an H7 current source inverter as the converter topology, and by changing the pulse sequence of the power switches, power switches S1 to S6 in the subsequent H6 converter bridge achieve zero-current switching. This not only eliminates the impact of superposition time on power quality but also reduces the switching losses of power switches S1 to S6, avoiding the problem of increased harmonics in the output power affecting power quality.

[0007] In one aspect, this disclosure provides a specific harmonic cancellation modulation method for eliminating the superposition time effect of current source inverters.

[0008] A specific harmonic cancellation modulation method for eliminating the superposition time effect in a current source inverter, modulating a current source inverter with an H7 topology, comprising:

[0009] Set the number of harmonics to be eliminated and determine the number of switching angles in the specific harmonic elimination modulation;

[0010] Based on the constraints of specific harmonic cancellation modulation of the current source inverter, drive pulse models for power switches S1 to S6 are constructed.

[0011] Based on the driving pulse characteristics of power switch S7 in the current source inverter, a driving pulse model of power switch S7 is constructed.

[0012] Based on the constructed driving pulse model of each power switch, and combined with the required harmonic order to be eliminated and the number of switching angles, the switching angle size under different modulation ratios is solved.

[0013] Based on the driving pulse model of power switches S1 to S7 and the solved switching angle, specific harmonic cancellation modulation is achieved.

[0014] The turn-off or turn-on time of power switches S1 to S6 is set at the moment when power switch S7 is turned on or off. Based on the set rules, the superposition time is introduced to ensure that the circuit of the current source inverter is always in a closed state.

[0015] A further technical solution, employing the H7 current source inverter topology, is as follows:

[0016] The topology is divided into two stages: a front stage and a rear stage. The front stage circuit consists of a DC voltage source U. dc An inductor L dc It consists of a power switch S7 connected in parallel with the bus; the subsequent circuit adopts an H6 converter bridge structure composed of power switches S1 to S6; the three phases of the AC output are respectively connected to capacitors for filtering.

[0017] The above one or more technical solutions have the following beneficial effects:

[0018] 1. This invention provides a specific harmonic cancellation modulation method to eliminate the superposition time effect of current source inverters. It uses an H7 current source inverter as the converter topology and changes the pulse sequence of the power switches. The power switches S1 to S6 in the subsequent H6 converter bridge achieve zero-current switching, which not only eliminates the impact of superposition time on power quality, but also reduces the switching losses of power switches S1 to S6, and avoids the problem of increased harmonics in the output power affecting power quality.

[0019] 2. The modulation method proposed in this invention provides a pulse sequence model for each power switch in the inverter and sets specific rules for the turn-on / turn-off times of each power switch, thereby achieving specific harmonic elimination modulation to eliminate the superposition time effect of the current source inverter. Attached Figure Description

[0020] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0021] Figure 1 This is a topology diagram of the H6 current source inverter in the existing technology;

[0022] Figure 2 This is a topology diagram of the H7 current source inverter used in the embodiments of the present invention;

[0023] Figure 3 This is a device selection diagram for low-speed power switching transistors S1 to S6;

[0024] Figure 4 Device selection diagram for high-performance power switch S7;

[0025] Figure 5 This is a flowchart of the specific harmonic elimination modulation method for eliminating the superimposed current time effect in a current source inverter according to an embodiment of the present invention;

[0026] Figure 6 These represent two different types of switching states of power switching transistors S1 to S6 at π / 6 in embodiments of the present invention.

[0027] Figure 7 This is a pulse sequence model of power switches S1 to S7 and output current under the first type in this embodiment of the invention;

[0028] Figure 8 This is a pulse sequence model of power switches S1 to S7 and output current under the second type in this embodiment of the invention;

[0029] Figure 9 This is a schematic diagram illustrating the setting of the turn-on / turn-off times of power switching transistors S1 to S6 in an embodiment of the present invention.

[0030] Figure 10 This is a pulse sequence model with N=2 in an embodiment of the present invention;

[0031] Figure 11 The results of solving the switching angle under different modulation ratios when N=2 are shown in the embodiments of the present invention;

[0032] Figure 12 This is a pulse sequence model with N=4 in an embodiment of the present invention;

[0033] Figure 13 The results of solving the switching angle under different modulation ratios when N=4 are shown in the embodiments of the present invention;

[0034] Figure 14 This is a pulse sequence model with N=6 in an embodiment of the present invention;

[0035] Figure 15 The results show the solution for the switching angle under different modulation ratios when N=6 in this embodiment of the invention. Detailed Implementation

[0036] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0038] Example 1

[0039] To eliminate the impact of superimposed current time effect on power quality, further reduce the power switching losses of current source inverters, and avoid the problem of increased output power harmonics affecting power quality, this embodiment proposes a specific harmonic elimination modulation method to eliminate the superimposed current time effect in current source inverters. This method eliminates the superimposed current time problem by changing the inverter topology and modulation strategy.

[0040] Traditional current source inverter topologies, such as Figure 1 As shown, the converter bridge of this structure consists of power switches S1 to S6, and the DC-side circuit consists of a DC voltage source U. dc and an inductor L dc The inverters are connected in series, and the AC output is filtered by three-phase capacitors. Based on the traditional current source inverter topology, an H7 current source inverter topology is proposed. This embodiment uses the H7 current source inverter as the converter topology and employs the proposed method to perform specific harmonic elimination and superimposed current time effect elimination modulation on the H7 current source inverter. Figure 2 As shown, the topology of the H7 current source inverter is divided into two stages: front and back. The front stage circuit consists of a DC voltage source U. dc An inductor L dc It consists of a power switch S7 connected in parallel with the bus; the subsequent circuit adopts a traditional H6 converter bridge structure composed of power switches S1 to S6, and the AC output is filtered by three-phase capacitors.

[0041] In this embodiment, the H7 current source inverter topology is as follows:

[0042] (1) Power switching transistors S1 to S6 retain the configuration scheme of traditional high-power current source inverters, using low-speed power switching transistors, such as... Figure 3As shown in (a), (b), and (c), gate turn-off thyristors (GTO), integrated gate-commutated thyristors (IGCT), and insulated gate bipolar transistors (IGBT) can be selected.

[0043] (2) The power switch S7 is selected as a fully controllable device with high-speed commutation capability, such as... Figure 4 As shown in (a) and (b), the following can be selected: reverse blocking high-speed insulated gate bipolar transistor (IGBT) and reverse blocking metal-oxide-semiconductor field-effect transistor (MOSFET) based on silicon carbide (SiC).

[0044] Based on the aforementioned H7 current source inverter topology, this embodiment discloses a specific harmonic cancellation modulation method for eliminating the superposition time effect of current source inverters. The method modulates a current source inverter employing the H7 current source inverter topology, such as... Figure 5 As shown, the modulation method includes the following steps:

[0045] Step S1: Set the number of harmonics to be eliminated and determine the number of switching angles in the specific harmonic elimination modulation;

[0046] Step S2: Based on the constraints of specific harmonic cancellation modulation of the current source inverter, construct the drive pulse model of power switch transistors S1 to S6.

[0047] Step S3: Based on the driving pulse characteristics of the power switch S7 in the current source inverter, construct the driving pulse model of the power switch S7.

[0048] Step S4: Based on the constructed drive pulse model of each power switch, and combined with the required harmonic order to be eliminated and the number of switching angles, solve for the switching angle size under different modulation ratios.

[0049] Step S5: Based on the driving pulse model of power switching transistors S1 to S7 and the solved switching angle, specific harmonic cancellation modulation is achieved.

[0050] Step S6: Set the turn-off or turn-on time of power switching transistors S1 to S6 when power switching transistor S7 is turned on or off. Introduce superposition time based on the set rules to ensure that the circuit of the current source inverter is always in a closed state.

[0051] Specifically, in step S1 above, the number of harmonics to be eliminated is set, and the number of switching angles in the specific harmonic elimination modulation of the current source inverter is determined.

[0052] In steps S2 and S3 above, the driving pulse models of power switches S1 to S6 are constructed based on the constraints of specific harmonic cancellation modulation of the current source inverter; and the driving pulse model of power switch S7 is constructed based on the driving pulse characteristics of power switch S7 in the current source inverter.

[0053] Specifically, taking (0, 2π) as a period, we will first explain the constraints of a traditional current source inverter when performing a specific harmonic cancellation modulation technique and the characteristics of the power switch S7 drive pulse used in this embodiment.

[0054] The constraints for traditional current source inverters to perform specific harmonic cancellation modulation techniques are as follows:

[0055] (1) Output current of the current source inverter (i a i b i c The following conditions must be met: the output current must satisfy half-wave symmetry, i.e., symmetry about the center point (π, 0); the output current must satisfy quarter-wave symmetry, i.e., symmetry about the axis x = π / 2; the output three-phase current i a i b i c The phases of the numbers differ by 2π / 3 in succession.

[0056] (2) Let the initial free angle be α, that is, the switching angle be α, and the number of switching angles be N. The switching angle α must satisfy the following condition:

[0057] 0 < α1 < α2 < ... < α N <π / 6.

[0058] (3) The driving pulses of power switching transistors S1 to S6 must meet the following condition: the driving pulses of power switching transistors S1 to S6 are sequentially π / 3 apart.

[0059] The characteristics of the drive pulse for the power switch S7 in the H7 current source inverter used in this embodiment are as follows:

[0060] (1) The driving pulse of power switch S7 is in the range of (0, π / 3), and the pulse sequence of power switch S7 is symmetrical about the π / 6 axis.

[0061] (2) The driving pulse of the power switch S7 has the same waveform in the intervals of (0, π / 3), (π / 3, 2π / 3) and (2π / 3, π).

[0062] Based on the above constraints and the characteristics of the driving pulses, a driving pulse model for power switches S1 to S7 is constructed, i.e., the driving pulse sequence of power switches S1 to S7 is obtained. Furthermore, the modulation of the current source inverter also requires determining the magnitude of each switching angle; therefore, the following steps are used to solve this problem.

[0063] Execute step S4, based on the constructed drive pulse model of each power switch, combined with the required harmonic order to be eliminated and the number of switching angles, to solve the switching angle size (i.e., switching angle) under different modulation ratios.

[0064] The number of switching angles in specific harmonic elimination techniques can be either odd or even. To meet the solution conditions, the number of switching angles in this embodiment should be even. Based on the different switching states of power switches S1 to S6 at π / 6, the pulse sequence models of the power switches are divided into two types, as detailed below. Figure 6 As shown.

[0065] The first type is the case where the number of switching angles is N = 4k + 2 (k = 0, 1, 2, ...). Figure 6 In Figure (a), the switching state of the first type at π / 6 is shown. The figure takes phase a as an example and shows the switching states of power switches S1, S3, S5, and S7 at π / 6.

[0066] Taking phase a as an example, the first type of pulse sequence model is as follows: Figure 7 As shown. Figure 7 The method for constructing the pulse sequence of switches S1 to S7 is demonstrated, and the modulation waveform of the output current (before filtering) is also given. Here, α is the set switching angle, which refers to the free angle in the entire pulse model (S1 to S7), and i a This is the output current of phase a.

[0067] Specifically, firstly, based on the constructed driving pulse model of the power switch, the output current waveform of the current source inverter is obtained, the output current expression of the current source inverter is written, and the output current expression is Fourier decomposed to obtain the nth harmonic expression of the output current. Formulas (1) and (2) are the Fourier decomposition expressions of the output current i(ωt); Formula (3) is the nth harmonic expression of the first type of output current I. a,n .

[0068]

[0069]

[0070]

[0071] Then, based on the nth harmonic expression of the output current, the switching angle (i.e., the switching angle) under different modulation ratios is calculated. Wherein, the modulation ratio m is related to the DC-side current I. dc The amplitude I of the fundamental current on the AC side a,1 This is related to the expression in formula (4). By controlling the modulation ratio, and simultaneously setting the expression for the nth harmonic of the harmonic to be eliminated as I... a,n =0, construct a system of nonlinear equations, and then solve for the switching angle under different modulation ratios.

[0072]

[0073] The second type is the case where the number of switching angles is N = 4k (k = 1, 2, 3, ...). Figure 6 In the middle (b), the second type of switch state is at π / 6.

[0074] Taking phase a as an example, the second type of pulse sequence model is as follows: Figure 8 As shown. Figure 8 The method for constructing the pulse sequence of switches S1 to S7 is shown, and the modulation waveform of the output current (before filtering) is also given.

[0075] Similarly, in step S4, the output current waveform of the current source inverter is first obtained based on the constructed power switch driving pulse model. The output current expression of the current source inverter is calculated, and the output current expression is Fourier decomposed to obtain the nth harmonic expression of the output current.

[0076] Formula (5) is the nth harmonic expression for the output current of the second type. a,n .

[0077]

[0078] Using the same method, by controlling the modulation ratio and simultaneously setting the expression I of the nth harmonic to be eliminated... a,n =0, construct a system of nonlinear equations, and then solve for the switching angles of each switch S1 to S7 under different modulation ratios.

[0079] At this point, step S5 is executed, which uses the driving pulse model of power switching transistors S1 to S7 and the solved switching angle to achieve specific harmonic cancellation modulation.

[0080] Furthermore, to ensure the circuit remains closed, a period of superposition current is typically introduced between the drive signals of the switching transistors. Therefore, the turn-on / turn-off times of power switches S1 to S6 need to be adjusted. In this embodiment, a current source inverter with an H7 topology is selected. When S7 is closed and conducting, the power switches S1 to S6 in the subsequent circuit are short-circuited. At this time, the turn-on / turn-off of S1 to S6 actually performs zero-current switching. During this time period, the turn-on / turn-off of S1 to S6 does not affect the waveform of the output current. Therefore, the turn-off or turn-on time of power switches S1 to S6 is set accordingly when power switch S7 is turned on or off.

[0081] That is, step S6 is then executed, whereby a current overlap time is set or introduced according to the following rules. The introduction of this current overlap time does not affect the output current, thus eliminating the effect of the current overlap time. Specifically, the rules for setting the turn-on / turn-off times of power switches S1 to S6 are as follows:

[0082] Delay the turn-off of the power switch that is turned off at the S7 turn-on time (e.g.) Figure 9 S in x (x = 1, 2, 3, 4, 5, 6), the delay time is denoted as t. d (like Figure 9 As shown, t d In the interval (0, t) s The value is taken from t. s (where S7 is the on-time), the rules are as follows: the off-time of this power switch should lag behind the on-time of S7; the off-time of this power switch should precede the off-time of S7; the delay time should not exceed the on-time t of S7. s .

[0083] To enable the power switch transistor that is turned on at the S7 turn-off time to turn on in advance (e.g.) Figure 9 S in y (y = 1, 2, 3, 4, 5, 6), the advance time is denoted as t. e (like Figure 9 As shown, t e In the interval (0, t) s The values ​​are taken from within the range, and the rules are as follows: the turn-on time of the power switch should lag behind the turn-on time of S7; the turn-on time of the power switch should precede the turn-off time of S7; the advance time should not exceed the turn-on time t of S7. s .

[0084] The losses generated by power switches S1 to S7 are mainly classified into on-state losses, off-state losses, and switching losses. The modulation method proposed in this embodiment introduces zero vectors before and after the power switches S1 to S6 are turned on / off. Therefore, the commutation of S1 to S6 is all zero-current switching, and the switching losses are all borne by the high-performance power switch S7. The conduction of power switch S7 can eliminate the influence of superposition time on the output power, and further reduce the switching losses of power switches S1 to S6.

[0085] Furthermore, in order to explain the modulation method described above in this embodiment in more detail, the following describes setting two switching angles (eliminating 5°). th Taking the case of harmonics as an example, the modulation method described in this embodiment will be explained.

[0086] Set two switching angles, α1 and α2 (to eliminate 5). th (Harmonics). Construct driving pulse models for each power switch S1 to S7, and the pulse sequence model for N=2 is as follows. Figure 10 As shown, it belongs to the first type. Formula (6) is the nth harmonic expression for the output current of N=2. Figure 11 The results of solving the switching angle for N=2 at different modulation ratios are as follows: Figure 11 As shown, when N=2, the modulation ratio m is at its maximum of 0.87. When m is greater than 0.87, the solved switching angle does not meet the constraint conditions, that is, when m is greater than 0.87, there is no solution for the switching angle.

[0087]

[0088] By controlling the modulation ratio to be less than 0.87, and simultaneously setting the expression I of the nth harmonic of the harmonic to be eliminated... a,n =0, construct a nonlinear equation system to solve for the switching angle when the modulation ratio is less than 0.87. Based on the driving pulse model of power switches S1 to S7 and the solved switching angle, specific harmonic cancellation modulation is achieved. Then, the turn-off or turn-on time of power switches S1 to S6 in the on or off state of power switch S7 is set. Based on this set rule, a superposition current time is introduced to ensure that the circuit of the current source inverter is always in a closed state, and the introduction of this superposition current time does not affect the final output current, thus eliminating the effect of the superposition current time.

[0089] Example 2

[0090] In Example 2, four switching angles are set (to eliminate 5). th 7 th 11 th Taking the case of harmonics as an example, this embodiment will explain the specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters.

[0091] Four switching angles are set, namely α1, α2, α3, and α4 (to eliminate 5). th 7 th 11 th Harmonics). The pulse sequence model for N=4 is as follows: Figure 12 As shown, this belongs to the second type. Formula (7) is the nth harmonic expression for the output current when N=4. Figure 13 The results show the switching angles for N=4 at different modulation ratios. For example... Figure 13 As shown, when N=4, the modulation ratio m is at its maximum of 0.88. When m is greater than 0.88, the solved switching angle does not meet the constraint conditions, that is, when m is greater than 0.88, there is no solution for the switching angle.

[0092]

[0093] By controlling the modulation ratio to be less than 0.88, and simultaneously setting the expression I of the nth harmonic of the harmonic to be eliminated... a,n =0, construct a nonlinear equation system to solve for the switching angle when the modulation ratio is less than 0.88. Based on the driving pulse model of power switches S1 to S7 and the solved switching angle, specific harmonic cancellation modulation is achieved. Then, the turn-off or turn-on time of power switches S1 to S6 in the on or off state of power switch S7 is set. Based on the set rule, a superposition current time is introduced to ensure that the circuit of the current source inverter is always in a closed state, and the introduction of this superposition current time does not affect the final output current, thus eliminating the effect of superposition current time.

[0094] Example 3

[0095] In Example 3, six switching angles are set (to eliminate 5). th 7 th 11 th 13 th 17 th Taking the case of harmonics as an example, this embodiment will explain the specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters.

[0096] Six switching angles are set: α1, α2, α3, α4, α5, and α6 (to eliminate 5). th 7 th 11 th 13 th 17 th Harmonics). The pulse sequence model for N=6 is as follows: Figure 14 As shown, it belongs to the first type. Formula (8) is the nth harmonic expression for the output current when N=6. Figure 15 The results show the switching angles for N=6 at different modulation ratios. For example... Figure 15As shown, when N=6, the modulation ratio m is at its maximum of 0.86. When m is greater than 0.86, the solved switching angle does not meet the constraint conditions, that is, when m is greater than 0.86, there is no solution for the switching angle.

[0097]

[0098] By controlling the modulation ratio to be less than 0.86, and simultaneously setting the expression I of the nth harmonic of the harmonic to be eliminated... a,n =0, construct a nonlinear equation system to solve for the switching angle when the modulation ratio is less than 0.86. Based on the driving pulse model of power switches S1 to S7 and the solved switching angle, specific harmonic cancellation modulation is achieved. Then, the turn-off or turn-on time of power switches S1 to S6 in the on or off state of power switch S7 is set. Based on this set rule, a superposition current time is introduced to ensure that the circuit of the current source inverter is always in a closed state, and the introduction of this superposition current time does not affect the final output current, thus eliminating the effect of the superposition current time.

[0099] Those skilled in the art will understand that the steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.

[0100] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0101] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A specific harmonic cancellation modulation method for eliminating the superposition time effect of current source inverters, characterized in that, The current source inverter employing the H7 topology includes: Set the number of harmonics to be eliminated and determine the number of switching angles in the specific harmonic elimination modulation; Based on the constraints of specific harmonic cancellation modulation of the current source inverter, drive pulse models for power switches S1~S6 are constructed. Based on the driving pulse characteristics of power switch S7 in the current source inverter, a driving pulse model of power switch S7 is constructed. The driving pulse characteristics of power switch S7 in the current source inverter include: the driving pulse of power switch S7 is within the range of (0, π / 3), and the pulse sequence of power switch S7 is symmetrical about the π / 6 axis; the driving pulse of power switch S7 has the same waveform in the ranges of (0, π / 3), (π / 3, 2π / 3), and (2π / 3, π). Based on the constructed driving pulse model of each power switch, and combined with the required harmonic order to be eliminated and the number of switching angles, the switching angle size under different modulation ratios is solved. Based on the driving pulse model of power switches S1~S7 and the solved switching angle, specific harmonic cancellation modulation is achieved. The turn-off or turn-on time of power switches S1~S6 is set at the turn-on or turn-off time of power switch S7. Based on the set rules, the superposition time is introduced to ensure that the circuit of the current source inverter is always in a closed state. The rules for setting the turn-off time of power switches S1 to S6 are as follows: the power switches that are turned off when power switch S7 is turned on are delayed, including: the turn-off time of the power switch is delayed after the turn-on time of power switch S7; the turn-off time of the power switch is advanced before the turn-off time of power switch S7; and the delay time is not greater than the turn-on time of power switch S7. The rules for setting the turn-on time of power switches S1 to S6 are as follows: power switches that are turned on at the turn-off time of power switch S7 are turned on in advance, including: the turn-on time of the power switch is later than the turn-on time of power switch S7; the turn-on time of the power switch is earlier than the turn-off time of power switch S7; the advance time is not greater than the turn-on time of power switch S7.

2. The specific harmonic elimination modulation method for eliminating the superimposed current time effect in a current source inverter as described in claim 1, characterized in that, The step of determining the switching angle of each power switch under different modulation ratios based on the constructed driving pulse model of each power switch, combined with the required harmonic order to be eliminated and the number of switching angles, includes: Based on the constructed driving pulse model of the power switch, the output current waveform of the current source inverter is obtained, and the expression of the output current of the current source inverter is written. Performing Fourier decomposition on the output current expression yields the output current. n The expression for the second harmonic; Based on the output current n The subharmonic expression is used to solve for the switching angles of power switches S1 to S7 under different modulation ratios.

3. The specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters as described in claim 2, characterized in that, The output current n The expression for the second harmonic is used to solve for the switching angles of power switches S1~S7 under different modulation ratios, including: Controlling the modulation ratio allows the harmonics to be eliminated to... n The subharmonic expression is equal to 0. A set of nonlinear equations is constructed, and then the switching angles of each power switch S1~S7 under different modulation ratios are obtained by solving the equations.

4. The specific harmonic elimination modulation method for eliminating the superimposed current time effect in a current source inverter as described in claim 1, characterized in that, The modulation ratio is the ratio of the amplitude of the AC fundamental current to the DC current.

5. The specific harmonic elimination modulation method for eliminating the superimposed current time effect in a current source inverter as described in claim 1, characterized in that, The H7 current source inverter topology used is as follows: The topology is divided into two stages: a front stage and a rear stage. The front stage circuit consists of a DC voltage source U. dc An inductor L dc It consists of a power switch S7 connected in parallel with the bus; the subsequent circuit adopts an H6 converter bridge structure composed of power switches S1~S6; the three phases of the AC output are respectively connected to capacitors for filtering.

6. The specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters as described in claim 5, characterized in that, The power switching transistors S1 to S6 are low-speed power switching transistors, including gate turn-off thyristors, reverse blocking integrated gate thyristors, and reverse blocking insulated gate bipolar transistors.

7. The specific harmonic elimination modulation method for eliminating the superposition time effect of current source inverters as described in claim 5, characterized in that, The power switch S7 uses a fully controllable device with high-speed commutation capability, including a reverse-blocking high-speed insulated-gate bipolar transistor and a silicon carbide-based reverse-blocking metal-oxide-semiconductor field-effect transistor.

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