A hybrid-mode dual-phase buck converter for backlight LED driving

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a hybrid mode dual-phase buck converter for backlight LED driving. The low-voltage conversion ratio hybrid mode dual-phase buck converter combines the advantages of a traditional dual-phase Buck converter and a hybrid mode DC-DC converter, realizes self-balancing of dual-phase inductor currents by introducing a flying capacitor, and reduces voltage stress of a power switch tube to half of that of the traditional Buck converter, thereby improving overall energy conversion efficiency of the converter and realizing equal-current and equal-brightness driving of dual-phase LED loads. In addition, the introduction of the flying capacitor makes the converter have a low voltage conversion ratio, and is suitable for series LED backlight driving applications, and has significant advantages in light source uniformity, conversion efficiency and driving cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a hybrid-mode dual-phase buck converter for backlight LED driving. Background Technology

[0002] Light-emitting diodes (LEDs) offer advantages over traditional light sources, including high brightness, low power consumption, low heat generation, and long lifespan. They are widely used in lighting, communication, and display equipment, and their demand and market share are increasing year by year. Backlighting technology, as one of the main application scenarios for LEDs, plays a crucial role in display devices such as mobile phones, monitors, and televisions. Compared to traditional backlights such as cold cathode fluorescent lamps (CCFLs), LED backlighting technology has significant energy-saving advantages, but technical challenges remain in areas such as energy efficiency and light source uniformity. The ever-increasing market demand and performance requirements necessitate LED backlighting technologies with higher efficiency, higher current accuracy, and better light uniformity. For backlighting applications, constant current driving is typically required to ensure the consistency of brightness and color among individual LEDs. Switching DC-DC converters, due to their high energy conversion efficiency and output current accuracy, have become an important component of constant current LED drivers.

[0003] Hybrid-mode DC-DC converters combine the advantages of traditional switched-inductor and switched-capacitor converters. By adding flying capacitors, they reduce the voltage stress on the power switches in the converter, thereby improving energy conversion efficiency. This makes them ideal for LED driver applications with high efficiency requirements. Furthermore, hybrid-mode two-phase buck converters feature two-phase current output and spontaneously achieve two-phase current balancing through the self-current sharing effect introduced by the flying capacitors. This enables simultaneous equal current and brightness control for both LED strings, offering significant advantages in backlight applications with high requirements for light source uniformity. Summary of the Invention

[0004] The purpose of this invention is to propose a hybrid-mode two-phase buck converter suitable for driving multi-string LED backlights. This converter has a two-phase current output, enabling it to drive two LED strings simultaneously, and achieves equal current and equal brightness operation for the two strings through the self-current sharing effect of the flying capacitor. Simultaneously, this converter has a low voltage conversion ratio, is suitable for constant current driving of long strings of multiple LEDs connected in series, and exhibits high energy conversion efficiency.

[0005] The technical solution of this invention is as follows:

[0006] A hybrid-mode dual-phase buck converter for driving backlight LEDs, characterized in that it includes a power stage topology and a bootstrap driving circuit.

[0007] The power stage topology includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a capacitor C. F The circuit comprises: a first inductor L1, a second inductor L2, a first LED load string LEDs1, and a second LED load string LEDs2; the bootstrap driving circuit includes a first PMOS switch MP1, a second PMOS switch MP2, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a fourth driving module DRV4, a first potential shifting module LS1, a second potential shifting module LS2, a third potential shifting module LS3, and a first bootstrap capacitor C. BST1 Second bootstrap capacitor C BST2 Third bootstrap capacitor C BST3 Diode D1 and floating LDO module;

[0008] The source of the first NMOS transistor MN1 is connected to the positive terminal of the first inductor L1 and the flying capacitor C. F The upper plate has its gate connected to the output TG1 of the first drive module DRV1, and its drain connected to the converter input voltage V. IN The source of the second NMOS transistor MN2 is connected to the positive terminal of the second inductor L2 and the drain of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 is connected to the output TG2 of the second driver module DRV2, and the drain is connected to the input voltage V of the converter. IN The source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4 and the flying capacitor C. F The lower plate of the third NMOS transistor MN3 has its gate connected to the output TG3 of the third driver module DRV3, and its drain connected to the source of the second NMOS transistor MN2 and the second inductor L2. The source of the fourth NMOS transistor MN4 is grounded, its gate is connected to the output TG4 of the fourth driver module DRV4, and its drain is connected to the source of the third NMOS transistor MN3 and the flying capacitor C. F The lower plate is connected; the positive terminal of the first inductor L1 is connected to the source of the first NMOS transistor MN1 and the flying capacitor C. F The upper plate of the first LED load string LEDs1 is connected to the positive terminal of the negative terminal of the second LED load string LEDs1; the positive terminal of the second inductor L2 is connected to the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3, and the negative terminal is connected to the positive terminal of the second LED load string LEDs2; the negative terminals of the first LED load string LEDs1 and the second LED load string LEDs2 are both grounded.

[0009] The power supply terminal of the first drive module DRV1 is connected to the first bootstrap capacitor C. BST1 The upper plate is connected to the source of the first NMOS transistor MN1 and the flying capacitor C.F The upper plate of the first NMOS transistor MN1 has its input terminal connected to the output of the first potential shifting module LS1, and its output terminal connected to the gate of the first NMOS transistor MN1. The power supply terminal of the second drive module DRV2 is connected to the second bootstrap capacitor C. BST2 The upper plate of the circuit is connected to the source of the second NMOS transistor MN2, the positive terminal of the inductor L2, and the drain of the third NMOS transistor MN3. Its input is connected to the output of the second potential shifting module LS2, and its output is connected to the gate of the second NMOS transistor MN2. The power supply of the third drive module DRV3 is connected to the third bootstrap capacitor C. BST3 The upper plate is connected to the source of the third NMOS transistor MN3 and the flying capacitor C. F The lower electrode plate is connected to the output of the third potential shifting module LS3 at its input terminal, and to the gate of the third NMOS transistor MN3 at its output terminal; the power supply terminal of the fourth drive module DRV4 is connected to the drive voltage V. DR The ground terminal is connected to ground, the input terminal is connected to the drive signal S4, and the output terminal is connected to the gate of the fourth NMOS transistor MN4.

[0010] The power supply terminal of the first potential shifting module LS1 is connected to the first bootstrap capacitor C. BST1 The upper plate of the first NMOS transistor MN1 is connected to the source of the first NMOS transistor MN1 via ground, the input of which is connected to the drive signal S1, and the output of which is connected to the input of the first drive module DRV1. The power supply of the second potential shifting module LS2 is connected to the second bootstrap capacitor C. BST2 The upper plate of the third NMOS transistor LS3 is connected to the source of the second NMOS transistor MN2 via ground, its input is connected to the drive signal S2, and its output is connected to the input of the second drive module DRV2. The power supply of the third potential shifting module LS3 is connected to the third bootstrap capacitor C. BST3 The upper plate of the circuit is connected to the source of the third NMOS transistor MN3 via ground, the input of which is connected to the drive signal S3, and the output of which is connected to the input of the third drive module DRV3.

[0011] First bootstrap capacitor C BST1 The upper plate is connected to the power supply terminal of the first drive module DRV1 and the output of the floating LDO module, and the lower plate is connected to the source of the first NMOS transistor MN1; the second bootstrap capacitor C BST2 The upper plate is connected to the power supply terminal of the second drive module DRV2, and the lower plate is connected to the source of the second NMOS transistor MN2; the third bootstrap capacitor C BST3 The upper plate is connected to the power supply terminal of the third drive module DRV3, and the lower plate is connected to the source of the third NMOS transistor MN3.

[0012] The source of the first PMOS switch MP1 and the second bootstrap capacitor C BST2The upper plate is connected, the gate is connected to the control signal G1, and the drain is connected to the third bootstrap capacitor C. BST3 The upper plate of the first PMOS transistor is connected to the source of the second PMOS switch MP2; the source of the second PMOS switch is connected to the third bootstrap capacitor C. BST3 The upper plate has its gate connected to control signal G2 and its drain connected to drive voltage V. DR ;

[0013] The power supply terminal of the floating linear regulator module (Floating LDO) is connected to the cathode of diode D1, the ground terminal is connected to the source of the first NMOS transistor MN1, and the output terminal is connected to the first bootstrap driving capacitor C. BST1 The upper electrode plate;

[0014] The anode of diode D1 is connected to the converter input voltage V. IN The cathode is connected to the power supply terminal of the floating LDO module.

[0015] The beneficial effects of this invention are that the hybrid-mode dual-phase buck converter combines the advantages of traditional dual-phase buck converters and hybrid-mode DC-DC converters. By introducing flying capacitors, it achieves the balancing of dual-phase inductor currents and reduces the voltage stress on the switching transistors. It is very suitable for backlight driving applications of long LED strings and multiple LED strings, and has significant advantages in terms of light source uniformity and energy conversion efficiency. Attached Figure Description

[0016] Figure 1 This invention presents the power stage topology of a hybrid-mode two-phase buck converter.

[0017] Figure 2 The circuit diagram shows the power stage topology of the hybrid-mode dual-phase buck converter proposed in this invention.

[0018] Figure 3 This is a schematic diagram of the hybrid-mode two-phase buck converter topology proposed in this invention in operating states 1-3;

[0019] Figure 4 The waveform diagram shows the working waveforms of the hybrid-mode two-phase buck converter topology proposed in this invention.

[0020] Figure 5 This is a circuit diagram of an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of the operating current in state 1 of an embodiment of the present invention;

[0022] Figure 7 This is a schematic diagram of the operating current in state 2 of an embodiment of the present invention;

[0023] Figure 8This is a schematic diagram of the operating current in state 3 of an embodiment of the present invention;

[0024] Figure 9 This is a timing logic diagram of the control signals in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings.

[0026] For ease of description, the hybrid-mode two-phase buck converter of this invention is divided into two parts: a power stage topology and a bootstrap drive circuit module. The power stage topology includes four power switches S1, S2, S3, and S4, and a flying capacitor C. F Two inductors L1 and L2, and two LED load strings LEDs1 and LEDs2, as shown in the attached diagram. Figure 1 The power switching transistors can be NMOS or PMOS. Taking NMOS transistors as an example, the first NMOS transistor MN1 is switch S1, the second NMOS transistor MN2 is switch S2, the third NMOS transistor MN3 is switch S3, and the fourth NMOS transistor MN4 is switch S4, as shown in the attached diagram. Figure 2 The source of the first NMOS transistor MN1 is connected to the first inductor L1 and the flying capacitor C. F The upper plate is connected, and this node is denoted as SW1. The gate is connected to the drive signal TG1, and the drain is connected to the input voltage V. IN The source of the second NMOS transistor MN2 is connected to the inductor L2 and the drain of the third NMOS transistor MN3. This node is denoted as SW2. The gate is connected to the drive signal TG2, and the drain is connected to the input voltage V. IN The source of the third NMOS transistor MN3 and the flying capacitor C F The lower plate of the circuit is connected to the drain of the fourth NMOS transistor MN4, and this node is denoted as SW3. The gate of SW3 is connected to the drive signal TG3, and the drain is connected to the switching node SW2. The source of the fourth NMOS transistor MN4 is grounded, the gate is connected to the drive signal TG4, and the drain is connected to the switching node SW3. The other ends of inductors L1 and L2 are connected to the anodes of the LED load strings LEDs1 and LEDs2, respectively. The cathodes of the LED load strings LEDs1 and LEDs2 are both connected to ground.

[0027] The bootstrap driver circuit module is attached. Figure 5 It includes four drive modules DRV1, DRV2, DRV3, and DRV4, three potential shifting modules LS1, LS2, and LS3, and three bootstrap drive capacitors C. BST1 C BST2 C BST3 Two PMOS switches, MP1 and MP2, diode D1, and a floating LDO linear regulator module. The power supply of the first drive module DRV1 is connected to the first bootstrap capacitor C.BST1 The upper plate BST1 is grounded at the first switching node SW1 in the power stage topology, its input is connected to the output of the first potential shifting module LS1, and its output output is the drive signal TG1, which is connected to the gate of the first NMOS transistor MN1 in the power stage topology. The power supply of the second drive module DRV2 is connected to the second bootstrap capacitor C. BST2 The upper plate BST2 is grounded at the second switching node SW2 in the power stage topology. Its input is connected to the output of the second potential shifting module LS2, and its output is the drive signal TG2, which is connected to the gate of the second NMOS transistor MN2 in the power stage topology. The power supply of the third drive module DRV3 is connected to the third bootstrap capacitor C. BST3 The upper plate BST3 is connected to the ground terminal of the third switching node SW3 in the power stage topology. Its input terminal is connected to the output of the third potential shifting module LS3, and its output terminal outputs the drive signal TG3, which is connected to the gate of the third NMOS transistor MN3 in the power stage topology. The power supply of the fourth drive module DRV4 is connected to the drive voltage V. DR The ground terminal is connected to ground, the input terminal is driven by the signal S4, and the output terminal outputs the drive signal TG4 and is connected to the gate of the fourth NMOS transistor MN4 in the power stage topology.

[0028] The power supply terminal of the first potential shifting module LS1 is connected to BST1, the ground terminal is connected to the switch node SW1, the input terminal is the control signal S1, and the output terminal is connected to the input terminal of the first drive module DVR1. The power supply terminal of the second potential shifting module LS2 is connected to BST2, the ground terminal is connected to the switch node SW2, the input terminal is the control signal S2, and the output terminal is connected to the input terminal of the second drive module DVR2. The power supply terminal of the third potential shifting module LS3 is connected to BST3, the ground terminal is connected to the switch node SW3, the input terminal is the control signal S3, and the output terminal is connected to the input terminal of the third drive module DVR3.

[0029] First bootstrap driving capacitor C BST1 The upper plate is connected to BST1, and the lower plate is connected to the first switching node SW1; the second bootstrap driving capacitor C BST2 The upper plate is connected to BST2, and the lower plate is connected to the second switching node SW2; the third bootstrap driving capacitor C BST3 The upper electrode plate is connected to BST3, and the lower electrode plate is connected to the third switch node SW3.

[0030] The source of the first PMOS switch MP1 is connected to BST2, the gate is connected to the control signal G1, and the drain is connected to BST3. The source of the second PMOS switch MP2 is connected to BST3, the gate is connected to the control signal G2, and the drain is connected to the drive voltage V. DR .

[0031] The anode of diode D1 is connected to the input voltage V. INThe cathode is connected to the power supply terminal of the Floating LDO module. The ground terminal of the Floating LDO module is connected to the switching node SW1, and the output terminal is connected to BST1.

[0032] Appendix Figure 2 The circuit diagram of the power stage topology of the hybrid-mode dual-phase buck converter proposed in this invention includes a first NMOS switch MN1, a second NMOS switch MN2, a third NMOS switch MN3, a fourth NMOS switch MN4, and a flying capacitor C. F The first inductor L1, the second inductor L2, the first LED load string LEDs1, and the second LED load string LEDs2 are described in this invention. The hybrid-mode two-phase buck converter proposed in this invention adds a flying capacitor to the traditional two-phase buck converter to handle the voltage drop, reducing the voltage stress on the power switching transistors to V. IN / 2. This improves its energy conversion efficiency. Furthermore, the flying capacitor introduces a two-phase self-current sharing effect into the topology, allowing the topology itself to balance the average value of the two-phase inductor currents.

[0033] The hybrid-mode two-phase buck converter proposed in this invention has three operating states: State 1, State 2, and State 3, as shown in the attached diagram. Figure 3 As shown, when the converter is operating in a steady state, the flying capacitor C F The voltage drop across the two ends is V IN / 2. In operating state 1, switches S1 and S3 are on, and switches S2 and S4 are off. At this time, the voltage at switch node SW1 is V. IN The voltage at switching nodes SW2 and SW3 is V. IN / 2. In this state, the voltage across inductor L1 is V. IN -V OUT1 Therefore, inductor L1 is in a charging state, and the current in it flows at a slope (V IN -V OUT1) / L1 increases linearly. The voltage across inductor L2 is V. IN / 2-V OUT2 Therefore, inductor L2 is in a discharging state, and the current in L2 flows at a slope (V). IN / 2-V OUT2 The ratio C decreases linearly. In this state, the flying capacitance C... F The inductor L2 is charged by the current flowing through it, and the voltage across it gradually increases. Since inductors L1 and L2 are connected in series with the LED load strings LEDs1 and LEDs2 respectively, the current in the load strings is equal to the inductor current.

[0034] In operating state 2, switches S2 and S4 are on, and switches S1 and S3 are off. At this time, the voltage at switch node SW1 is V. IN / 2, the voltage at switch node SW2 is V IN The voltage at switch node SW3 is 0. In this state, the voltage across inductor L1 is V. IN / 2-V OUT1 Therefore, inductor L1 is in a discharging state, and its current flows at a slope (V IN / 2-V OUT1 The voltage across inductor L1 decreases linearly. Simultaneously, the voltage across inductor L2 is V. IN -V OUT2 Therefore, L2 is in a charging state, causing the current in inductor L2 to flow according to the slope (V). IN -V OUT2 The ratio C increases linearly. At this point, the flying capacitor C... F The current discharges through inductor L1, thereby causing the flying capacitor C to... F The voltage across the two ends gradually decreases.

[0035] In operating state 3, switches S1 and S2 are on, while switches S3 and S4 are off. At this time, the voltages across the two inductors L1 and L2 can be expressed as V. IN -V OUT1 V IN -V OUT2 Both inductors are in a charging state, and their inductor current rise slopes are respectively (V IN -V OUT1 ) / L1、(V IN -V OUT2 ) / L2. In this state, the flying capacitor C F No current flows through it, so the voltage across it remains constant in state 3.

[0036] The operating sequence of the three states of the hybrid-mode two-phase buck converter power stage topology is state 1, state 3, state 2, state 3. The three operating states cycle in the above order, and their operating waveforms are shown in the attached figure. Figure 4 The control signals D1 and D2 have the same period and duty cycle, with a 180° (half a period) phase difference between them. When control signal D1 is high and control signal D2 is low, the converter operates in state 1, at which time the voltage at switch node SW1 is equal to V. IN The voltage at switching nodes SW2 and SW3 is V. IN / 2. Inductor L1 charges and its inductor current increases linearly, while inductor L2 discharges and its current decreases linearly. During this stage, the flying capacitor C... F The current in capacitor C is equal to the current in inductor L2 and flows in from the upper plate; therefore, the flying capacitor C... FVoltage V across two terminals CF increases gradually. When the control signal D1 is at low level and the control signal D2 is at high level, the converter operates in state 2, and the voltage of the switching node SW1 is equal to V IN / 2, the voltage of the switching node SW2 is V IN , and the voltage of the switching node SW3 is 0. Therefore, the inductor L1 is in a discharging state, and the current thereon decreases linearly, while the inductor L2 is in a charging state, and the current thereon is in a linearly rising stage. At this time, the current on the flying capacitor C F is equal to the current on the inductor L1 and flows out from the upper plate, so the voltage V across the flying capacitor C F across two terminals V CF decreases gradually. When both the control signals D1 and D2 are at high level, the converter operates in state 3, and the voltages of the switching nodes SW1 and SW2 are both V IN , and the voltage of the switching node SW3 is equal to V IN / 2. At this time, both the inductors L1 and L2 are in a charging state, and the two-phase inductor currents rise simultaneously. When the converter operates in state 3, no current passes through the flying capacitor C F , so the voltage V across its two terminals CF remains unchanged.

[0037] It can be known from the foregoing working mode of the power stage topology and the attached Figure 4 that the duty cycles of both the control signals D1 and D2 are greater than 0.5. According to the volt-second balance of the inductors L1 and L2, it can be obtained that the voltage conversion ratio CR of the converter is (1+D) / 2. When the duty cycle of the control signal satisfies 0.5<D<1, the voltage conversion ratio range of the converter proposed by the present invention is 0.75 to 1. When the load light string is composed of a plurality of LEDs connected in series, the conduction voltage drop thereof is usually relatively high, so a lower voltage conversion ratio is very beneficial for the driving application of long LED light strings. When the voltage conversion ratio is the same, the duty cycle D of the converter proposed by the present invention is lower than that of the traditional Buck converter, so it has significant advantages in high-frequency applications. Meanwhile, according to the volt-second balance of the inductors L1 and L2, it can be obtained that the voltage drop of the flying capacitor C F during stable operation is V IN / 2, which reduces the voltage stress of the power switch of the converter to half that of the traditional Buck converter, so that the switching loss is greatly reduced. In addition, when the converter is in a stable operating state, the charge balance of the flying capacitor C F requires that the charging and discharging charge amounts thereof in one switching cycle are equal, thereby realizing self-balancing of the two-phase inductor currents. Therefore, better light source uniformity can be achieved in LED backlight applications, and the driving cost is reduced.

[0038] the attached Figure 5The circuit diagram shown in this embodiment of the invention comprises two parts: a power stage topology circuit and a bootstrap driving circuit. The power stage topology circuit is the one described above. Figure 2 The circuit shown includes four power switching transistors MN1, MN2, MN3, and MN4, two inductors L1 and L2, and a flying capacitor C. F And two LED load strings, LEDs1 and LEDs2. The bootstrap driver circuit includes four driver modules DRV1, DRV2, DRV3, and DRV4, three potential shifting modules LS1, LS2, and LS3, and three bootstrap driver capacitors C. BST1 C BST2 C BST3 Two PMOS switches, MP1 and MP2, diode D1, and a floating LDO linear regulator module.

[0039] Specifically, the bootstrap drive circuit has three operating states: State 1, State 2, and State 3. These states work in conjunction with the three operating states of the power stage topology to achieve bootstrap driving of the power transistors in the power stage topology. The four drive modules DRV1, DRV2, DRV3, and DRV4 serve as the turn-on and turn-off drive circuits for the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 in the power stage topology, respectively. The first potential shifting module LS1 shifts the control signal S1 from the drive voltage V... DR The voltage domain is shifted from BST1 to SW1, and the second potential shifting module LS2 shifts the control signal S2 from the drive voltage V to the ground voltage domain. DR The voltage domain is shifted from BST2 to SW2 voltage domain, and the third potential shifting module LS3 shifts the control signal S3 from the drive voltage V. DR The voltage domain to ground is shifted to the voltage domain from BST3 to SW3. The first bootstrap drive capacitor C... BST1 Controlled by diode D1 and the floating LDO module, the converter input voltage V IN During charging, the voltage across its terminals serves as the power supply voltage and ground voltage for the first drive module DRV1, driving the first NMOS transistor MN1 and achieving bootstrap driving of the first NMOS transistor MN1; the second bootstrap driving capacitor C... BST2 Controlled by the first PMOS switch MP1, and driven by the third bootstrap capacitor C BST3 During charging, the voltage across its terminals serves as the power supply voltage and ground voltage for the second drive module DRV2, driving the second NMOS transistor MN2 and achieving bootstrap driving of the second NMOS transistor MN2; the third bootstrap driving capacitor C BST3 Controlled by the second PMOS switch MP2, and driven by the voltage VDR The charging process uses the voltage across its terminals as the power supply and ground voltage for the third drive module DRV3 to drive the third NMOS transistor MN3, thus achieving bootstrapping drive for MN3. The floating LDO module generates a stable voltage drop between the switching nodes SW1 and BST1, and its output voltage is equal to the drive voltage V. DR Diode D1 is in a state of flux from the input voltage V. IN On the charging path between the floating LDO and the floating ground linear regulator module, when the voltage at switching node SW1 rises to the level of V... IN When they are equal, diode D1 can prevent the first bootstrap capacitor C from being blocked. BST1 The charge on the circuit is discharged to the input voltage V. IN .

[0040] When control signal D1 is high and control signal D2 is low, both the bootstrap drive circuit and the power stage topology circuit operate in State 1, as shown in the attached diagram. Figure 6 As shown. In this state, the first NMOS transistor MN1 is turned on, and the first bootstrap capacitor C... BST1 Power is supplied to the first drive module DRV1 and the first potential shift module LS1. Simultaneously, the second NMOS transistor MN2 is turned off, therefore the second drive module DRV2 and the second potential shift module LS2 are not operational. The third NMOS transistor MN3 and the first PMOS switch MP1 are turned on, at which time the third bootstrap drive capacitor C... BST3 The first PMOS switch MP1 serves as the second bootstrap capacitor C. BST2 The circuit charges and simultaneously powers the third drive module DRV3 and the third potential shift module LS3. At the same time, the fourth NMOS transistor MN4 is turned off, and the fourth drive module DRV4 ceases operation.

[0041] When control signal D1 is low and control signal D2 is high, both the bootstrap drive circuit and the power stage topology circuit operate in State 2, as shown in the attached diagram. Figure 7 As shown. At this time, the first NMOS transistor MN1 is turned off, therefore the first drive module DRV1 and the first potential shift module LS1 are not working, and the input voltage V IN The floating ground linear regulator module (Floating LDO) is powered by the forward-biased diode D1. Simultaneously, the floating ground linear regulator module (Floating LDO) is powered by the first bootstrap capacitor C. BST1 Charge to V DR In this state, the second NMOS transistor MN2 is turned on, the first PMOS switch MP1 is turned off, and the second bootstrap capacitor C... BST2Power is supplied to the second drive module DRV2 and the second potential shift module LS2. Simultaneously, the third NMOS transistor MN3 is turned off and the second PMOS switch MP2 is turned on. At this time, the third drive module DRV3 and the third potential shift module LS3 are not operating, and the drive voltage V... DR The second PMOS switch MP2 serves as the third bootstrap capacitor C. BST3 Charging. The fourth NMOS transistor MN4 is turned on, and the drive voltage V... DR Power supply to the fourth drive module DRV4.

[0042] When both control signals D1 and D2 are high, the bootstrap drive circuit and the power stage topology circuit operate in State 3, as shown in the attached diagram. Figure 8 As shown. At this time, the first NMOS transistor MN1 is turned on, and the first bootstrap capacitor C... BST1 Power is supplied to the first drive module DRV1 and the first potential shift module LS1. Simultaneously, the second NMOS transistor MN2 is turned on, therefore the second bootstrap capacitor C... BST2 Power is supplied to the second drive module DRV2 and the second potential shift module LS2. In this state, the first PMOS switch MP1 and the second PMOS switch MP2 are both off, while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are also off. At this time, the third drive module DRV3, the third potential shift module LS3, and the fourth drive module DRV4 are all inactive.

[0043] Appendix Figure 9 This is a timing logic diagram of the control signals in an embodiment of the present invention. S1, S2, S3, and S4 are the input signals of the first potential shift module LS1, the second potential shift module LS2, the third potential shift module LS3, and the fourth drive module DRV4, respectively; TG1, TG2, TG3, and TG4 are the gate signals of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4, respectively; and G1 and G2 are the gate signals of the first PMOS switch MP1 and the second PMOS switch MP2, respectively.

[0044] When control signal D1 is high and control signal D2 is low, the converter operates in state 1. At this time, the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned on, while the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are turned off. Therefore, control signals S1 and S3 are high, while control signals S2 and S4 are low. In this state, the voltage of the gate signal TG1 of the first NMOS transistor MN1 is V. IN +V DR The voltage of the gate signal TG2 of the second NMOS transistor MN2 is equal to V. IN / 2, the voltage of the gate signal TG3 of the third NMOS transistor MN3 is VIN / 2+V DR Meanwhile, the voltage of the gate signal TG4 of the fourth NMOS transistor MN4 is equal to 0. Furthermore, since the first PMOS switch MP1 is turned on and the second PMOS switch MP2 is turned off in state 1, the voltage of the gate signal G1 of the first PMOS switch MP1 is V at this time. IN / 2, the voltage of the gate signal G2 of the second PMOS switch MP2 is V IN / 2+V DR .

[0045] When control signal D1 is low and control signal D2 is high, the converter operates in state 2. At this time, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are turned on, while the first NMOS transistor MN1 and the third NMOS transistor MN3 are turned off. Therefore, control signals S2 and S4 are high, while control signals S1 and S3 are low. In this state, the voltage of the gate signal TG1 of the first NMOS transistor MN1 is V. IN / 2, the voltage of the gate signal TG2 of the second NMOS transistor MN2 is equal to V IN +V DR The voltage of the gate signal TG3 of the third NMOS transistor MN3 is 0, while the voltage of the gate signal TG4 of the fourth NMOS transistor MN4 is equal to V. DR Furthermore, since the first PMOS switch MP1 is off and the second PMOS switch MP2 is on in state 2, the voltage of the gate signal G1 of the first PMOS switch MP1 is V at this time. IN +V DR The voltage of the gate signal G2 of the second PMOS switch MP2 is 0.

[0046] When control signals D1 and D2 are both high, the converter operates in state 3. At this time, the first NMOS transistor MN1 and the second NMOS transistor MN2 are turned on, while the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are turned off. Therefore, control signals S1 and S2 are high, while control signals S3 and S4 are low. In this state, the voltages of the gate signal TG1 of the first NMOS transistor MN1 and the gate signal TG2 of the second NMOS transistor MN2 are both V. IN +V DR The voltage of the gate signal TG3 of the third NMOS transistor MN3 is V. IN / 2, while the voltage of the gate signal TG4 of the fourth NMOS transistor MN4 is equal to 0. Furthermore, since both the first PMOS switch MP1 and the second PMOS switch MP2 are turned off in state 3, the voltage of the gate signal G1 of the first PMOS switch MP1 is V at this time. IN +V DR The voltage of the gate signal G2 of the second PMOS switch MP2 is V.IN / 2+V DR .

[0047] As can be seen from the above specific embodiments: the low voltage ratio hybrid mode two-phase buck converter proposed in this invention uses a flying capacitor C F By introducing a two-phase current self-balancing mechanism and reducing the voltage stress on the power switches, the energy conversion efficiency of the converter is improved while achieving better light source uniformity. Simultaneously, the converter's low voltage conversion ratio gives it a significant advantage in applications with multiple LEDs connected in series. The inductor current of the two-phase output can simultaneously drive two identical LED strings, greatly saving driving costs and reducing circuit area. Furthermore, the introduction of flying capacitors extends the converter's effective duty cycle. With the same voltage conversion ratio, the duty cycle of the converter proposed in this invention is smaller than that of traditional Buck converters, which is beneficial for its high-frequency development. Due to the aforementioned low voltage conversion ratio and two-phase current sharing output characteristics, the hybrid-mode two-phase buck converter proposed in this invention is suitable for series-connected LED backlight driving applications with high requirements for output current accuracy.

Claims

1. A hybrid-mode two-phase buck converter for driving backlight LEDs, characterized in that, Including power stage topology and bootstrap driver circuitry; The power stage topology includes a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a capacitor C. F The circuit comprises: a first inductor L1, a second inductor L2, a first LED load string LEDs1, and a second LED load string LEDs2; the bootstrap driving circuit includes a first PMOS switch MP1, a second PMOS switch MP2, a first driving module DRV1, a second driving module DRV2, a third driving module DRV3, a fourth driving module DRV4, a first potential shifting module LS1, a second potential shifting module LS2, a third potential shifting module LS3, and a first bootstrap capacitor C. BST1 Second bootstrap capacitor C BST2 Third bootstrap capacitor C BST3 Diode D1 and floating LDO module; The source of the first NMOS transistor MN1 is connected to the positive terminal of the first inductor L1 and the flying capacitor C. F The upper plate has its gate connected to the output TG1 of the first drive module DRV1, and its drain connected to the converter input voltage V. IN The source of the second NMOS transistor MN2 is connected to the positive terminal of the second inductor L2 and the drain of the third NMOS transistor MN3. The gate of the second NMOS transistor MN2 is connected to the output TG2 of the second driver module DRV2, and the drain is connected to the input voltage V of the converter. IN The source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4 and the flying capacitor C. F The lower plate of the third NMOS transistor MN3 has its gate connected to the output TG3 of the third driver module DRV3, and its drain connected to the source of the second NMOS transistor MN2 and the second inductor L2. The source of the fourth NMOS transistor MN4 is grounded, its gate is connected to the output TG4 of the fourth driver module DRV4, and its drain is connected to the source of the third NMOS transistor MN3 and the flying capacitor C. F The lower plate is connected; the positive terminal of the first inductor L1 is connected to the source of the first NMOS transistor MN1 and the flying capacitor C. F The upper plate of the first LED load string LEDs1 is connected to the positive terminal of the negative terminal of the second LED load string LEDs1; the positive terminal of the second inductor L2 is connected to the source of the second NMOS transistor MN2 and the drain of the third NMOS transistor MN3, and the negative terminal is connected to the positive terminal of the second LED load string LEDs2; the negative terminals of the first LED load string LEDs1 and the second LED load string LEDs2 are both grounded. The power supply terminal of the first drive module DRV1 is connected to the first bootstrap capacitor C. BST1 The upper plate is connected to the source of the first NMOS transistor MN1 and the flying capacitor C. F The upper plate of the first NMOS transistor MN1 has its input terminal connected to the output of the first potential shifting module LS1, and its output terminal connected to the gate of the first NMOS transistor MN1. The power supply terminal of the second drive module DRV2 is connected to the second bootstrap capacitor C. BST2 The upper plate of the circuit is connected to the source of the second NMOS transistor MN2, the positive terminal of the inductor L2, and the drain of the third NMOS transistor MN3. Its input is connected to the output of the second potential shifting module LS2, and its output is connected to the gate of the second NMOS transistor MN2. The power supply of the third drive module DRV3 is connected to the third bootstrap capacitor C. BST3 The upper plate is connected to the source of the third NMOS transistor MN3 and the flying capacitor C. F The lower electrode plate is connected to the output of the third potential shifting module LS3 at its input terminal, and to the gate of the third NMOS transistor MN3 at its output terminal; the power supply terminal of the fourth drive module DRV4 is connected to the drive voltage V. DR The ground terminal is connected to ground, the input terminal is connected to the drive signal S4, and the output terminal is connected to the gate of the fourth NMOS transistor MN4. The power supply terminal of the first potential shifting module LS1 is connected to the first bootstrap capacitor C. BST1 The upper plate of the first NMOS transistor MN1 is connected to the source of the first NMOS transistor MN1 via ground, the input of which is connected to the drive signal S1, and the output of which is connected to the input of the first drive module DRV1. The power supply of the second potential shifting module LS2 is connected to the second bootstrap capacitor C. BST2 The upper plate of the third NMOS transistor LS3 is connected to the source of the second NMOS transistor MN2 via ground, its input is connected to the drive signal S2, and its output is connected to the input of the second drive module DRV2. The power supply of the third potential shifting module LS3 is connected to the third bootstrap capacitor C. BST3 The upper plate of the circuit is connected to the source of the third NMOS transistor MN3 via ground, the input of which is connected to the drive signal S3, and the output of which is connected to the input of the third drive module DRV3. First bootstrap capacitor C BST1 The upper plate is connected to the power supply terminal of the first drive module DRV1 and the output of the floating LDO module, and the lower plate is connected to the source of the first NMOS transistor MN1; the second bootstrap capacitor C BST2 The upper plate is connected to the power supply terminal of the second drive module DRV2, and the lower plate is connected to the source of the second NMOS transistor MN2; the third bootstrap capacitor C BST3 The upper plate is connected to the power supply terminal of the third drive module DRV3, and the lower plate is connected to the source of the third NMOS transistor MN3. The source of the first PMOS switch MP1 and the second bootstrap capacitor C BST2 The upper plate is connected, the gate is connected to the control signal G1, and the drain is connected to the third bootstrap capacitor C. BST3 The upper plate of the first PMOS transistor is connected to the source of the second PMOS switch MP2; the source of the second PMOS switch is connected to the third bootstrap capacitor C. BST3 The upper plate has its gate connected to control signal G2 and its drain connected to drive voltage V. DR ; The power supply terminal of the floating linear regulator module (Floating LDO) is connected to the cathode of diode D1, the ground terminal is connected to the source of the first NMOS transistor MN1, and the output terminal is connected to the first bootstrap driving capacitor C. BST1 The upper electrode plate; The anode of diode D1 is connected to the converter input voltage V. IN The cathode is connected to the power supply terminal of the FloatingLDO module.

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