Pulse width modulation controller and method of controlling the same

Abstract

A pulse width modulation controller and a control method thereof, comprising a current detector, a current simulator, a voltage-to-current converter, and a current adder. The current detector can detect a first current and generate a second current according to the first current, wherein the current detector can receive an input voltage and output an output voltage. The current simulator can obtain a related information of a lower bridge current. The voltage-to-current converter can draw a third current from the current simulator according to the input voltage and the output voltage, wherein the current simulator can generate a fourth current according to the related information and the third current. The current adder can add the second current and the fourth current to generate a sum current.

Description

Technical Field

[0001] This invention relates to a pulse width modulation controller, and more particularly to a pulse width modulation controller that can reduce distortion. Background Technology

[0002] In traditional designs, pulse width modulation (PWM) controllers often suffer from drawbacks such as insufficiently timely transmission of current information and excessively long transient response times. These shortcomings frequently lead to subsequent output distortion and poor overall linearity. Therefore, it is essential to propose a novel solution to overcome the limitations of previous technologies. Summary of the Invention

[0003] In a preferred embodiment, the present invention provides a pulse width modulation controller, comprising: a current detector for detecting a first current and generating a second current based on the first current, wherein the current detector further receives an input potential and outputs an output potential; a current simulator for obtaining relevant information about a lower bridge current; a voltage-to-current converter for drawing a third current from the current simulator based on the input potential and the output potential, wherein the current simulator further generates a fourth current based on the relevant information and the third current; and a current adder for adding the second current and the fourth current to generate a summed current.

[0004] In some embodiments, the second current is approximately proportional to the first current.

[0005] In some embodiments, the fourth current approaches the second current.

[0006] In some embodiments, the current detector includes: a first transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a first node, the first terminal of the first transistor is coupled to an input node to receive the input potential, and the second terminal of the first transistor is coupled to a second node; an inductor having a first terminal and a second terminal, wherein the first terminal of the inductor is coupled to the second node, and the second terminal of the inductor is coupled to an output node to output the output potential; and a second transistor having... A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the first node, the first terminal of the second transistor is coupled to a third node, and the second terminal of the second transistor is coupled to the input node; and a third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the first node, the first terminal of the third transistor is coupled to a fourth node, and the second terminal of the third transistor is coupled to the second node; wherein the first current flows through the first transistor.

[0007] In some embodiments, the current detector further includes: a fourth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to a fifth node, the first terminal of the fourth transistor is coupled to the third node, and the second terminal of the fourth transistor is coupled to the fifth node; and a fifth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is coupled to the fifth node, the first terminal of the fifth transistor is coupled to the fourth node, and the second terminal of the fifth transistor is coupled to a sixth node.

[0008] In some embodiments, the current detector further includes: a sixth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to a seventh node, the first terminal of the sixth transistor is coupled to the fifth node, and the second terminal of the sixth transistor is coupled to an eighth node; and a seventh transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh transistor is coupled to the seventh node, the first terminal of the seventh transistor is coupled to the sixth node, and the second terminal of the seventh transistor is coupled to a ninth node.

[0009] In some embodiments, the current detector further includes: an output transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the output transistor is coupled to the sixth node, the first terminal of the output transistor is coupled to the third node, and the second terminal of the output transistor is coupled to a first adder node to output the second current; a first current sink drawing a first bias current from the eighth node; and a second current sink drawing a second bias current from the ninth node, wherein the second bias current is approximately equal to the first bias current.

[0010] In some embodiments, the first transistor, the second transistor, and the third transistor are each an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET).

[0011] In some embodiments, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the output transistor are each a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET).

[0012] In some embodiments, the current simulator includes: an eighth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth transistor is coupled to a tenth node, the first terminal of the eighth transistor is coupled to a ground potential, and the second terminal of the eighth transistor is coupled to the tenth node to receive the lower bridge current; and a ninth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth transistor is coupled to the tenth node, the first terminal of the ninth transistor is coupled to the ground potential, and the second terminal of the ninth transistor is coupled to an eleventh node.

[0013] In some embodiments, the current simulator further includes: a tenth transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the tenth transistor is coupled to the eleventh node, the first terminal of the tenth transistor is coupled to a supply potential, and the second terminal of the tenth transistor is coupled to the eleventh node; a first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to the eleventh node, and the second terminal of the first switch is coupled to a twelfth node; and a capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled to the supply potential, and the second terminal of the capacitor is coupled to the twelfth node.

[0014] In some embodiments, the current simulator further includes: an eleventh transistor having a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eleventh transistor is coupled to the twelfth node, the first terminal of the eleventh transistor is coupled to the supply potential, and the second terminal of the eleventh transistor is coupled to a second adder node to output the fourth current; and a second switch having a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the twelfth node, and the second terminal of the second switch is coupled to a thirteenth node.

[0015] In some embodiments, the eighth transistor and the ninth transistor are each an N-type metal-oxide-semiconductor field-effect transistor.

[0016] In some embodiments, the tenth transistor and the eleventh transistor are each a P-type metal-oxide-semiconductor field-effect transistor.

[0017] In some embodiments, the first switch selectively turns on or off according to a first control potential, while the second switch selectively turns on or off according to a second control potential.

[0018] In some embodiments, the first control potential and the second control potential have substantially complementary logic levels.

[0019] In some embodiments, the voltage-to-current converter includes: a first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is used to receive the input potential, and the second terminal of the first resistor is coupled to a fourteenth node; and a second resistor having a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the fourteenth node, and the second terminal of the second resistor is coupled to the ground potential.

[0020] In some embodiments, the voltage-to-current converter further includes: a third resistor having a first terminal and a second terminal, wherein the first terminal of the third resistor is used to receive the output potential, and the second terminal of the third resistor is coupled to a fifteenth node; and a fourth resistor having a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the fifteenth node, and the second terminal of the fourth resistor is coupled to the ground potential.

[0021] In some embodiments, the voltage-to-current converter further includes: a comparator circuit having a positive input, a negative input, and an output, wherein the positive input of the comparator circuit is coupled to the fourteenth node, the negative input of the comparator circuit is coupled to the fifteenth node, and the output of the comparator circuit is used to output a third control potential; and a dependent current sink that draws a third current from the thirteenth node according to the third control potential, wherein the third current is approximately proportional to a potential difference between the input potential and the output potential.

[0022] In another preferred embodiment, the present invention proposes a pulse width modulation control method, comprising the following steps: detecting a first current and generating a second current based on the first current; obtaining relevant information about a lower bridge current using a current simulator; drawing a third current from the current simulator based on an input potential and an output potential; generating a fourth current using the current simulator based on the relevant information and the third current; and adding the second current and the fourth current to generate a sum current.

[0023] This invention proposes a novel pulse width modulation (PWM) controller and its control method. Compared with traditional designs, this invention has advantages such as shortening transient response time, suppressing output distortion, and improving overall linearity, making it well-suited for application in various electronic devices. Attached Figure Description

[0024] Figure 1 This diagram shows a pulse width modulation controller according to an embodiment of the present invention.

[0025] Figure 2 This diagram shows a circuit diagram of a pulse width modulation controller according to an embodiment of the present invention.

[0026] Figure 3 This displays a potential waveform diagram of a pulse width modulation controller according to an embodiment of the present invention.

[0027] Figure 4 The diagram shows the current waveform of a pulse width modulation controller according to an embodiment of the present invention.

[0028] Figure 5 This diagram shows a flowchart of a pulse width modulation control method according to an embodiment of the present invention.

[0029] Attached icon number

[0030] 100, 200: Pulse Width Modulation Controller

[0031] 110, 210: Current detector

[0032] 120,220: Current simulator

[0033] 130, 230: Voltage to Current Converter

[0034] 140, 240: Current adders

[0035] 212: First current absorber

[0036] 214: Second current absorber

[0037] 222: First Switcher

[0038] 224: Second Switcher

[0039] 232: Comparator Circuit

[0040] 234: Dependent Current Absorber

[0041] 250: Lower bridge current source

[0042] CM: Capacitor

[0043] IA: First Current

[0044] IB: Second Current

[0045] IC: Third Current

[0046] ID: Fourth Current

[0047] IF: Information related to the lower bridge current

[0048] IG: Down-bridge current

[0049] IK1: First bias current

[0050] IK2: Second bias current

[0051] IS: Total Current

[0052] LM: Inductor

[0053] M1: First transistor

[0054] M2: Second transistor

[0055] M3: Third transistor

[0056] M4: Fourth transistor

[0057] M5: Fifth Transistor

[0058] M6: Sixth Transistor

[0059] M7: Seventh Transistor

[0060] M8: Eighth transistor

[0061] M9: Ninth Transistor

[0062] M10: Tenth Transistor

[0063] M11: Eleventh Transistor

[0064] MG: Output transistor

[0065] N1: First node

[0066] N2: Second node

[0067] N3: Third node

[0068] N4: Fourth Node

[0069] N5: Fifth Node

[0070] N6: Sixth Node

[0071] N7: Seventh Node

[0072] N8: Eighth Node

[0073] N9: Ninth Node

[0074] N10: Tenth Node

[0075] N11: Eleventh Node

[0076] N12: The twelfth node

[0077] N13: The Thirteenth Node

[0078] N14: The fourteenth node

[0079] N15: The fifteenth node

[0080] ND1: First adder node

[0081] ND2: Second adder node

[0082] NIN: Input node

[0083] NOUT: Output node

[0084] VC1: First control potential

[0085] VC2: Second control potential

[0086] VC3: Third control potential

[0087] VF: Capacitance potential

[0088] VIN: Input potential

[0089] VLG: Lower bridge drive potential

[0090] VOUT: Output potential

[0091] VUG: Upper bridge drive potential

[0092] R1: First resistor

[0093] R2: Second resistor

[0094] R3: Third resistor

[0095] R4: Fourth resistor

[0096] S510, S520, S530, S540, S550: Steps

[0097] T1: First Operation Phase

[0098] T2: Second Operation Phase

[0099] T3: Third Operation Phase

[0100] TON: High Logic Duration Detailed Implementation

[0101] To make the objectives, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in conjunction with the accompanying drawings for detailed explanation.

[0102] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "including but not limited to". The term "generally" means that within an acceptable margin of error, those skilled in the art can solve the technical problem and achieve the basic technical effect within a certain margin of error. Furthermore, the term "coupled" in this specification includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device via other devices or connection means.

[0103] Figure 1 This diagram illustrates a pulse width modulation (PWM) controller 100 according to an embodiment of the present invention. For example, the PWM controller 100 can be applied to a mobile device or an automotive chip, but is not limited thereto. Figure 1 In one embodiment, the pulse width modulation controller 100 includes: a current detector 110, a current simulator 120, a voltage-to-current converter 130, and a current adder 140. It must be understood that, although not shown in... Figure 1 However, the pulse width modulation controller 100 may also include other components, such as a processor, an upper-gate circuit, a lower-gate circuit, or a driving circuit.

[0104] Current detector 110 can detect a first current IA and generate a second current IB based on the first current IA. For example, the second current IB can be approximately proportional to the first current IA. Current detector 110 can also receive an input potential VIN and output an output potential VOUT. Current simulator 120 can obtain a related information IF of a lower bridge current IG, where the lower bridge current IG may come from a lower bridge circuit (not shown). Voltage-to-current converter 130 can draw a third current IC from current simulator 120 based on the input potential VIN and the output potential VOUT. Current simulator 120 can also generate a fourth current ID based on the related information IF of the lower bridge current IG and the third current IC. Finally, current adder 140 can add the second current IB and the fourth current ID to generate a total current IS. For example, the fourth current ID can be close to the second current IB. Under the design of this invention, the operating information of current detector 110, current simulator 120, and voltage-to-current converter 130 can be easily obtained by analyzing the total current IS. Based on actual measurement results, the proposed pulse width modulation controller 100 helps to shorten its transient response time, suppress its output distortion, and improve overall linearity.

[0105] The following embodiments will describe the detailed structure and operating principle of the pulse width modulation controller 100. It must be understood that these figures and descriptions are merely illustrative and not intended to limit the scope of the invention.

[0106] Figure 2 This diagram shows a circuit diagram of a pulse width modulation controller 200 according to an embodiment of the present invention. Figure 2In one embodiment, the pulse width modulation controller 200 has an input node NIN and an output node NOUT, and includes: a current detector 210, a current simulator 220, a voltage-to-current converter 230, and a current adder 240, wherein the input node NIN of the pulse width modulation controller 200 can be used to receive an input potential VIN, and the output node NOUT of the pulse width modulation controller 200 can be used to output an output potential VOUT.

[0107] The current detector 210 includes: a first current sink 212, a second current sink 214, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an output transistor MG, and an inductor LM. For example, the first transistor M1, the second transistor M2, and the third transistor M3 can each be an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET), while the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the output transistor MG can each be a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET).

[0108] The first transistor M1 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the first transistor M1 is coupled to a first node N1, the first terminal of the first transistor M1 is coupled to an input node NIN, and the second terminal of the first transistor M1 is coupled to a second node N2. It is important to note that a first current IA can flow through the first transistor M1. The inductor LM has a first terminal and a second terminal. The first terminal of the inductor LM is coupled to the second node N2, and the second terminal of the inductor LM is coupled to an output node NOUT. The second transistor M2 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the second transistor M2 is coupled to the first node N1, the first terminal of the second transistor M2 is coupled to a third node N3, and the second terminal of the second transistor M2 is coupled to the input node NIN. The third transistor M3 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain), wherein the control terminal of the third transistor M3 is coupled to a first node N1, the first terminal of the third transistor M3 is coupled to a fourth node N4, and the second terminal of the third transistor M3 is coupled to a second node N2.

[0109] The fourth transistor M4 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fourth transistor M4 is coupled to a fifth node N5, the first terminal of the fourth transistor M4 is coupled to a third node N3, and the second terminal of the fourth transistor M4 is coupled to the fifth node N5. The fifth transistor M5 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the fifth transistor M5 is coupled to the fifth node N5, the first terminal of the fifth transistor M5 is coupled to the fourth node N4, and the second terminal of the fifth transistor M5 is coupled to a sixth node N6.

[0110] The sixth transistor M6 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the sixth transistor M6 is coupled to a seventh node N7, the first terminal of the sixth transistor M6 is coupled to a fifth node N5, and the second terminal of the sixth transistor M6 is coupled to an eighth node N8. The seventh transistor M7 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the seventh transistor M7 is coupled to a seventh node N7, the first terminal of the seventh transistor M7 is coupled to a sixth node N6, and the second terminal of the seventh transistor M6 is coupled to a ninth node N9.

[0111] The output transistor MG has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the output transistor MG is coupled to a sixth node N6, the first terminal of the output transistor MG is coupled to a third node N3, and the second terminal of the output transistor MG is coupled to a first adder node ND1 to output a second current IB. A first current sink 212 can draw a first bias current IK1 from an eighth node N8. A second current sink 214 can draw a second bias current IK2 from a ninth node N9. For example, the second bias current IK2 can be approximately equal to the first bias current IK1.

[0112] The current simulator 220 includes a first switch element 222, a second switch element 224, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a capacitor CM. For example, the eighth transistor M8 and the ninth transistor M9 may each be an N-type metal-oxide-semiconductor field-effect transistor, while the tenth transistor M10 and the eleventh transistor M11 may each be a P-type metal-oxide-semiconductor field-effect transistor.

[0113] The eighth transistor M8 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the eighth transistor M8 is coupled to a tenth node N10, the first terminal of the eighth transistor M8 is coupled to a ground voltage VSS, and the second terminal of the eighth transistor M8 is coupled to the tenth node N10 to receive a lower bridge current IG. In some embodiments, the pulse width modulation controller 200 further includes a lower bridge current source 250, which can output the aforementioned lower bridge current IG to the tenth node N10. For example, the lower bridge current source 250 may represent a related lower bridge circuit, the circuit structure of which is not particularly limited in this invention. The ninth transistor M9 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the ninth transistor M9 is coupled to the tenth node N10, the first terminal of the ninth transistor M9 is coupled to ground potential VSS, and the second terminal of the ninth transistor M9 is coupled to an eleventh node N11.

[0114] The tenth transistor M10 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the tenth transistor M10 is coupled to the eleventh node N11, the first terminal of the tenth transistor M10 is coupled to a supply voltage VDD, and the second terminal of the tenth transistor M10 is coupled to the eleventh node N11. The first switch 222 has a first terminal and a second terminal. The first terminal of the first switch 222 is coupled to the eleventh node N11, and the second terminal of the first switch 222 is coupled to a twelfth node N12. The first switch 222 can be selectively turned on or off according to a first control voltage VC1. For example, if the first control potential VC1 is at a high logic level, the first switch 222 will be turned on; conversely, if the first control potential VC1 is at a low logic level, the first switch 222 will be turned off. The capacitor CM has a first terminal and a second terminal, wherein the first terminal of the capacitor CM is coupled to the supply potential VDD, and the second terminal of the capacitor CM is coupled to the twelfth node N12.

[0115] The eleventh transistor M11 has a control terminal (e.g., a gate), a first terminal (e.g., a source), and a second terminal (e.g., a drain). The control terminal of the eleventh transistor M11 is coupled to the twelfth node N12, the first terminal of the eleventh transistor M11 is coupled to the supply potential VDD, and the second terminal of the eleventh transistor M11 is coupled to a second adder node ND2 to output a fourth current ID. The second switch 224 has a first terminal and a second terminal. The first terminal of the second switch 224 is coupled to the twelfth node N12, and the second terminal of the second switch 224 is coupled to a thirteenth node N13. The second switch 224 can be selectively turned on or off according to a second control potential VC2. For example, if the second control potential VC2 is a high logic level, the second switch 224 will be turned on; conversely, if the second control potential VC2 is a low logic level, the second switch 224 will be turned off.

[0116] For example, the first control potential VC1 and the second control potential VC2 may originate from a lower bridge driver and an upper bridge driver (not shown), respectively. In some embodiments, the first control potential VC1 and the second control potential VC2 may have substantially complementary logic levels, such that one of the first switch 222 and the second switch 224 is in a conducting state, while the other of the first switch 222 and the second switch 224 is in a de-conducting state. However, the invention is not limited thereto. In other embodiments, the first control potential VC1 and the second control potential VC2 may both be at low logic levels, such that both the first switch 222 and the second switch 224 are simultaneously de-conducting.

[0117] The voltage-to-current converter 230 includes a comparison circuit 232, a dependent current sink 234, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0118] The first resistor R1 has a first terminal and a second terminal, wherein the first terminal of the first resistor R1 is coupled to the input node NIN to receive the input potential VIN, and the second terminal of the first resistor R1 is coupled to a fourteenth node N14. The second resistor R2 has a first terminal and a second terminal, wherein the first terminal of the second resistor R2 is coupled to the fourteenth node N14, and the second terminal of the second resistor R2 is coupled to ground potential VSS. The third resistor R3 has a first terminal and a second terminal, wherein the first terminal of the third resistor R3 is coupled to the output node NOUT to receive the output potential VOUT, and the second terminal of the third resistor R3 is coupled to a fifteenth node N15. The fourth resistor R4 has a first terminal and a second terminal, wherein the first terminal of the fourth resistor R4 is coupled to the fifteenth node N15, and the second terminal of the fourth resistor R4 is coupled to ground potential VSS. In some embodiments, the resistance ratio (R1 / R2) of the first resistor R1 to the second resistor R2 can be approximately equal to the resistance ratio (R3 / R4) of the third resistor R3 to the fourth resistor R4. For example, the aforementioned resistance ratios (R1 / R2 or R3 / R4) can both be equal to 14, but are not limited thereto.

[0119] Comparator circuit 232 has a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of comparator circuit 232 is coupled to the fourteenth node N14, the negative input terminal of comparator circuit 232 is coupled to the fifteenth node N15, and the output terminal of comparator circuit 232 is used to output a third control potential VC3. Dependent current sink 234 can draw a third current IC from the thirteenth node N13 according to the third control potential VC3. In some embodiments, the third current IC is approximately proportional to a voltage difference between the input potential VIN and the output potential VOUT. That is, the combination of comparator circuit 232 and dependent current sink 234 can be regarded as an equivalent transconductance amplifier. However, the specific implementation of comparator circuit 232 and dependent current sink 234 is not particularly limited in this invention.

[0120] Finally, the current adder 240 can receive the second current IB from the first adder node ND1 and the fourth current ID from the second adder node ND2, and then add the two to generate a total current IS (that is, IS = IB + ID).

[0121] Figure 3 This diagram displays a potential waveform of a pulse width modulation controller 200 according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents voltage level. Figure 3 In this embodiment, the first control potential VC1 can also be considered as a lower bridge drive potential VLG, which has complementary logic levels to an upper bridge drive potential VUG. Furthermore, the second control potential VC2 has approximately the same waveform as the upper bridge drive potential VUG, except that the second control potential VC2 has a slight phase delay compared to the upper bridge drive potential VUG. Please refer to [the relevant documentation / reference]. Figure 2 , Figure 3 To understand the operating principle of the pulse width modulation controller 200.

[0122] During a first operation phase T1, the first control potential VC1 is at a high logic level and the second control potential VC2 is at a low logic level, causing the first switch 222 to be turned on and the second switch 224 to be turned off. At this time, because of the first current mirror formed by the eighth transistor M8 and the ninth transistor M9 and the second current mirror formed by the tenth transistor M10 and the eleventh transistor M11, a related information IF of the lower bridge current IG can be recorded as a capacitor potential VF at the twelfth node N12.

[0123] During the second operation phase T2, both the first control potential VC1 and the second control potential VC2 are at low logic levels, causing both the first switch 222 and the second switch 224 to disconnect simultaneously. At this time, the aforementioned capacitor potential VF can be maintained and stored in the capacitor CM. It must be noted that the duration of the second operation phase T2 is very short.

[0124] During a third operation phase T3, the first control potential VC1 is at a low logic level and the second control potential VC2 is at a high logic level, causing the first switch 222 to turn off and the second switch 224 to turn on, wherein the second control potential VC2 provides a high logic duration TON. During this high logic duration TON, the dependent current absorber 234 can draw a third current IC from the capacitor CM via the turned-on second switch 224 and discharge it for the capacitor potential VF. As the capacitor potential VF gradually decreases, the fourth current I4 from the eleventh transistor M11 will gradually increase. In some embodiments, the operating principle of the pulse width modulation controller 200 can be described by the following equations (1) to (7):

[0125]

[0126] Where “R1” represents the resistance of the first resistor R1, “R2” represents the resistance of the second resistor R2, “R3” represents the resistance of the third resistor R3, “R4” represents the resistance of the fourth resistor R4, and “DF” represents the voltage divider ratio of the voltage-to-current converter 230.

[0127] IC=(VIN-VOUT)·DF·Gm……………………(2)

[0128] Where “IC” represents the current value of the third current IC, “VIN” represents the potential level of the input potential VIN, “VOUT” represents the potential level of the output potential VOUT, and “Gm” represents the common transconductance of the comparator circuit 232 and the dependent current absorber 234.

[0129]

[0130] Where “ΔV” represents the voltage drop caused by the discharge operation of the third current IC, “TON” represents the high logic duration TON of the second control potential VC2, and “CM” represents the capacitance of the capacitor CM.

[0131]

[0132]

[0133] Where “ID0” represents an initial current value of the fourth current ID, and “gm” represents a small-signal transduction value of the eleventh transistor M11.

[0134]

[0135] Where “IA0” represents the initial current value of the first current IA, and “LM” represents the inductance value of the inductor LM.

[0136]

[0137] Where “IB” represents the current value of the second current IB, and “DS” represents the ratio of the second current IB to the first current IA.

[0138] According to equations (1) to (7), both the second current IB and the fourth current ID are related to the potential difference between the input potential VIN and the output potential VOUT. It should be noted that the current simulator 220 has a simpler structure and a shorter response time compared to the current detector 210. Therefore, when the second current IB of the current detector 210 has not yet reached a steady state, the fourth current ID of the current simulator 220 can be used to replace the second current IB and provide similar current information, thereby suppressing the output distortion of the pulse width modulation controller 200.

[0139] In some embodiments, if the following equation (8) is further assumed, the second current IB and the fourth current ID will be completely equal, and the relationship between the above component parameters can be further simplified to the following equation (9):

[0140]

[0141] CM=L·DF·DS·gm……………………(9)

[0142] For example, based on equations (8) and (9), the capacitance of capacitor CM can be set to 16.45pF, the inductance of inductor LM can be set to 1.5μH, the voltage divider ratio DF can be set to 0.0667, the current ratio DS can be set to 32577, and the small-signal transduction value gm of the eleventh transistor M11 can be set to 0.4mA / V, but it is not limited to these.

[0143] Figure 4 This diagram displays the current waveform of a pulse width modulation controller 200 according to an embodiment of the present invention, where the horizontal axis represents time and the vertical axis represents the current magnitude. Figure 4 The measurement results show that regardless of the variation of the first current IA, the second current IB and the fourth current ID both exhibit similar waveforms, with the phase of the fourth current ID even leading the phase of the second current IB. It is important to understand that the fourth current ID can be considered a pseudo-lower-gate current, which can be used to provide more immediate current information.

[0144] Figure 5 This diagram shows a flowchart of a pulse width modulation (PWM) control method according to an embodiment of the present invention. The aforementioned control method includes the following steps: In step S510, a first current is detected, and a second current is generated based on the first current. In step S520, relevant information about the lower bridge current is obtained using a current simulator. In step S530, a third current is drawn from the current simulator based on an input potential and an output potential. In step S540, a fourth current is generated using the current simulator based on the relevant information and the third current. In step S550, the second current and the fourth current are added to generate a sum current. It must be understood that the above steps do not need to be performed sequentially, but... Figures 1-4 Each feature of the embodiments can be applied to Figure 5 Among the control methods.

[0145] This invention proposes a novel pulse width modulation (PWM) controller and its control method. Compared with traditional designs, this invention has advantages such as shortening transient response time, suppressing output distortion, and improving overall linearity, making it well-suited for application in various electronic devices.

[0146] It is worth noting that the potential, current, resistance, inductance, capacitance, and other component parameters mentioned above are not limiting conditions of this invention. Designers can adjust these settings according to different needs. The pulse width modulation controller and control method of this invention are not limited to... Figures 1-5 The state shown. This invention may include only... Figures 1-5 Any one or more features of any one or more embodiments. In other words, not all illustrated features need to be implemented simultaneously in the pulse width modulation controller and control method of the present invention. Although the embodiments of the present invention use metal-oxide-semiconductor field-effect transistors as examples, the present invention is not limited thereto. Those skilled in the art can use other types of transistors, such as junction field-effect transistors or fin field-effect transistors, without affecting the effects of the present invention.

[0147] The method, or a specific form or part thereof, of the present invention may exist in the form of code. The code may be contained in physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or may be a computer program product, not limited to an external form, wherein when the code is loaded and executed by a machine, such as a computer, that machine becomes an apparatus for participating in the present invention. The code may also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method, wherein when the code is received, loaded, and executed by a machine, such as a computer, that machine becomes an apparatus for participating in the present invention. When implemented in a general-purpose processing unit, the code, combined with the processing unit, provides a unique apparatus that operates similarly to application-specific logic circuitry.

[0148] The ordinal numbers in this specification and the claims, such as "first", "second", "third", etc., are not sequential in any way; they are only used to distinguish between two different elements with the same name.

[0149] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the scope of the invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended claims.

Claims

1. A pulse width modulation controller, characterized in that, include: A current detector detects a first current and generates a second current based on the first current, wherein the current detector further receives an input potential and outputs an output potential; A current simulator is used to obtain relevant information about the lower bridge current. A voltage-to-current converter draws a third current from a current simulator based on the input potential and the output potential, wherein the current simulator further generates a fourth current based on the relevant information and the third current; as well as A current adder adds the second current to the fourth current to produce a sum current.

2. The pulse width modulation controller as described in claim 1, characterized in that, The second current is proportional to the first current.

3. The pulse width modulation controller as described in claim 1, characterized in that, The fourth current approaches the second current.

4. The pulse width modulation controller as described in claim 1, characterized in that, The current detector includes: A first transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor is coupled to a first node, the first terminal of the first transistor is coupled to an input node to receive the input potential, and the second terminal of the first transistor is coupled to a second node. An inductor having a first terminal and a second terminal, wherein the first terminal of the inductor is coupled to the second node, and the second terminal of the inductor is coupled to an output node to output the output potential; A second transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the second transistor is coupled to the first node, the first terminal of the second transistor is coupled to a third node, and the second terminal of the second transistor is coupled to the input node; and A third transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the third transistor is coupled to the first node, the first terminal of the third transistor is coupled to a fourth node, and the second terminal of the third transistor is coupled to the second node. The first current flows through the first transistor.

5. The pulse width modulation controller as described in claim 4, characterized in that, The current detector further includes: A fourth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fourth transistor is coupled to a fifth node, the first terminal of the fourth transistor is coupled to a third node, and the second terminal of the fourth transistor is coupled to the fifth node; and A fifth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the fifth transistor is coupled to the fifth node, the first terminal of the fifth transistor is coupled to the fourth node, and the second terminal of the fifth transistor is coupled to a sixth node.

6. The pulse width modulation controller as described in claim 5, characterized in that, The current detector further includes: A sixth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the sixth transistor is coupled to a seventh node, the first terminal of the sixth transistor is coupled to a fifth node, and the second terminal of the sixth transistor is coupled to an eighth node; and A seventh transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the seventh transistor is coupled to the seventh node, the first terminal of the seventh transistor is coupled to the sixth node, and the second terminal of the seventh transistor is coupled to a ninth node.

7. The pulse width modulation controller as described in claim 6, characterized in that, The current detector further includes: An output transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the output transistor is coupled to the sixth node, the first terminal of the output transistor is coupled to the third node, and the second terminal of the output transistor is coupled to a first adder node to output the second current. A first current sink draws a first bias current from the eighth node; and A second current absorber draws a second bias current from the ninth node, wherein the second bias current is equal to the first bias current.

8. The pulse width modulation controller as described in claim 4, characterized in that, The first transistor, the second transistor, and the third transistor are each an N-type metal-oxide-semiconductor field-effect transistor.

9. The pulse width modulation controller as described in claim 7, characterized in that, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the output transistor are each a P-type metal-oxide-semiconductor field-effect transistor.

10. The pulse width modulation controller as described in claim 1, characterized in that, This current simulator includes: An eighth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eighth transistor is coupled to a tenth node, the first terminal of the eighth transistor is coupled to a ground potential, and the second terminal of the eighth transistor is coupled to the tenth node to receive the lower bridge current; and A ninth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the ninth transistor is coupled to the tenth node, the first terminal of the ninth transistor is coupled to the ground potential, and the second terminal of the ninth transistor is coupled to an eleventh node.

11. The pulse width modulation controller as described in claim 10, characterized in that, This current simulator further includes: A tenth transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the tenth transistor is coupled to the eleventh node, the first terminal of the tenth transistor is coupled to a supply potential, and the second terminal of the tenth transistor is coupled to the eleventh node. A first switch having a first terminal and a second terminal, wherein the first terminal of the first switch is coupled to the eleventh node, and the second terminal of the first switch is coupled to a twelfth node; and A capacitor having a first terminal and a second terminal, wherein the first terminal of the capacitor is coupled to the supply potential, and the second terminal of the capacitor is coupled to the twelfth node.

12. The pulse width modulation controller as described in claim 11, characterized in that, This current simulator further includes: An eleventh transistor has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the eleventh transistor is coupled to the twelfth node, the first terminal of the eleventh transistor is coupled to the supply potential, and the second terminal of the eleventh transistor is coupled to a second adder node to output the fourth current; and A second switch has a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the twelfth node, and the second terminal of the second switch is coupled to a thirteenth node.

13. The pulse width modulation controller as described in claim 10, characterized in that, The eighth transistor and the ninth transistor are each an N-type metal-oxide-semiconductor field-effect transistor.

14. The pulse width modulation controller as described in claim 12, characterized in that, The tenth transistor and the eleventh transistor are each a P-type metal-oxide-semiconductor field-effect transistor.

15. The pulse width modulation controller as described in claim 12, characterized in that, The first switch selectively turns on or off based on a first control potential, while the second switch selectively turns on or off based on a second control potential.

16. The pulse width modulation controller as described in claim 15, characterized in that, The first control potential and the second control potential have complementary logic levels.

17. The pulse width modulation controller as described in claim 12, characterized in that, The voltage-to-current converter includes: A first resistor having a first terminal and a second terminal, wherein the first terminal of the first resistor is used to receive the input potential, and the second terminal of the first resistor is coupled to a fourteenth node; and A second resistor having a first end and a second end, wherein the first end of the second resistor is coupled to the fourteenth node, and the second end of the second resistor is coupled to the ground potential.

18. The pulse width modulation controller as described in claim 17, characterized in that, This voltage-to-current converter further includes: A third resistor has a first terminal and a second terminal, wherein the first terminal of the third resistor is used to receive the output potential, and the second terminal of the third resistor is coupled to a fifteenth node; and A fourth resistor has a first terminal and a second terminal, wherein the first terminal of the fourth resistor is coupled to the fifteenth node, and the second terminal of the fourth resistor is coupled to the ground potential.

19. The pulse width modulation controller as described in claim 18, characterized in that, This voltage-to-current converter further includes: A comparator circuit has a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the comparator circuit is coupled to the fourteenth node, the negative input terminal of the comparator circuit is coupled to the fifteenth node, and the output terminal of the comparator circuit is used to output a third control potential; and A phase-dependent current absorber draws a third current from the thirteenth node according to the third control potential, wherein the third current is proportional to a potential difference between the input potential and the output potential.

20. A method for controlling pulse width modulation, characterized in that, Includes the following steps: A first current is detected, and a second current is generated based on the first current; Using a current simulator, information related to one of the lower bridge currents is obtained; A third current is drawn from the current simulator based on an input potential and an output potential; Using this current simulator, a fourth current is generated based on the relevant information and the third current; as well as The second current is added to the fourth current to produce a sum current.

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