DC-DC converter topology and control method with differential power handling capability

Abstract

This invention belongs to the field of power electronic conversion technology, and relates to a DC-DC converter topology and control method with differential power handling capability. It includes an input capacitor bank, a photovoltaic array connected to a three-port DC-DC converter switch with integrated dual flying capacitors after passing through the input capacitor bank, and the three-port DC-DC converter switch with integrated dual flying capacitors connected to an output capacitor bank after passing through a transformer and a switch bank. This invention simplifies the overall complexity and cost of distributed photovoltaic power generation systems by using a single module to achieve MPPT control of multiple photovoltaic modules, and reduces the voltage stress on the switching devices in the module by employing a multi-level approach. Simultaneously, the integration of the switching devices reduces the number of switching devices, allowing the use of lower voltage level devices, further reducing costs. It also achieves zero-voltage turn-on for all switching devices, improving the efficiency of solar energy harvesting under conditions of uneven input power in the photovoltaic array.

Description

Technical Field

[0001] This invention belongs to the field of power electronic conversion technology, and particularly relates to a DC-DC converter topology and control method with differential power processing capability. Background Technology

[0002] A key characteristic of distributed photovoltaic (PV) power generation systems is achieving the maximum power output of the PV array. When the PV modules in a PV array are exposed to different environmental conditions, such as differences in irradiance levels or operating temperatures, each module will exhibit mismatched power-to-voltage (IU) characteristics. Since PV modules are typically connected in series to achieve higher voltage output, the current in each PV module is the same, which leads to multiple local power maxima (PUs) in the PU characteristics of a PV array composed of multiple PV modules. However, even though the PV array operates at a local PU, this does not mean that each PV module operates at its own maximum power point. Therefore, the mismatch in the operating characteristics of the PV modules will significantly reduce the power output of the PV array. As the number of modules connected in series increases, the mismatch problem caused by environmental differences becomes more severe.

[0003] To address the power mismatch issue among multiple photovoltaic (PV) modules, the primary solution currently involves an Input Independent Output Series (IIOS) structure combined with a power balancing unit. This approach uses a submodule for each PV module to achieve MPPT (Multi-Level Testing) control, with the output boosted via a series connection. Finally, the power balancing unit manages power flow between adjacent submodules to eliminate voltage inconsistencies caused by power mismatch. The advantage of this method is its ability to precisely control the operating status of each PV module, and the fact that the switching devices in each submodule handle the voltage level of a single PV module, simplifying submodule design. However, this approach uses too many submodules, significantly increasing system complexity and cost. Furthermore, the coordination between multiple modules and between submodules and multiple power balancing units increases the difficulty of control. A better solution is to control the operating status of multiple PV modules using a single module, thereby reducing system complexity, improving efficiency, and lowering overall cost. However, since a single module handles the voltage level of the entire series-connected PV module, designing the single module becomes extremely challenging. Summary of the Invention

[0004] The purpose of this invention is to achieve MPPT control of multiple photovoltaic modules using a single module, simplifying the overall complexity and cost of distributed photovoltaic power generation systems, and reducing voltage stress on switching devices in the module by adopting a multi-level approach. Simultaneously, the integration of switching transistors reduces the number of transistors, further decreasing the overall system complexity and cost.

[0005] This invention provides a DC-DC converter topology with differential power processing capability, including an input capacitor bank, a photovoltaic array connected to a three-port DC-DC converter switch with integrated dual flying capacitors after passing through the input capacitor bank; and the three-port DC-DC converter switch with integrated dual flying capacitors connected to the output capacitor bank after passing through a transformer and a switch bank.

[0006] Preferably, the photovoltaic array includes a first photovoltaic array PV#1 and a second photovoltaic array PV#2, and the three-port DC-DC converter with integrated dual flying capacitors includes a first main switch. S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4. First auxiliary switch tube S d2 Second auxiliary switch tube S d3 Flying capacitor C f and series inductors L s ;

[0007] The transformer turns ratio is K 1. The input capacitor bank includes the first input capacitor. C i1 Second input capacitor C i2 and auxiliary inductor L b The switch group includes the fifth main switch transistor. S 5 and the sixth main switch transistor S 6. First output capacitor of the output capacitor bank C o1 Second output capacitor C o2 .

[0008] Preferably, the positive electrode of the first photovoltaic array PV#1 is connected to the first input capacitor. C i1 The positive terminal, the first switching transistor S The drain of the first photovoltaic array PV#1 is connected to the auxiliary inductor; the negative terminal of the first photovoltaic array PV#1 is connected to the auxiliary inductor. L b One end of the first input capacitor is connected to the positive terminal of the second photovoltaic array PV#2; the first input capacitor is connected to the positive terminal of the second photovoltaic array PV#2. C i1 The negative terminal is connected to one end of the primary side of the transformer and the second input capacitor. C i2 The positive terminal of the first photovoltaic array is connected to the second input capacitor; the negative terminal of the second photovoltaic array PV#2 is connected to the second input capacitor. C i2The negative terminal, the fourth switching transistor S The source of 4 is connected.

[0009] Preferably, the first auxiliary switch transistor S d2 The drain of the first main switch transistor S The source of 1, the second main switch transistor S The flying capacitor with the drain of 2 C f One end is connected; the first auxiliary switch tube S d2 The source and the auxiliary inductor L b One end, the second auxiliary switch tube S d3 The drains of the second auxiliary switch are connected; S d3 The source and the flying capacitor C f One end of the third main switch transistor S The source of 3, the fourth main switch transistor S The drains of transistor 4 are connected; the second main switch transistor S The source of 2 and the series inductor L s One end of the third main switch transistor S The drains of 3 are connected; the series inductor L s The other end is connected to one end of the primary side of the transformer;

[0010] The secondary side of the transformer and the fifth main switch tube S The source of 5, the sixth main switch transistor S The drain of 6 is connected; the fifth main switch transistor S The drain of 5 and the first output capacitor C o1 The positive terminal of the transistor is connected to the positive terminal of the DC bus; the sixth main switch transistor... S The source of 6 and the second output capacitor C o2 The negative terminal of the capacitor is connected to the negative terminal of the DC bus; the first output capacitor C o1 The negative terminal is connected to one end of the secondary side of the transformer and the second output capacitor. C o2 The positive terminals are connected.

[0011] Preferably, the first auxiliary switch transistor S d2 With the second auxiliary switch Sd3 Complementary conduction with a certain dead zone; the first main switch transistor S 1 and the fourth main switch transistor S 4. Complementary conduction with a certain dead zone; the second main switch transistor S 2 and the third main switch tube S 3. Complementary conduction with a certain dead zone; the fifth main switch transistor S 5 and the sixth main switch transistor S 6. Complementary conduction with a certain dead zone.

[0012] A control method applicable to DC-DC converter topologies with differential power handling capability, by controlling the first main switch transistor. S 1. Fourth main switch transistor S 4 and the fifth main switch transistor S 5. Sixth main switch transistor S The phase shift angle between 6 intervals controls the converter's power transmission, specifically:

[0013] Auxiliary Inductor L b The current on the series inductor L s All currents will flow through the flying capacitor. C f By changing the first main switch transistor S 1. The fourth main switch transistor S 4 and the second main switch transistor S 2. The third main switch transistor S Phase shift angle between 3 φ Capable of controlling the flying capacitor C f The current on the capacitor thus enables the flying capacitor to... C f Voltage control; by controlling the flying capacitor C f voltage on V Cf If the sum of the voltages at the terminals of the first photovoltaic array PV#1 and the second photovoltaic array PV#2, which are connected in series, is controlled to be half, then the first auxiliary switch transistor can be made to... S d2 The second auxiliary switch tube S d3 The first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S 4. The voltage stresses on all voltage plates are equal and are half of the total input voltage.

[0014] Preferably, the auxiliary inductor L b This provides an additional current path for the first photovoltaic array PV#1 and the second photovoltaic array PV#2 connected in series to eliminate the current clamping effect caused by the series structure; assuming the auxiliary inductor L b Average current i Lb_ave The direction is determined by the auxiliary inductor. L b The current flows from the left end to the right end, and the current relationship between the first photovoltaic array PV#1 and the second photovoltaic array PV#2 can be obtained by the following formula:

[0015]

[0016] in i pv1 This refers to the output current of the first photovoltaic array PV#1. i pv2 This is the output current of the second photovoltaic array PV#2.

[0017] Preferably, the first auxiliary switch transistor is adjusted. S d2 and the second auxiliary switch S d3 The duty cycle can achieve the auxiliary inductor L b Average current i Lb_ave Control; through control i Lb_ave The conditions for the first photovoltaic array PV#1 and the second photovoltaic array PV#2 to operate at their respective maximum power are met, thereby enabling all photovoltaic arrays to still operate in MPPT state when there is a power mismatch between the first photovoltaic array PV#1 and the second photovoltaic array PV#2; auxiliary inductor L b Average current i Lb_ave It can be expressed by the following formula:

[0018]

[0019] in I Lbmax For the auxiliary inductor L b The maximum value of the current. T s For the switching cycle, D The first auxiliary switch Sd2 The duty cycle of the conduction, V pv1 The output voltage of the first photovoltaic array PV#1 V pv2 This is the output voltage of the second photovoltaic array PV#2.

[0020] Preferably, the first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S 4 and the flying capacitor C f This constitutes a flying capacitor three-level structure; the first main switch transistor S 1. The first auxiliary switch transistor S d2 The second auxiliary switch tube S d3 The fourth main switch transistor S 4 and the flying capacitor C f This constitutes another flying capacitor three-level structure; this double flying capacitor structure reduces the voltage stress on each switching device on the primary side of the transformer, enabling the use of lower voltage level and better performance switching transistors to achieve power transmission of the photovoltaic array output; the voltage borne by each switching device on the primary side of the transformer can be expressed by the following formula:

[0021]

[0022] in V S1 The first main switch transistor S 1. Voltage between drain and source V S2 The second main switch transistor S 2. Voltage between drain and source V S3 The third main switch transistor S 3. Voltage between drain and source V S4 The fourth main switch transistor S 4. Voltage between drain and source V Sd2 The first auxiliary switch S d2 The voltage between the drain and source, V Sd3 The second main switch transistor S d3 The voltage between the drain and source, V CfThe voltage across the flying capacitor is denoted as .

[0023] Preferably, the auxiliary inductor L b The conditions that need to be met are expressed by the following formula:

[0024]

[0025] The series inductor L s The current can assist the first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S The fifth main switch transistor described in section 4 S 5 and the sixth main switch transistor S ZVS 6.

[0026] The method of this invention has the following significant effects: 1. The three-port DC-DC converter topology with integrated dual flying capacitors proposed in this invention can enable each photovoltaic module to operate at its own maximum power point when there is power mismatch among multiple photovoltaic modules, thereby improving the photovoltaic output efficiency; 2. The three-port DC-DC converter topology with integrated dual flying capacitors proposed in this invention reduces the number of switching transistors by adopting integrated switching transistors and a multi-level structure with dual flying capacitors, and the voltage stress they bear is reduced to half of the total input voltage, thus reducing the difficulty of design; 3. The three-port DC-DC converter topology with integrated dual flying capacitors proposed in this invention can achieve ZVS for all switching transistors, reduce the switching losses of the switching transistors, and make the converter highly efficient. Attached Figure Description

[0027] Figure 1 This is a topology diagram of a three-port DC-DC converter with integrated dual flying capacitors disclosed in this invention;

[0028] Figure 2(a) shows the integration process of the switching transistor of the three-port DC-DC converter with integrated dual flying capacitors (topology diagram before integration).

[0029] Figure 2(b) shows the integration process of the switching transistor of the three-port DC-DC converter with integrated dual flying capacitors (topology diagram after integration).

[0030] Figure 3 This is a block diagram of a typical circuit control strategy of the present invention;

[0031] Figure 4 The waveforms are typical steady-state operating waveforms of the circuit in this invention.

[0032] Figures 5(a) to 5(b) are equivalent circuit diagrams of each stage of the typical circuit of the present invention; wherein Figure 5(a) shows the equivalent circuit diagram of the typical circuit of the present invention. t 0~ t The equivalent circuit diagram for stage 1 is shown in Figure 5(b). t 1~ t The equivalent circuit diagram for the two stages is shown in Figure 5(c). t 2~ t The equivalent circuit diagram for the three stages is shown in Figure 5(d). t 3~ t The equivalent circuit diagram for the four stages is shown in Figure 5(e). t 4~ t The equivalent circuit diagram for the 5 stages is shown in Figure 5(f). t 5~ t The equivalent circuit diagram for the 6 stages is shown in Figure 5(g). t 6~ t 7-stage equivalent circuit diagram;

[0033] Figure 6 The simulation waveform diagram of the present invention is shown when the light intensity of the first photovoltaic array PV#1 and the second photovoltaic array PV#2 remains unchanged.

[0034] Figure 7 The simulation waveform diagram of the present invention is shown when the light intensity of the first photovoltaic array PV#1 remains unchanged while the light intensity of the second photovoltaic array PV#2 decreases.

[0035] Figure 8 The simulation waveform diagram of the present invention is shown when the light intensity of both the first photovoltaic array PV#1 and the second photovoltaic array PV#2 is reduced. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be noted that these embodiments are only for illustration and explanation of the present invention and are not intended to limit the scope of protection of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0037] Example

[0038] Figure 1 The diagram shows a three-port DC-DC converter topology with integrated dual flying capacitors. It includes: a first photovoltaic array PV#1, a second photovoltaic array PV#2, and a first input capacitor. C i1 Second input capacitor C i2 Auxiliary inductor L b First auxiliary switch tube S d2Second auxiliary switch tube S d3 Flying capacitor C f First main switch transistor S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4. Series inductor L s The turns ratio is K Transformer 1, fifth main switch transistor S 5. Sixth main switch transistor S 6. First output capacitor C o1 Second output capacitor C o2 and DC bus;

[0039] The positive terminal of the first photovoltaic array PV#1 and the first input capacitor C i1 The positive terminal, the first switching transistor S The drain of 1 is connected; the negative terminal of the first photovoltaic array PV#1 is connected to the auxiliary inductor. L b One end is connected to the positive terminal of the second photovoltaic array PV#2; the first input capacitor C i1 The negative terminal is connected to one end of the primary side of the transformer and the second input capacitor. C i2 The positive terminal of the first photovoltaic array is connected to the second input capacitor; the negative terminal of the second photovoltaic array PV#2 is connected to the second input capacitor. C i2 negative terminal, fourth switching transistor S The source of 4 is connected;

[0040] First auxiliary switch S d2 The drain of the first main switch transistor S The source of 1, the second main switch transistor S 2 drain flying capacitor C f One end is connected; the first auxiliary switch tube S d2 Source and auxiliary inductor L b One end, the second auxiliary switch tube S d3 The drains of the two transistors are connected; the second auxiliary switch transistor... S d3 The source and flying capacitor C f One end, the third main switch transistor S 3's source, the fourth main switch transistorS The drains of transistor 4 are connected; the second main switch transistor S 2's source and series inductor L s One end, the third main switch transistor S The drains of 3 are connected; series inductor L s The other end is connected to one end of the primary side of the transformer;

[0041] Transformer secondary side and fifth main switch tube S 5's source, the sixth main switch transistor S The drains of transistor 6 are connected; the fifth main switch transistor S 5's drain and the first output capacitor C o1 The positive terminal of the main switch is connected to the positive terminal of the DC bus; the sixth main switch transistor S The source of 6 and the second output capacitor C o2 The negative terminal of the capacitor is connected to the negative terminal of the DC bus; the first output capacitor C o1 The negative terminal is connected to one end of the transformer secondary side and the second output capacitor. C o2 The positive terminals are connected.

[0042] First auxiliary switch S d2 With the second auxiliary switch S d3 Complementary conduction with a certain dead zone; first main switch transistor S 1 and the fourth main switch transistor S 4. Complementary conduction with a certain dead zone; second main switch transistor S 2 and the third main switch tube S 3. Complementary conduction with a certain dead zone; fifth main switch transistor S 5 and the sixth main switch transistor S 6. Complementary conduction with a certain dead zone.

[0043] Figure 2 illustrates the integration process of the switching transistors in a three-port DC-DC converter with integrated dual flying capacitors disclosed in this invention. As shown in Figure 2, the first main switching transistor... S 1. First auxiliary switch tube S d2 Second auxiliary switch tube S d3 Fourth main switch tube S 4. Auxiliary inductor L b The auxiliary converter is composed of the first main switch transistor. S 1. Second main switch transistor S 2. Third main switch transistor S3. Fourth main switch transistor S 4. Flying capacitor C f The flying capacitor three-level converter is constructed by sharing the first main switch through the integration of switching transistors. S 1 and second main switch transistors S 4. At the same time, a dual-flying capacitor structure is formed to clamp the voltage, thereby reducing the voltage stress of all switching transistors.

[0044] Figure 3 The block diagram shows the control strategy employed in the three-port DC-DC converter topology with integrated dual flying capacitors provided by this invention. The first auxiliary switch is changed. S d2 Second auxiliary switch S d3 The duty cycle is adjusted to achieve maximum power tracking of the first photovoltaic array PV#1, and the fifth main switch is changed. S 5 and the sixth main switch transistor S A phase shift angle of 6 achieves maximum power tracking for the second photovoltaic array PV#2, and finally, the second main switch is changed. S 2 and the third main switch transistor S A phase shift angle of 3 enables flying capacitors C f voltage on V Cf Control.

[0045] When two photovoltaic modules are matched (having the same IU characteristics), the clamping effect of the series current allows the two photovoltaic modules to be combined into one, achieving maximum power point tracking. Therefore, the following analysis will take the case of mismatched photovoltaic modules (reduced light intensity of the second photovoltaic array PV#2) as an example to explain the various operating stages and ZVS implementation of each switch in the three-port DC-DC converter topology with integrated dual flying capacitors provided by this invention. Figure 4 This is the operating waveform of a three-port DC-DC converter topology with integrated dual flying capacitors under steady-state operating conditions.

[0046] 1. For example Figure 5a As shown, t 0~ t Phase 1:

[0047] Second auxiliary switch S d3 and the fourth main switch transistor S 4 in t Turn off at 0, in series inductor L s and auxiliary inductor L b Under the influence of iLs and i Lb It will not mutate and will maintain its original flow direction. i Ls and i Lb For the first main switch transistor S 1 and the first auxiliary switch tube S d2 The parasitic capacitance discharges until the voltage drops to zero, forcing the first main switch transistor to... S 1 and the first auxiliary switch tube S d2 The body diode is turned on, thereby realizing the first main switch transistor. S 1 and the first auxiliary switch tube S d2 ZVS condition. Dead time ends, first main switch transistor... S 1 and the first auxiliary switch tube S d2 Turn on. Second auxiliary switch tube. S d3 Second main switch transistor S The voltage stress of 2 is V Cf Fourth main switch tube S The voltage stress of 4 is V pv1 + V pv2 - V Cf The first photovoltaic array PV#1 is paired with an auxiliary inductor. L b Discharge, i Lb Linear decrease. 0.5 K × V bus For series inductors L s Charging, current i Ls Linear increase. (Settings) i Lb and i Ls initial state ( t 0=0) are respectively i Lb ( t 0) and i Ls ( t 0). Assuming the impact of dead time is negligible, this stage... i Lb ( t )and iLs ( t This can be represented as:

[0048] (1)

[0049] in V bus This is the DC bus voltage.

[0050] 2. For example Figure 5b As shown, t 1~ t Phase 2:

[0051] Third main switch transistor S 3 in t 1. Turn off, in series inductor L s Under the influence of i Ls For the second main switch transistor S The parasitic capacitance of transistor 2 discharges until the voltage drops to zero, forcing the second main switch transistor to... S The body diode of transistor 2 is turned on, thus realizing the second main switch. S ZVS condition 2. Dead time ends, second main switch transistor S 2. Turn on. Third main switch tube. S The voltage stress of 3 is V Cf The first photovoltaic array PV#1 still relies on the auxiliary inductor. L b Discharge, V pv1 + V pv2 +0.5 K × V bus For series inductors L s Charge. i Lb ( t )and i Ls ( t This can be represented as:

[0052] (2)

[0053] 3. For example Figure 5c As shown, t 2~ t Phase 3:

[0054] Sixth main switch transistor S 6 in t 2. When the transformer is turned off, the current in the secondary winding affects the fifth main switch transistor. SThe parasitic capacitance of transistor 5 discharges until the voltage drops to zero, forcing the fifth main switch transistor to discharge. S The fifth main switch is activated when the five diodes are turned on. S ZVS condition 5. Dead time ends, fifth main switch transistor S 5. Activation. During this phase, the first photovoltaic array PV#1 still relies on the auxiliary inductor. L b Discharge, V pv1 + V pv2 -0.5 K × V bus For series inductors L s Charge it. i Lb ( t )and i Ls ( t The expression for ) is:

[0055] (3)

[0056] 4. For example Figure 5d As shown, t 3~ t Phase 4:

[0057] First auxiliary switch S d2 exist t 3. Turn off, in the auxiliary inductor L b Under the impact, i Lb For the second auxiliary switch S d3 The parasitic capacitance discharges until the voltage drops to zero, forcing the second auxiliary switch to... S d3 The body diode is turned on, thereby realizing the second auxiliary switch. S d3 ZVS condition. Dead time ends, second auxiliary switch transistor S d3 Activated. First auxiliary switch tube. S d2 The voltage stress is V Cf The first photovoltaic array PV#1 and the flying capacitor C f Together with the auxiliary inductor L b Discharge, series inductor L s Still byV pv1 + V pv2 -0.5 K × V bus Charge. i Lb ( t )and i Ls ( t The expression for ) can be represented as:

[0058] (4)

[0059] 5. For example Figure 5e As shown, t 4~ t Phase 5:

[0060] First main switch transistor S 1 in t Turn off at 4 o'clock, fourth main switch tube S The process of achieving the zero-voltage switching condition in step 4 is similar to the previous voltage state. The first main switch transistor... S The voltage stress of 1 is V pv1 + V pv2 - V Cf The second photovoltaic array PV#2 has an auxiliary inductor. L b Charge, i Lb Linear increase. -0.5 K × V bus For series inductors L s Discharge, i Ls Linear decrease. i Lb ( t )and i Ls ( t The expression for ) is:

[0061] (5)

[0062] 6. For example Figure 5f As shown, t 5~ t Phase 6:

[0063] Second main switch transistor S 2 in t The third main switch is turned off at 5 o'clock. SThe process of achieving the ZVS condition in step 3 is similar to the previous stages. The second main switch... S The voltage stress of 2 is V Cf The second photovoltaic array PV#2 still relies on the auxiliary inductor. L b Charging, series inductor L s Depend on- V pv1 - V pv2 -0.5 K × V bus Discharge. i Lb ( t )and i Ls ( t The expression for ) is:

[0064] (6)

[0065] 7. For example Figure 5g As shown, t 6~ t 7 stages:

[0066] Fifth main switch tube S 5 in t The sixth main switch tube is turned off at 6 o'clock. S The ZVS condition fulfillment process for step 6 is similar to the previous stages. In this stage, the auxiliary inductor... L b Still charged by the second photovoltaic array PV#2, with a series inductor. L s Depend on- V pv1 - V pv2 +0.5 K × V bus Discharge. i Lb ( t )and i Ls ( t The expression for ) is:

[0067] (7)

[0068] For the transformer secondary side of the three-port DC-DC converter topology with integrated dual flying capacitors provided in this invention, when the fifth main switch transistor... S 5. Required to open i LsIf positive, when the sixth main switch transistor... S 6. Required to open i Ls Only when the voltage is negative can the transformer transfer energy to the DC bus, thus enabling the transmission of main power. Therefore, for a half-cycle ( t 2~ t 6) i Ls The waveform can be obtained within half a period using the average state-space method. i Ls average current value I Ls_ave Under steady state, the inductor in one switching cycle ( T S The average current within the range is zero; therefore, from equation (1) to equation (4), the instantaneous current can be obtained. I Ls ( t 0) I Ls ( t 1) I Ls ( t 2) I Ls ( t 4) is:

[0069] (8)

[0070] I Ls ( t 5) and I Ls ( t 6) Equal to - I Ls ( t 1) and - I Ls ( t 2). Therefore, the fifth main switch transistor... S 5. During the half-cycle of operation, the voltage on the secondary side of the transformer is transformed to the voltage on the primary side by 0.5. K × V bus With the time-domain expression of inductor current i Ls ( t Integrating and averaging the product of the products, we obtain the average main power. P o for:

[0071] (9)

[0072] As can be seen from equation (9), by controlling the first main switch transistor S1. Fourth main switch transistor S 4 and the fifth main switch transistor S 5. Sixth main switch transistor S A phase shift angle of 6° is sufficient to control the power transmission of the converter.

[0073] Next, we will analyze the power mismatch between the two photovoltaic arrays. Since the first photovoltaic array PV#1 and the second photovoltaic array PV#2 are connected in series, their currents have the following relationship:

[0074] (10)

[0075] If the light intensity of the second photovoltaic array PV#2 decreases, its current will decrease. i pv2 It will decrease. Because i pv1 and i pv2 Equal, therefore i pv1 This will decrease, leading to a reduction in the output power of the first photovoltaic array PV#1. Therefore, an additional current path is introduced to eliminate the current clamping problem caused by the series connection. At this time, the output current of the first photovoltaic array PV#1... i pv1 With the output current of the second photovoltaic array PV#2 i pv2 The relationship between them is:

[0076] (11)

[0077] According to the auxiliary inductor L b Current i Lb The time-domain expression can be obtained as follows:

[0078] (12)

[0079] Similarly, using the state-space averaging method, we can obtain... i Lb The expression for the average value is:

[0080] (13)

[0081] As can be seen from equation (12), adjusting the first auxiliary switch tube S d2 Second auxiliary switch S d3 The duty cycle can achieve auxiliary inductance L b Average current iLb_ave Control. Through control i Lb_ave The conditions for the first photovoltaic array PV#1 and the second photovoltaic array PV#2 to operate at their maximum power are met, thereby enabling all photovoltaic arrays to still operate in MPPT state when the output power of the first photovoltaic array PV#1 and the second photovoltaic array PV#2 is mismatched.

[0082] As can be seen from each steady-state operation stage, the first main switch transistor S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4 and flying capacitors C f This constitutes a three-level structure; the first main switch transistor S 1. First auxiliary switch tube S d2 Second auxiliary switch tube S d3 Fourth main switch tube S 4 and flying capacitors C f This forms another three-level structure; this double-flying capacitor structure reduces the voltage stress on the switching devices on the primary side of the transformer, enabling the use of lower voltage-level, higher-performance switching transistors to achieve power transmission from the photovoltaic array. The voltage across each switching device on the primary side of the transformer can be expressed by the following formula:

[0083] (14)

[0084] As can be seen from the above description of the power transfer principle, whether it is the transfer of mismatched power or the transfer of main power, the flying capacitor... C f The involvement of these components is unavoidable. This is because it requires utilizing the degree of freedom of the mismatch power (the first auxiliary switch). S d2 Second auxiliary switch tube S d3 The duty cycle is used to achieve maximum power point tracking for the first photovoltaic array PV#1, therefore it does not have a flying capacitor. C f voltage on V Cf The control capability. During the transmission of main power, by changing the first main switch transistor... S 1. Fourth main switch transistor S 4 and the second main switch transistor S 2. Third main switch transistor S The phase shift angle between the three phases can control the flying capacitor. Cf The current, thereby achieving the control V Cf Control. By using the flying capacitor C f voltage on V Cf If the voltage at the terminals of the first photovoltaic array PV#1 and the second photovoltaic array PV#2, which are connected in series, is controlled to be half the sum of their voltages, then the first auxiliary switch transistor can be made to... S d2 Second auxiliary switch tube S d3 First main switch transistor S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4. The voltage stresses on all voltage plates are equal and are half of the total input voltage.

[0085] According to equation (11), for the auxiliary inductor L b Make appropriate selections so that the flow through the auxiliary inductor L b The current can be both positive and negative, thus enabling the first auxiliary switching transistor. S d2 Second auxiliary switch S d3 ZVS. Auxiliary inductor L b The conditions that need to be met are expressed by the following formula:

[0086] (15)

[0087] Analysis of the above working stages shows that the series inductor L s The current can assist the first main switch transistor S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4. Fifth main switch transistor S 5 and the sixth main switch transistor S ZVS 6.

[0088] The proposed solution of this invention was verified using the PSIM simulation experimental platform. The simulation results are as follows: Figure 6 , Figure 7 and Figure 8 As shown. Each photovoltaic array has a rated power of 500W, a total power of 1000W, and an output DC bus voltage of 380V. Under normal circumstances, the output voltage of each photovoltaic array is 50V.

[0089] Figure 6 The diagram shows the simulation waveforms when the illumination intensity of the first photovoltaic array PV#1 and the second photovoltaic array PV#2 remains unchanged. It can be seen that each photovoltaic array can achieve MPPT tracking, and the voltage stress of each primary-side switch is equal and half of the total input voltage. All switches can achieve ZVS.

[0090] Figure 7 The diagram shows the simulated waveforms when the illumination intensity of the first photovoltaic array PV#1 remains unchanged while the illumination intensity of the second photovoltaic array PV#2 decreases. It can be seen that despite the difference in illumination intensity, each photovoltaic array operates at its maximum power point under its respective illumination intensity, enabling independent MPPT control. Simultaneously, the voltage stress on each primary-side switch is equal and half of the total input voltage. All switches achieve ZVS.

[0091] Figure 8 The diagram shows the simulated waveforms when the illumination intensity of both the first photovoltaic array PV#1 and the second photovoltaic array PV#2 decreases. It can be seen that even when the illumination intensity of each photovoltaic array decreases, their respective MPPT tracking can still be achieved. The voltage stress of each primary-side switch is equal and half of the total input voltage. All switches can achieve ZVS.

[0092] The simulation results show that the three-port DC-DC converter topology with integrated dual flying capacitors disclosed in this invention can enable each photovoltaic module to operate at its own maximum power point when there is power mismatch among multiple photovoltaic modules, thereby improving the photovoltaic output efficiency. The voltage stress borne by all primary-side switches is half of the total input voltage, reducing the difficulty of design. Furthermore, it can achieve ZVS for all switches, reducing the switching losses of the switches and making the converter highly efficient.

[0093] The above embodiments are preferred implementation examples of the present invention and are not intended to limit the ideas or implementation methods of the present invention. Any changes, modifications, equivalent substitutions, simplifications, improvements, etc., made without departing from the spirit and principle of the present invention should be considered equivalent substitutions and are included within the protection scope of the present invention.

Claims

1. A DC-DC converter topology with differential power handling capability, characterized in that, The photovoltaic array includes a first photovoltaic array PV#1 and a second photovoltaic array PV#2. The three-port DC-DC converter with integrated dual flying capacitors includes a first main switch. S 1. Second main switch transistor S 2. Third main switch transistor S 3. Fourth main switch transistor S 4. First auxiliary switch tube S d2 Second auxiliary switch tube S d3 Flying capacitor C f and series inductors L s ; The transformer turns ratio is K 1. The input capacitor bank includes the first input capacitor. C i1 Second input capacitor C i2 and auxiliary inductor L b The switch group includes the fifth main switch transistor. S 5 and the sixth main switch transistor S 6. First output capacitor of the output capacitor bank C o1 Second output capacitor C o2 ; The positive terminal of the first photovoltaic array PV#1 and the first input capacitor C i1 The positive terminal, the first main switch transistor S The drain of the first photovoltaic array PV#1 is connected to the auxiliary inductor; the negative terminal of the first photovoltaic array PV#1 is connected to the auxiliary inductor. L b One end of the first input capacitor is connected to the positive terminal of the second photovoltaic array PV#2; the first input capacitor is connected to the positive terminal of the second photovoltaic array PV#2. C i1 The negative terminal is connected to one end of the primary side of the transformer and the second input capacitor. C i2 The positive terminal of the first photovoltaic array is connected to the second input capacitor; the negative terminal of the second photovoltaic array PV#2 is connected to the second input capacitor. C i2 The negative terminal, the fourth main switch transistor S The source of 4 is connected; First auxiliary switch S d2 The drain of the first main switch transistor S The source of 1, the second main switch transistor S The flying capacitor with the drain of 2 C f One end is connected; the first auxiliary switch tube S d2 The source and the auxiliary inductor L b The other end, the second auxiliary switch tube S d3 The drains of the second auxiliary switch are connected; S d3 The source and the flying capacitor C f The other end, the third main switch transistor S The source of 3, the fourth main switch transistor S The drains of transistor 4 are connected; the second main switch transistor S The source of 2 and the series inductor L s One end of the third main switch transistor S The drains of 3 are connected; the series inductor L s The other end is connected to the other end of the primary side of the transformer; One end of the transformer secondary side is connected to the fifth main switch transistor. S The source of 5, the sixth main switch transistor S The drain of 6 is connected; the fifth main switch transistor S The drain of 5 and the first output capacitor C o1 The positive terminal of the transistor is connected to the positive terminal of the DC bus; the sixth main switch transistor S The source of 6 and the second output capacitor C o2 The negative terminal of the capacitor is connected to the negative terminal of the DC bus; the first output capacitor C o1 The negative terminal is connected to the other end of the secondary side of the transformer and the second output capacitor. C o2 The positive terminals are connected.

2. The DC-DC converter topology with differential power processing capability according to claim 1, characterized in that, First auxiliary switch S d2 With the second auxiliary switch S d3 Complementary conduction with a certain dead zone; the first main switch transistor S 1 and the fourth main switch transistor S 4. Complementary conduction with a certain dead zone; the second main switch transistor S 2 and the third main switch tube S 3. Complementary conduction with a certain dead zone; the fifth main switch transistor S 5 and the sixth main switch transistor S 6. Complementary conduction with a certain dead zone.

3. A control method applicable to the DC-DC converter topology with differential power processing capability as described in claim 2, characterized in that, By controlling the first main switch transistor S 1. Fourth main switch transistor S 4 and the fifth main switch transistor S 5. Sixth main switch transistor S The phase shift angle between 6 intervals controls the converter's power transmission, specifically: Auxiliary Inductor L b The current on the series inductor L s All currents will flow through the flying capacitor. C f By changing the first main switch transistor S 1. The fourth main switch transistor S 4 and the second main switch transistor S 2. The third main switch transistor S Phase shift angle between 3 f Capable of controlling the flying capacitor C f The current on the capacitor thus enables the flying capacitor to... C f Voltage control; by controlling the flying capacitor C f voltage on V Cf If the sum of the voltages at the terminals of the first photovoltaic array PV#1 and the second photovoltaic array PV#2, which are connected in series, is controlled to be half, then the first auxiliary switch transistor can be made to... S d2 The second auxiliary switch tube S d3 The first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S 4. The voltage stresses on all voltage plates are equal and are half of the total input voltage.

4. The control method according to claim 3, characterized in that, The auxiliary inductor L b This provides an additional current path for the first photovoltaic array PV#1 and the second photovoltaic array PV#2 connected in series to eliminate the current clamping effect caused by the series structure; assuming the auxiliary inductor L b Average current i Lb_ave The direction is determined by the auxiliary inductor. L b The current flows from the left end to the right end, and the current relationship between the first photovoltaic array PV#1 and the second photovoltaic array PV#2 can be obtained by the following formula: in i pv1 This refers to the output current of the first photovoltaic array PV#1. i pv2 This is the output current of the second photovoltaic array PV#2.

5. The control method according to claim 3, characterized in that, Adjust the first auxiliary switch tube S d2 and the second auxiliary switch S d3 The duty cycle can achieve the auxiliary inductor L b Average current i Lb_ave Control; through control i Lb_ave The conditions for the first photovoltaic array PV#1 and the second photovoltaic array PV#2 to operate at their respective maximum power are met, thereby enabling all photovoltaic arrays to still operate in MPPT state when there is a power mismatch between the first photovoltaic array PV#1 and the second photovoltaic array PV#2; auxiliary inductor L b Average current i Lb_ave It can be expressed by the following formula: in I Lbmax For the auxiliary inductor L b The maximum value of the current. T s For the switching cycle, D The first auxiliary switch S d2 The duty cycle of the conduction, V pv1 The output voltage of the first photovoltaic array PV#1 V pv2 This is the output voltage of the second photovoltaic array PV#2.

6. The control method according to claim 5, characterized in that, The first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S 4 and the flying capacitor C f This forms a three-level structure for the flying capacitor; The first main switch transistor S 1. The first auxiliary switch transistor S d2 The second auxiliary switch tube S d3 The fourth main switch transistor S 4 and the flying capacitor C f This constitutes another flying capacitor three-level structure; this double flying capacitor structure reduces the voltage stress on each switching device on the primary side of the transformer, enabling the use of lower voltage level and better performance switching transistors to achieve power transmission of the photovoltaic array output; the voltage borne by each switching device on the primary side of the transformer can be expressed by the following formula: in V S1 The first main switch transistor S 1. Voltage between drain and source V S2 The second main switch transistor S 2. Voltage between drain and source V S3 The third main switch transistor S 3. Voltage between drain and source V S4 The fourth main switch transistor S 4. Voltage between drain and source V Sd2 The first auxiliary switch S d2 The voltage between the drain and source, V Sd3 The second main switch transistor S d3 The voltage between the drain and source, V Cf The voltage across the flying capacitor is denoted as .

7. The control method according to claim 5, characterized in that, The auxiliary inductor L b The conditions that need to be met are expressed by the following formula: The series inductor L s The current can assist the first main switch transistor S 1. The second main switch transistor S 2. The third main switch transistor S 3. The fourth main switch transistor S The fifth main switch transistor described in section 4 S 5 and the sixth main switch transistor S 6 ZVS, of which, i pv1 This is the output current of the first photovoltaic array PV#1. i pv2 This is the output current of the second photovoltaic array PV#2.

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