Level shifter circuit and method of operation thereof

Abstract

The present disclosure relates to a level shifter circuit and a method of operation thereof. A circuit includes an input circuit, a level shifter circuit, and an output circuit. The input circuit is coupled to a first voltage source and configured to receive a first input signal and generate at least a second input signal or a third input signal. The level shifter circuit is coupled to the input circuit and a second voltage source and configured to receive a first enable signal, the second input signal, or the third input signal and generate a first signal in response to the first enable signal, the second input signal, or the third input signal. The level shifter circuit includes a head circuit coupled to a first node and configured to enable or disable the level shifter circuit in response to the first enable signal. The output circuit is coupled to at least the level shifter circuit and the second voltage source and configured to receive the first signal and generate an output signal.

Description

Technical Field

[0001] This disclosure relates to a level shifter circuit and its operation method. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to solve problems in many different fields. Some of these digital devices (such as level shifter circuits) are configured to enable circuits that can operate in different voltage domains. As ICs become smaller and more complex, the operating voltage of these digital devices continues to decrease, thus affecting IC performance. Summary of the Invention

[0003] According to one embodiment of this disclosure, an integrated circuit is provided, comprising: an input circuit coupled to a first voltage source and configured to receive a first input signal and generate at least a second input signal or a third input signal; a level shifter circuit coupled to at least the input circuit and a second voltage source different from the first voltage source and configured to receive at least a first enable signal, the second input signal, or the third input signal, and generate at least a first signal in response to at least the first enable signal, the second input signal, or the third input signal, the level shifter circuit comprising: a header circuit coupled to a first node of the level shifter circuit and configured to receive the first enable signal and configured to enable or disable the level shifter circuit in response to the first enable signal; and an output circuit coupled to at least the level shifter circuit and the second voltage source and configured to receive the first signal and generate at least an output signal.

[0004] According to another embodiment of this disclosure, an integrated circuit is provided, comprising: an input circuit coupled to a first voltage source and configured to receive a first input signal having a first voltage swing and generate at least a second input signal or a third input signal; a level shifter circuit coupled to at least the input circuit and a second voltage source different from the first voltage source and configured to generate at least a first signal in response to at least a first enable signal, the second input signal, or the third input signal, the first signal having a second voltage swing different from the first voltage swing, the level shifter circuit comprising: a first circuit coupled between the second voltage source and a first node of the level shifter circuit, the first circuit having a first threshold voltage; and a foot circuit coupled to the first node of the level shifter circuit, the foot circuit being configured to enable or disable the level shifter circuit in response to the first enable signal, the foot circuit having a second threshold voltage different from the first threshold voltage; and an output circuit coupled to at least the level shifter circuit and the second voltage source, the output circuit being configured to generate at least an output signal in response to the first signal.

[0005] According to another embodiment of this disclosure, a method of operating a circuit is provided, the method comprising: enabling a level shifter circuit in response to a first enable signal, wherein enabling the level shifter circuit comprises: enabling a first circuit in a first path or a second path of at least the level shifter circuit in response to at least the first enable signal, thereby electrically coupling the first path or the second path to a first voltage source or a first reference power supply; generating a first signal in response to at least a first input signal, the first input signal having a first voltage swing and the first signal having a second voltage swing different from the first voltage swing; disabling a second circuit in response to the first enable signal, the second circuit being coupled to a first output node of the level shifter circuit; and generating an output signal by an output circuit in response to at least the first enable signal or the first signal. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a block diagram of an integrated circuit according to some embodiments.

[0008] Figure 2 This is a circuit diagram of a circuit according to some embodiments.

[0009] Figures 3A-3D This is a schematic diagram of an integrated circuit according to some embodiments.

[0010] Figure 4 This is a circuit diagram of a circuit according to some embodiments.

[0011] Figures 5A-5B This is a flowchart of a method for operating circuits according to some embodiments.

[0012] Figure 6 This is a flowchart of a method for forming or manufacturing an integrated circuit according to some embodiments.

[0013] Figure 7 This is a flowchart of a method for generating an integrated circuit layout design according to some embodiments.

[0014] Figure 8 This is a schematic diagram of a system for designing IC layout and manufacturing IC circuits according to some embodiments.

[0015] Figure 9 This is a block diagram of an IC manufacturing system and an associated IC manufacturing process according to at least one embodiment of the present disclosure. Detailed Implementation

[0016] The following disclosure provides various embodiments or examples for implementing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "upper," etc.) may be used herein to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly.

[0018] According to some embodiments, the circuit includes an input circuit, a level shifter circuit, and an output circuit. In some embodiments, the input circuit is coupled to a first voltage source and configured to receive a first input signal. In some embodiments, the input circuit is further configured to generate at least a second or a third input signal. In some embodiments, the first input signal has a first voltage swing.

[0019] In some embodiments, the level shifter circuit is coupled at least to the input circuit and a second voltage source different from the first voltage source.

[0020] In some embodiments, the level shifter circuit is configured to receive at least a first enable signal, a second input signal, or a third input signal. In some embodiments, the level shifter circuit is configured to generate at least a first signal in response to at least the first enable signal, the second input signal, or the third input signal. In some embodiments, the first signal has a second voltage swing that is different from the first voltage swing.

[0021] In some embodiments, the level shifter circuit includes a header circuit coupled to a first node of the level shifter circuit. In some embodiments, the header circuit is configured to receive a first enable signal. In some embodiments, the header circuit is configured to enable or disable the level shifter circuit in response to the first enable signal.

[0022] In some embodiments, the output circuit is coupled at least to a level shifter circuit and a second voltage source, and is configured to receive a first signal and generate at least one output signal.

[0023] In some embodiments, the level shifter circuit further includes a first path and a second path. In some embodiments, the first path and the second path are enabled or disabled by a first enable signal. In some embodiments, the first path or the second path includes a head transistor. In some embodiments, by including a head circuit in the first path or the second path of the level shifter circuit, leakage current in the first path and the second path of the level shifter circuit is reduced or prevented in response to the level shifter circuit being disabled by the first enable signal, thereby resulting in lower power consumption than other methods.

[0024] Figure 1 This is a block diagram of an integrated circuit 100 according to some embodiments.

[0025] The integrated circuit 100 includes an input circuit 102, an enable circuit 104, a level shifter circuit 106, and an output circuit 108.

[0026] Input circuit 102 is coupled to a first input terminal of level shifter circuit 106. Input circuit 102 is configured to receive input signal IN and generate at least input signal IB or input signal IBB. Input signal IB is inverted compared to input signal IN. Input signal IBB is inverted compared to input signal IB. In some embodiments, input circuit 102 is configured to output one or more of input signal IN, input signal IB, or input signal IBB to level shifter circuit 106.

[0027] In some embodiments, the input circuit 102 is coupled to a first voltage source node 1N. In some embodiments, the first voltage source node 1N has a first supply voltage VDDL. Figure 2 and Figure 4 Therefore, it is referred to as being in the VDDL voltage domain. In some embodiments, the first power supply voltage VDDL has a first voltage swing. In some embodiments, one or more of the input signal IN, input signal IB, or input signal IBB have a first voltage swing.

[0028] Enable circuit 104 is coupled to the second input terminal of level shifter circuit 106 and signal source NSLEEP. Enable circuit 104 is configured to receive signal NSLEEP and generate signal SLEEP. Signal SLEEP is inverted from signal NSLEEP. In some embodiments, enable circuit 104 is configured to receive signal NSLEEP and generate signals SLEEP and NSLEEPD. Figure 4 The signal NSLEEPD is inverted from the signal SLEEP. In some embodiments, the enable circuit 104 is configured to output the signal SLEEP to the level shifter circuit 106. In some embodiments, the enable circuit 104 is configured to output at least the signal SLEEP or the signal NSLEEPD to the level shifter circuit 106. In some embodiments, at least the signals NSLEEP, SLEEP, or NSLEEPD are corresponding enable signals configured to enable the level shifter circuit 106 or the output circuit 108.

[0029] The level shifter circuit 106 is coupled to the input circuit 102, the enable circuit 104 and the output circuit 108.

[0030] The level shifter circuit 106 is configured to receive at least the signal SLEEP, the input signal IB, or the input signal IBB. In some embodiments, the level shifter circuit 106 is configured to receive at least the signal SLEEP, the signal NSLEEPD, the input signal IB, or the input signal IBB.

[0031] In some embodiments, the level shifter circuit 106 is configured to generate at least a first signal SH1 or a second signal SH2 in response to at least the signal SLEEP, the signal NSLEEPD, the input signal IB, or the input signal IBB. The level shifter circuit 106 is configured to output at least the first signal SH1 or the second signal SH2 to the output circuit 108. In other words, one or more of the first signal SH1 or the second signal SH2 is the output of the level shifter circuit 106.

[0032] In some embodiments, the level shifter circuit 106 is coupled to a second voltage source node 2N, the second voltage source node 2N having a second power supply voltage VDD. Figure 2 and Figure 4 Therefore, it is referred to as being in the VDD voltage domain. In some embodiments, the second power supply voltage VDD is different from the first power supply voltage VDDL. In some embodiments, the second power supply voltage VDD is greater than the first power supply voltage VDDL. In some embodiments, the second power supply voltage VDD is less than the first power supply voltage VDDL. In some embodiments, the second power supply voltage VDD has a second voltage swing different from the first voltage swing. In some embodiments, the VDD voltage domain is different from the VDDL voltage domain. The level shifter circuit 106 is a level shifter circuit configured to shift the input signal IN, INB, or INBB from the VDDL voltage domain using the power supply voltage VDDL to the VDD voltage domain using the power supply voltage VDD.

[0033] In some embodiments, one or more of the first signal SH1 or the second signal SH2 are referred to as level-shifted output signals. In some embodiments, one or more of the first signal SH1 or the second signal SH2 have a second voltage swing.

[0034] Output circuit 108 is coupled to level shifter circuit 106. The input terminals of output circuit 108 are coupled to at least the output terminals of level shifter circuit 106 and are configured to receive at least a first signal SH1 or a second signal SH2. Output circuit 108 is configured to generate at least an output signal OUT in response to at least the first signal SH1 or the second signal SH2.

[0035] The output terminal of the output circuit 108 is configured to output an output signal OUT. The output signal OUT is the output signal of the integrated circuit 100. In some embodiments, the output signal OUT is referred to as a level-shifted output signal of the integrated circuit 100. In some embodiments, the output signal OUT has a second voltage swing. In some embodiments, the output signal OUT is a level-shifted form of the input signal IN.

[0036] Integrated circuit 100 is configured to operate in either a first mode or a second mode. For example, in the first mode, level shifter circuit 106 is enabled or woken up, and the output signal OUT corresponds to the level-shifted form of the input signal IN. In the second mode, level shifter circuit 106 is disabled or put to sleep, and the output signal OUT is either logic high or logic low.

[0037] In some embodiments, the first mode is referred to as a level shift mode, and the second mode is referred to as a sleep mode. In some embodiments, the integrated circuit 100 is referred to as a level shifter.

[0038] In some embodiments, the level shifter circuit 106 is enabled or turned on by a signal SLEEP or NSLEEPD having a first logic value. In some embodiments, the level shifter circuit 106 is disabled or turned off by a signal SLEEP or NSLEEPD having a second logic value. In some embodiments, the second logic value is inversely related to the first logic value.

[0039] In some embodiments, by disabling the level shifter circuit 106, the integrated circuit 100 exhibits better power performance than other methods. In some embodiments, by disabling the level shifter circuit 106, the integrated circuit 100 consumes less power than other methods.

[0040] Figure 2 This is a circuit diagram of circuit 200 according to some embodiments.

[0041] Circuit 200 is Figure 1 An embodiment of the integrated circuit 100.

[0042] Circuit 200 includes input circuit 202, enable circuit 204, level shifter circuit 206 and output circuit 208.

[0043] Input circuit 202 is Figure 1 An embodiment of the input circuit 102 is described below, and similar detailed descriptions are omitted. The input circuit 202 includes inverters 202a and 202b.

[0044] Inverter 202a is configured to receive input signal IN and output input signal IB. Inverter 202a is coupled to a first voltage source node 1N. Inverters 202a and 202b are configured to operate in the VDDL voltage domain. Inverter 202a is configured to generate input signal IB in response to input signal IN.

[0045] Inverter 202b is configured to receive input signal IB and output input signal IBB. Inverter 202b is coupled to a first voltage source node 1N. Inverter 202b is configured to generate input signal IBB in response to input signal IB.

[0046] Input circuit 202, inverter 202a, and inverter 202b are coupled to level shifter circuit 206. For ease of illustration, input circuit 202, inverter 202a, and inverter 202b are not shown as being coupled to level shifter circuit 206.

[0047] Inverter 202a includes a P-type metal-oxide-semiconductor (PMOS) transistor M1 and an N-type metal-oxide-semiconductor (NMOS) transistor M2.

[0048] Inverter 202b includes PMOS transistor M3 and NMOS transistor M4.

[0049] The gate terminals of PMOS transistor M1 and NMOS transistor M2 are coupled together and configured as the input node (not labeled) of input circuit 202. The gate terminals of PMOS transistor M1 and NMOS transistor M2 are configured to receive the input signal IN.

[0050] The source terminal of PMOS transistor M1 is coupled to a voltage source node having a first power supply voltage VDDL. The source terminal of NMOS transistor M2 is coupled to a reference voltage source VSS. The body or body terminal of PMOS transistor M1 is coupled to a first voltage source node 1N having a first power supply voltage VDDL. The body or body terminal of NMOS transistor M2 is coupled to the reference voltage source VSS.

[0051] The drain terminals of PMOS transistor M1 and NMOS transistor M2 are coupled together and configured as the output node (e.g., node n1) of inverter 202a. The drain terminals of PMOS transistor M1 and NMOS transistor M2 are configured to output the input signal IB at node n1.

[0052] The drain terminal of PMOS transistor M1, the drain terminal of NMOS transistor M2, the gate terminal of PMOS transistor M3, and the gate terminal of NMOS transistor M4 are each coupled together at node n1.

[0053] The gate terminals of PMOS transistor M3 and NMOS transistor M4 are configured to receive input signal IB from the drain terminals of PMOS transistor M1 and NMOS transistor M2.

[0054] The drain terminals of PMOS transistor M3 and NMOS transistor M4 are coupled together and configured as the output node (e.g., node n2) of inverter 202b. The drain terminals of PMOS transistor M3 and NMOS transistor M4 are configured to output the input signal IBB at node n2.

[0055] The source terminal of PMOS transistor M3 is coupled to a first voltage source node 1N having a first power supply voltage VDDL. The source terminal of NMOS transistor M4 is coupled to a reference voltage source VSS. The body or body terminal of PMOS transistor M3 is coupled to a first voltage source node 1N having a first power supply voltage VDDL. The body or body terminal of NMOS transistor M4 is coupled to a reference voltage source VSS.

[0056] Other transistor types or numbers in the input circuit 202 are within the scope of this disclosure.

[0057] Enable circuit 204 is Figure 1 An embodiment of the enable circuit 104 is described below, and similar detailed descriptions are omitted. Enable circuit 204 includes an inverter 204a coupled to the second voltage source node 2N. Enable circuit 204 is coupled to at least level shifter circuit 206 or output circuit 208. For ease of illustration, enable circuit 204 is not shown as being coupled to level shifter circuit 206 or output circuit 208.

[0058] Inverter 204a is configured to receive the signal NSLEEP and output the signal SLEEP. Inverter 204a is coupled to a second voltage source node 2N. Inverter 204a is configured to operate in the VDD voltage domain. Inverter 204a is configured to generate the signal SLEEP in response to the signal NSLEEP. The input terminal of inverter 204a is configured to receive the signal NSLEEP. The output terminal of inverter 204a is configured to output the signal SLEEP to level shifter circuit 206 and output circuit 208 at node n3. The output terminal of inverter 204a is coupled to level shifter circuit 206 and output circuit 208 at node n3.

[0059] Inverter 204a includes PMOS transistor M5 and NMOS transistor M6.

[0060] The gate terminals of PMOS transistor M5 and NMOS transistor M6 are coupled together and configured as the input node (unlabeled) of enable circuit 204. The gate terminals of PMOS transistor M5 and NMOS transistor M6 are configured to receive the signal NSLEEP.

[0061] The source terminal of PMOS transistor M5 is coupled to a second voltage source node 2N having a second power supply voltage VDD. The source terminal of NMOS transistor M6 is coupled to a reference voltage source VSS. The body or body terminal of PMOS transistor M5 is coupled to a second voltage source node 2N having a second power supply voltage VDD. The body or body terminal of NMOS transistor M6 is coupled to a reference voltage source VSS.

[0062] The drain terminals of PMOS transistor M5 and NMOS transistor M6 are coupled together and configured as the output node (e.g., node n3) of inverter 204a. The drain terminals of PMOS transistor M5 and NMOS transistor M6 are configured to output the signal SLEEP at node n3.

[0063] Other transistor types or numbers in the enabling circuit 204 are within the scope of this disclosure.

[0064] Level shifter circuit 206 is Figure 1 An embodiment of the level shifter circuit 106 is described below, and similar detailed descriptions are omitted. The level shifter circuit 206 is configured to shift an input signal IN, IB, or IBB from the VDDL voltage domain to the VDD voltage domain. The level shifter circuit 206 is coupled to at least an input circuit 202, an enable circuit 204, and an output circuit 208. The level shifter 206 is configured to receive at least a signal NSLEEP, an input signal IB, or an input signal IBB. The level shifter 206 is configured to generate a first signal SH1 in response to at least the signal NSLEEP or the input signal IBB. The level shifter 206 is configured to generate a second signal SH2 in response to at least the signal NSLEEP or the input signal IB. The first signal SH1 or the second signal SH2 is the output of the level shifter circuit 206. The level shifter circuit 206 is configured to operate in the VDD voltage domain. In some embodiments, one or more of the first signal SH1 or the second signal SH2 are level-shifted output signals (e.g., second voltage swing) of the input signal IN (e.g., first voltage swing).

[0065] The level shifter circuit 206 includes PMOS transistors M7, M8, M9, M10, and M11, and NMOS transistors M12 and M13. Each of the PMOS transistors M7, M8, M9, M10, and M11, and the NMOS transistors M12 and M13, is configured to operate in the VDD voltage domain.

[0066] PMOS transistors M7, M8, M9, M10, and M11 are part of region 206a of level shifter circuit 206. NMOS transistors M12 and M13 are part of region 206b of level shifter circuit 206.

[0067] PMOS transistor M7 is coupled between node n4 of level shifter circuit 206 and the second voltage source node 2N. The voltage at node n4 corresponds to the voltage of signal CCHD. PMOS transistor M7 is also referred to as the header circuit.

[0068] The source terminal of PMOS transistor M7 is coupled to node 2N of a second voltage source having a second power supply voltage VDD. The drain terminal of PMOS transistor M7 is coupled to node n4, the source terminal of PMOS transistor M8, and the source terminal of PMOS transistor M9. The body or body terminal of PMOS transistor M7 is coupled to node 2N of the second voltage source.

[0069] The gate terminal of PMOS transistor M7 is coupled at node n3 to at least the drain terminal of PMOS transistor M5 and the drain terminal of NMOS transistor M6. The gate terminal of PMOS transistor M7 is configured to receive the SLEEP signal. PMOS transistor M7 is turned on or off based on the SLEEP signal. In response to being turned on by the SLEEP signal, PMOS transistor M7 electrically couples node n4 to the second voltage source node 2N, thereby setting the voltage of node n4 equal to the second supply voltage VDD. In response to being turned off by the SLEEP signal, PMOS transistor M7 electrically decouples node n4 and the second voltage source node 2N from each other.

[0070] PMOS transistors M8 and M10 (collectively referred to as the "first group of transistors") are coupled between the first node n5 and node n4 of the level shifter circuit 206. The voltage of the first node n5 corresponds to the voltage of the second signal SH2.

[0071] PMOS transistors M9 and M11 (collectively referred to as the "second group of transistors") are coupled between the second node n6 and node n4 of the level shifter circuit 206. The voltage of the second node n6 corresponds to the voltage of the first signal SH1.

[0072] Each of node n6, the gate terminal of PMOS transistor M8, the drain terminal of PMOS transistor M11, the drain terminal of NMOS transistor M13, the drain terminal of NMOS transistor M14, the gate terminal of PMOS transistor M15, the gate terminal of PMOS transistor M16, the gate terminal of NMOS transistor M17, and the gate terminal of NMOS transistor M18 is coupled together.

[0073] The gate terminal of PMOS transistor M8 is configured to receive the first signal SH1. PMOS transistor M9 is turned on or off based on the first signal SH1.

[0074] Each of the source terminals of PMOS transistor M8, PMOS transistor M9, and PMOS transistor M7 is coupled together at node n4.

[0075] The drain terminal of PMOS transistor M8 and the source terminal of PMOS transistor M10 are coupled together. The body or body terminal of PMOS transistor M8 is coupled to the second voltage source node 2N.

[0076] Each of node n5, the gate terminal of PMOS transistor M9, the drain terminal of PMOS transistor M10, and the drain terminal of NMOS transistor M12 is coupled together.

[0077] The gate terminal of PMOS transistor M9 is configured to receive a second signal SH2. PMOS transistor M9 is turned on or off based on the second signal SH2.

[0078] The drain terminal of PMOS transistor M9 is coupled to the source terminal of PMOS transistor M11. The body or body terminal of PMOS transistor M9 is coupled to the second voltage source node 2N.

[0079] The gate terminal of the PMOS transistor M10 is configured to receive the input signal IB. The PMOS transistor M10 is turned on or off based on the input signal IB.

[0080] The gate terminal of PMOS transistor M10, the gate terminal of NMOS transistor M12, the drain terminal of PMOS transistor M1, the drain terminal of NMOS transistor M2, and each of node n1 are coupled together. The body or body terminal of PMOS transistor M10 is coupled to the second voltage source node 2N.

[0081] The gate terminal of PMOS transistor M11 is configured to receive the input signal IBB. PMOS transistor M11 is turned on or off based on the input signal IBB.

[0082] The gate terminal of PMOS transistor M11, the gate terminal of NMOS transistor M13, the drain terminal of PMOS transistor M3, the drain terminal of NMOS transistor M4, and each of node n2 are coupled together. The body or body terminal of PMOS transistor M11 is coupled to the second voltage source node 2N.

[0083] The gate terminal of NMOS transistor M12 is configured to receive an input signal IB. NMOS transistor M12 is turned on or off based on the input signal IB. The source terminal of NMOS transistor M12 is coupled to a reference voltage source VSS. The body or body terminal of NMOS transistor M12 is also coupled to the reference voltage source VSS.

[0084] The gate terminal of NMOS transistor M13 is configured to receive the input signal IBB. NMOS transistor M13 is turned on or off based on the input signal IBB. The source terminal of NMOS transistor M13 is coupled to a reference voltage source VSS. The body or body terminal of NMOS transistor M13 is also coupled to the reference voltage source VSS.

[0085] NMOS transistor M12, PMOS transistor M8, and PMOS transistor M10 are referred to as the first path P1 of the level shifter circuit 206. NMOS transistor M13, PMOS transistor M9, and PMOS transistor M11 are referred to as the second path P2 of the level shifter circuit 206. The first path P1 and the second path P2 of the level shifter circuit 206 are enabled or disabled by at least the input signal IB or IBB.

[0086] Other transistor types or numbers in the level shifter circuit 206 are within the scope of this disclosure.

[0087] Output circuit 208 is Figure 1 An embodiment of the output circuit 108 is described below, and similar detailed descriptions are omitted. The output circuit 208 is configured to receive at least the signal SLEEP or a first signal SH1. The output circuit 208 is configured to generate at least the output signal OUT1 in response to at least the first signal SH1 or the signal SLEEP. The output circuit 208 is at least coupled to the level shifter circuit 206, the second voltage source node 2N of the level shifter circuit 206, or the second node n6.

[0088] The output circuit 208 includes PMOS transistors M15 and M16 and NMOS transistors M14, M17 and M18. Each of the PMOS transistors M15 and M16 and the NMOS transistors M14, M17 and M18 is configured to operate in the VDD voltage domain.

[0089] NMOS transistor M14 is part of region 208a of output circuit 208. PMOS transistors M15 and M16, as well as NMOS transistors M14 and M17, are part of region 208b of output circuit 208.

[0090] Although NMOS transistor M14 is in Figure 2 While shown as part of output circuit 208, in some embodiments, NMOS transistor M14 is not part of output circuit 208. For example, in some embodiments, NMOS transistor M14 is part of level shifter circuit 206. In some embodiments, NMOS transistor M14 is neither part of level shifter circuit 206 nor part of output circuit 208.

[0091] The NMOS transistor M14 is configured to set the voltage at the second node n6 corresponding to the first signal SH1. The NMOS transistor M14 is coupled between node n6 of the level shifter circuit 206 and the node of the reference voltage source VSS. The NMOS transistor M14 is also referred to as the pin circuit.

[0092] The source terminal of NMOS transistor M14 is coupled to the node of the reference voltage source VSS. The body or body terminal of NMOS transistor M14 is coupled to the node of the reference voltage source VSS.

[0093] The gate terminal of NMOS transistor M14 is coupled at node n3 to at least the drain terminal of NMOS transistor M5, the drain terminal of NMOS transistor M6, and the gate terminal of PMOS transistor M7. The gate terminal of NMOS transistor M14 is configured to receive the SLEEP signal. NMOS transistor M14 is turned on or off based on the SLEEP signal. In response to being turned on by the SLEEP signal, NMOS transistor M14 electrically couples node n6 to the node of the reference voltage source VSS, thereby setting the voltage of node n6 equal to that of the reference voltage source VSS. In response to being turned off by the SLEEP signal, NMOS transistor M14 electrically decouples node n6 from the node of the reference voltage source VSS.

[0094] PMOS transistors M15 and M16, and NMOS transistors M17 and M18 are coupled to level shifter circuit 206 and NMOS transistor M14 via a second node n6. PMOS transistors M15 and M16, and NMOS transistors M17 and M18 are configured to generate output signal OUT1 in response to at least a first signal SH1.

[0095] Each of the gate terminals of PMOS transistor M15, PMOS transistor M16, NMOS transistor M17, and NMOS transistor M18 is at least coupled to a second node n6 of the level shifter circuit 206. Each of the gate terminals of PMOS transistor M15, PMOS transistor M16, NMOS transistor M17, and NMOS transistor M18 is configured to receive a first signal SH1.

[0096] Each of the PMOS transistors M15, M16, M17, and M18 is configured to be turned on or off based on a first signal SH1. In some embodiments, PMOS transistors M15-M16 and NMOS transistors M17-M18 are used as inverters.

[0097] For example, in some embodiments, if the first signal SH1 is logically high, then PMOS transistors M15 and M16 are turned off, NMOS transistors M17 and M18 are turned on, and the output signal OUT1 is logically low. For example, in some embodiments, if the first signal SH1 is logically low, then PMOS transistors M15 and M16 are turned on, NMOS transistors M17 and M18 are turned off, and the output signal OUT1 is logically high.

[0098] The source terminal of PMOS transistor M15 is coupled to the second voltage source node 2N. The drain terminal of PMOS transistor M15 is coupled to the source terminal of PMOS transistor M16. At least the body or body terminal of PMOS transistor M15 or the body or body terminal of PMOS transistor M16 is coupled to the second voltage source node 2N.

[0099] The drain terminals of PMOS transistor M16 and NMOS transistor M17 are coupled together and correspond to the output node ND0 of output circuit 208. Output node ND0 of output circuit 208 has an output signal OUT1.

[0100] The source terminal of NMOS transistor M17 and the drain terminal of NMOS transistor M18 are coupled to each other. The source terminal of NMOS transistor M18 is coupled to at least the reference voltage source node VSS. At least the body or body terminal of NMOS transistor M17 or the body or body terminal of NMOS transistor M18 is coupled to the reference voltage source VSS.

[0101] Other transistor types or numbers in the output circuit 208 are within the scope of this disclosure.

[0102] Circuit 200 is configured to operate in either a first mode or a second mode. For example, in the first mode, level shifter circuit 206 is enabled or woken up, and the output signal OUT1 corresponds to the level-shifted form of the input signal IN. In the second mode, level shifter circuit 206 is disabled or in sleep mode, and the output signal OUT1 is a high logic value or a low logic value.

[0103] In some embodiments, the level shifter circuit 206 is enabled or turned on by a signal NSLEEP equal to a high logic value (e.g., "1"). In some embodiments, the level shifter circuit 206 is disabled or turned off by a signal NSLEEP equal to a low logic value (e.g., "0"). Other values ​​of the signal NSLEEP that cause the level shifter circuit 206 to be enabled or turned on are within the scope of this disclosure. Other values ​​of the signal NSLEEP that cause the level shifter circuit 206 to be disabled or turned off are within the scope of this disclosure.

[0104] In some embodiments, when the level shifter circuit 206 is disabled or in sleep mode, and the NMOS transistor M14 is enabled or turned on, the circuit 200 is configured to output a high logic value (e.g., "1"), regardless of the value of at least the input signals IN, IBB, or IBB. For example, in some embodiments, if the signal NSLEEP has a low logic value (e.g., "0"), the signal SLEEP has a high logic value (e.g., "1"), causing the PMOS transistor M7 and the level shifter circuit 206 to be disabled, thereby causing the NMOS transistor M14 to be enabled or turned on. In response to the NMOS transistor M14 being enabled or turned on, the NMOS transistor M14 pulls the voltage of node n6 towards the reference voltage VSS, thereby setting the voltage of the first signal SH1 to be equal to the low logic value. In response to the voltage of the first signal SH1 being equal to the low logic value, PMOS transistors M15 and M16 turn on and pull the voltage of the output node ND0 towards the second supply voltage VDD, thereby setting the voltage of the output signal OUT1 to be equal to the high logic value.

[0105] In some embodiments, when the level shifter circuit 206 is enabled or activated and the NMOS transistor M14 is disabled or turned off, the circuit 200 is configured to output an output signal OUT corresponding to the level shifted form of the input signal IN (e.g., the first signal SH1).

[0106] For example, in some embodiments, if the signal NSLEEP has a high logic value (e.g., "1"), the signal SLEEP has a low logic value (e.g., "0"), thereby causing the PMOS transistor M7 and the level shifter circuit 206 to be enabled, and causing the NMOS transistor M14 to be disabled or turned off.

[0107] In response to the PMOS transistor M7 being enabled or turned on, the PMOS transistor M7 pulls the voltage of node n4 towards the second supply voltage VDD, thereby setting the voltage of node n4 (e.g., the signal CCHD) to be equal to the second supply voltage VDD. In response to the NMOS transistor M14 being disabled or turned off, the NMOS transistor M14 will not set the voltage of node n6. In these embodiments, the voltage of node n6 will be set based on the value of the input signal IN by: (1) the NMOS transistor M13 or (2) the PMOS transistors M7, M9, and M11.

[0108] For example, in these embodiments, when the input signal IN has a high logic value (e.g., "1"), the input signal IB has a low logic value (e.g., "0"), and the input signal IBB has a high logic value (e.g., "1").

[0109] In response to the input signal IBB being a high logic value (e.g., "1"), NMOS transistor M13 is turned on, pulling the voltage of the second node n6 towards the reference voltage VSS, thereby setting the voltage of the first signal SH1 to a low logic value. In response to the first signal SH1 being a low logic value, PMOS transistors M15 and M16 are turned on and pull the voltage of the output node ND0 towards the second power supply voltage VDD, thereby setting the voltage of the output signal OUT1 to a high logic value. Therefore, when the input signal IN has a high logic value (e.g., "1") in the VDDDL domain, the output signal OUT1 is a level-shifted form of the input signal IN and is equal to the high logic value in the VDD domain.

[0110] For example, in these embodiments, when the input signal IN has a low logic value (e.g., "0"), the input signal IB has a high logic value (e.g., "1"), and the input signal IBB has a low logic value (e.g., "0").

[0111] In response to the input signal IB being a high logic value (e.g., "1"), the PMOS transistor M10 is turned off and the NMOS transistor M12 is turned on, thereby causing the NMOS transistor M12 to pull the voltage of the first node n5 to the reference voltage VSS, and setting the gate voltage of the PMOS transistor M9 to be equal to a low logic value.

[0112] In response to the voltage at the gate of PMOS transistor M9 being equal to a low logic value, PMOS transistor M9 is turned on, thereby coupling node n4 to the source terminal of PMOS transistor M11.

[0113] In response to the input signal IBB being a low logic value (e.g., "0"), NMOS transistor M13 is turned off and PMOS transistor M11 is turned on. However, since node n4 is electrically coupled to the source terminal of PMOS transistor M11, turning on PMOS transistor M11 causes node n4 to be electrically coupled to the second node n6. By electrically coupling node n4 to the second node n6, one or more of PMOS transistors M7, M9, and M11 pull the voltage of the second node n6 towards the second power supply voltage VDD, thereby setting the voltage of the first signal SH1 to be equal to a high logic value.

[0114] In response to the voltage of the first signal SH1 being equal to a high logic value, NMOS transistors M17 and M18 are turned on, pulling the voltage of output node ND0 towards the reference supply voltage VSS, thereby setting the voltage of output signal OUT1 to be equal to a low logic value. Therefore, when the input signal IN has a low logic value (e.g., "0") in the VDDL domain, the output signal OUT1 is a level-shifted form of the input signal IN and is equal to a low logic value in the VDD domain.

[0115] Other values ​​for the signals NSLEEP and SLEEP, the transistor type or configuration of the level shifter circuit 206 and the output circuit 208 are within the scope of this disclosure.

[0116] Each transistor in circuit 202 has a corresponding threshold voltage. In some embodiments, the threshold voltage of the transistor device is related to one or more of the following: the work function difference between the channel and the gate electrode of the transistor, the amount of p-type or n-type dopant in the transistor device, or the thickness of the gate oxide of the corresponding gate in the transistor device, etc.

[0117] For example, in some embodiments, increasing the work function difference between the channel and gate of an NMOS transistor increases the threshold voltage of the NMOS transistor, and vice versa. Similarly, in some embodiments, increasing the work function difference between the channel and gate of a PMOS transistor decreases the threshold voltage of the PMOS transistor, and vice versa.

[0118] For example, in some embodiments, the threshold voltage of the transistor device is reduced by decreasing the thickness of the gate oxide of the transistor device.

[0119] For example, in some embodiments, the threshold voltage is increased by increasing the concentration of P-type dopant in the channel of the NMOS transistor. In some embodiments, the threshold voltage is decreased by increasing the concentration of N-type dopant in the channel of the NMOS transistor.

[0120] In some embodiments, each transistor in the input circuit 202 has a first threshold voltage. In some embodiments, the first threshold voltage corresponds to a standard threshold voltage. In some embodiments, each transistor in the input circuit 202 corresponds to a standard threshold voltage device.

[0121] In some embodiments, each transistor in region 206b of the level shifter circuit 206 has a second threshold voltage. In some embodiments, the second threshold voltage corresponds to a high threshold voltage. In some embodiments, each transistor in region 206b of the level shifter circuit 206 corresponds to a high threshold voltage device.

[0122] In some embodiments, each transistor in region 206a of the enable circuit 204, the output circuit 208, and the level shifter circuit 206 has a third threshold voltage. In some embodiments, the third threshold voltage corresponds to an ultra-high threshold voltage. In some embodiments, each transistor in region 206a of the enable circuit 204, the output circuit 208, and the level shifter circuit 206 corresponds to an ultra-high threshold voltage device.

[0123] In some embodiments, the first threshold voltage is less than the second threshold voltage and the third threshold voltage. In some embodiments, the second threshold voltage is less than the third threshold voltage.

[0124] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first work function difference; NMOS transistors M6, M14, M17, and M18, having a second threshold voltage, have a corresponding second work function difference; and NMOS transistors M12 and M13, having a third threshold voltage, have a corresponding third work function difference. In some embodiments, the first work function difference is less than the second and third work function differences. In some embodiments, the second work function difference is less than the third work function difference.

[0125] In some embodiments, PMOS transistors M1 and M3, which have a first threshold voltage, have a corresponding fourth work function difference, and PMOS transistors M5, M7, M8, M9, M10, M11, M15, and M16, which have a second threshold voltage, have a corresponding fifth work function difference. In some embodiments, the fourth work function difference is greater than the fifth work function difference.

[0126] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first gate oxide thickness; NMOS transistors M6, M14, M17, and M18, having a second threshold voltage, have a corresponding second gate oxide thickness; and NMOS transistors M12 and M13, having a third threshold voltage, have a corresponding third gate oxide thickness. In some embodiments, the first gate oxide thickness is less than the second and third gate oxide thicknesses. In some embodiments, the second gate oxide thickness is less than the third gate oxide thickness.

[0127] In some embodiments, PMOS transistors M1 and M3 having a first threshold voltage have a corresponding fourth gate oxide thickness, and PMOS transistors M5, M7, M8, M9, M10, M11, M15, and M16 having a second threshold voltage have a corresponding fifth gate oxide thickness. In some embodiments, the fourth gate oxide thickness is less than the fifth gate oxide thickness.

[0128] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first P-type dopant concentration in their channels; NMOS transistors M6, M14, M17, and M18, having a second threshold voltage, have a corresponding second P-type dopant concentration in their channels; and NMOS transistors M12 and M13, having a third threshold voltage, have a corresponding third P-type dopant concentration in their channels. In some embodiments, the first P-type dopant concentration in the channel is less than both the second and third P-type dopant concentrations. In some embodiments, the second P-type dopant concentration in the channel is less than the third P-type dopant concentration in the channel.

[0129] In some embodiments, by configuring the level shifter circuit 206 to include regions 206a and 206b with different threshold voltages, leakage current in the first path P1 or the second path P2 is reduced, thereby reducing the power consumption of the circuit 200 compared to other methods with higher leakage current and greater power consumption.

[0130] In some embodiments, by configuring the level shifter circuit 206 as a head circuit (e.g., PMOS transistor M7), leakage current in the first path P1 or the second path P2 is reduced when the level shifter circuit 206 is disabled or in a sleep mode, thereby reducing the power consumption of the circuit 200 compared to other methods with higher leakage current and greater power consumption.

[0131] In some embodiments, by configuring circuit 200 as a head circuit (e.g., PMOS transistor M7), the number of transistors in circuit 200 is reduced, thereby reducing the power consumption of circuit 200 compared to other methods that have higher leakage current and greater power consumption.

[0132] Figures 3A-3D This is a schematic diagram of an integrated circuit 300 according to some embodiments.

[0133] Integrated Circuit 300 is Figure 1 Integrated circuit 100 or Figure 2 The embodiment of circuit 200 is described in detail below, therefore a similar detailed description is omitted.

[0134] For ease of explanation, Figures 3A-3D Some of the elements in one or more of the already marked elements are in Figures 3A-3D One or more figures in the diagram are no longer marked repeatedly. In some embodiments, integrated circuit 300 includes Figures 3A-3D Additional elements not shown.

[0135] Figure 3A , Figure 3B and Figure 3D This is a top view of an integrated circuit 300 according to some embodiments. Figure 3C This is region 380 of the integrated circuit 300, which is simplified for ease of explanation.

[0136] For clarity, not every element of integrated circuit 300 is... Figure 3A , Figure 3B , Figure 3C and Figure 3D The middle mark. For example, in Figure 3A The text indicates that one or more elements in the N-well layer and the oxide diffusion (OD) layer or active layer of the integrated circuit 300 are marked. For example, in... Figure 3B The text is a series of symbols and characters, each representing one or more elements of the POLY layer, the via over gate (VG) layer, and the via overdiffusion (VD) layer of the integrated circuit 300. For example, in... Figure 3C The text is a series of seemingly unrelated phrases and sentences, making it impossible to translate coherently. It appears to be a collection of fragments from various sources, possibly related to integrated circuits, and includes references to VG, VD, and other topics. A proper translation would require the original context and complete sentences. Figure 3D The text indicates one or more elements in the metal 0 (M0) layer and the metal 1 (M1) layer of the integrated circuit 300.

[0137] Integrated circuit 300 is manufactured using a corresponding layout design similar to integrated circuit 200. For the sake of simplicity, Figures 3A-3D It is described as the corresponding integrated circuit 300, but in some embodiments, Figures 3A-3D Further corresponding to a layout design having features similar to integrated circuit 200, and the structural elements of integrated circuit 300 further corresponding to a layout pattern, and the structural relationships of integrated circuit 300 including alignment, length and width, as well as the configuration and layers of the corresponding layout design, are similar to the structural relationships, configuration and layers of integrated circuit 200, and for the sake of brevity, similar detailed descriptions will not be described.

[0138] For the sake of brevity and clarity, Figure 3A , Figure 3B , Figure 3C and Figure 3D The common reference numerals and elements in the figures retain the same designations. Furthermore, to avoid repetition, these elements will not be discussed further. Differences between the figures are indicated by separate, new reference numerals, and these differences are discussed.

[0139] Integrated circuit 300 includes regions 380a and 380b (collectively referred to as "region 380"), regions 382a and 382b (collectively referred to as "region 382"), and region 384. In some embodiments, region 380a corresponds to Figure 2The enabling circuit 204, region 206a, and output circuit 208 will not be described in similar detail for the sake of brevity. In some embodiments, region 380b corresponds to Figure 2 For the sake of brevity, region 206b will not be described in a similar detailed description. In some embodiments, region 382b corresponds to Figure 2 For the sake of brevity, the input circuit 202 will not be described in a similar detailed description.

[0140] Integrated circuit 300 includes a substrate 390 and a set of wells 301. The substrate 390 includes the set of wells 301. The set of wells 301 extends in a first direction (e.g., the X-axis) and is located within the substrate 390. The set of wells 301 has a first dopant type. The first dopant type is an N-type dopant. In some embodiments, the N-type dopant includes phosphorus, arsenic, or other suitable N-type dopant. In some embodiments, the set of wells 301 includes a p-type dopant. In some embodiments, the p-type dopant includes boron, aluminum, or other suitable p-type dopant. The substrate 390 has a dopant type opposite to the dopant type of the set of wells 301. In some embodiments, the substrate 390 has the first dopant type.

[0141] The group of wells 301 includes wells 301a, 301b, and 301c. Each well in the group of wells 301 is spaced apart from each other in a first direction X. Each well in the group of wells 301 corresponds to one or more PMOS transistors in integrated circuit 200.

[0142] The integrated circuit 300 also includes a set of active regions 302. The set of active regions 302 includes one or more active regions 302a, 302b...302l or 302m embedded in the substrate 390.

[0143] The group of active regions 302 extends in a first direction X. Each active region of the group of active regions 302 is separated from each other in a first direction or a second direction Y. In some embodiments, the group of active regions 302 is referred to as an oxide diffusion (OD) region, which defines a source or drain diffusion region of the integrated circuit 200.

[0144] In some embodiments, the group of active regions 302 is located on a first level. In some embodiments, the first level corresponds to the active level or OD level of the integrated circuit 200.

[0145] Figure 2 The NMOS transistor M12 is shown as NMOS transistor M12a and NMOS transistor M12b in integrated circuit 300. Figure 2 The NMOS transistor M13 is shown as NMOS transistor M13a and NMOS transistor M13b in integrated circuit 300, and Figure 2 The PMOS transistor M7 is shown as PMOS transistor M7_1 and PMOS transistor M7_2 in integrated circuit 300. For the sake of brevity, similar detailed descriptions will not be described.

[0146] In some embodiments, active region 302a corresponds to the source and drain regions of NMOS transistors M17, M18, and M6 in circuit 200; active region 302b corresponds to the source and drain regions of NMOS transistor M14 in circuit 200; active region 302c corresponds to the source and drain regions of PMOS transistors M16, M15, and M5 in circuit 200; active region 302d corresponds to the body / tap regions of PMOS transistors M10, M8, M7_2, M7_1, M9, and M11 in circuit 200; active region 302e corresponds to the source and drain regions of PMOS transistors M10, M8, and M7_2 in circuit 200; active region 302f corresponds to the source and drain regions of PMOS transistors M7_1, M9, and M11 in circuit 200; and active region 302g corresponds to the source and drain regions of NMOS transistor M12a. The active regions are as follows: active region 302h corresponds to the source and drain regions of NMOS transistors M13a, M13b, and M12b in circuit 200; active region 302i corresponds to the body / tap regions of PMOS transistors M3 and M1 in circuit 200; active region 302j corresponds to the source and drain regions of NMOS transistors M3 and M1 in circuit 200; active region 302k corresponds to the source and drain regions of PMOS transistors M4 and M2 in circuit 200; active region 302l corresponds to the body / tap regions of NMOS transistors M17, M18, M6, and M14 in circuit 200; active region 302m corresponds to the body / tap regions of circuit 200; and active region 302n corresponds to the body / tap regions of NMOS transistors M12a, M13a, M13b, and M12b in circuit 200. For the sake of brevity, similar detailed descriptions will not be provided. Other transistor types and source / drain regions are within the scope of this disclosure.

[0147] Active regions 302c, 302d, 302e, and 302f are located within sink 301a. Active regions 302i and 302j are located within sink 301b. Active region 302m is located within sink 301c.

[0148] The number of other configurations, arrangements, or structures at other layout levels in the active region 302 of this group is within the scope of this disclosure.

[0149] Integrated circuit 300 also includes gate groups 304, 305 and 306.

[0150] The gate group 304 includes one or more of gates 304a, 304b...304l or 304m.

[0151] Gate group 305 includes one or more of gates 305a, 305b...305j or 305k.

[0152] The gate group 306 includes one or more of gates 306a, 306b...306g or 306h.

[0153] Gate groups 304, 305, and 306 extend in a second direction Y. Each gate in gate group 304 is separated from its adjacent gate pattern in gate group 304 by a first pitch (not labeled) in the first direction X. Each gate in gate group 305 is separated from its adjacent gate pattern in gate group 305 by a first pitch (not labeled) in the first direction X. Each gate in gate group 306 is separated from its adjacent gate pattern in gate group 306 by a first pitch (not labeled) in the first direction X.

[0154] In some embodiments, gate 304b is the gate of each of NMOS transistor M12a and PMOS transistor M10.

[0155] In some embodiments, gate 304c is the gate of each of NMOS transistor M8, NMOS transistor M17, and PMOS transistor M16.

[0156] In some embodiments, gate 304d is the gate of each of NMOS transistor M7_2, NMOS transistor M18, and PMOS transistor M15.

[0157] In some embodiments, gate 304e is the gate of each of NMOS transistor M6 and PMOS transistor M5.

[0158] In some embodiments, gate 304f is the gate of PMOS transistor M7_1.

[0159] In some embodiments, gate 304g is the gate of each of NMOS transistor M14 and PMOS transistor M9.

[0160] In some embodiments, gate 304h is the gate of PMOS transistor M11. In some embodiments, gate 304i is the gate of NMOS transistor M13a. In some embodiments, gate 304j is the gate of NMOS transistor M13b. In some embodiments, gate 304k is the gate of PMOS transistor M12b.

[0161] In some embodiments, gate 305a is the gate of each of NMOS transistor M4 and PMOS transistor M3. In some embodiments, gate 305b is the gate of each of NMOS transistor M2 and PMOS transistor M1.

[0162] In some embodiments, at least one or more gates in gate groups 304, 305, or 306 correspond to dummy gates. In some embodiments, a dummy gate is the gate of a non-functional transistor. For example, gate 304a is a dummy gate.

[0163] Gate groups 304, 305, and 306 are located above a set of active regions 302. Gate groups 304, 305, and 306 are located on a second level, which is different from the first level. In some embodiments, the second level is different from the first level. In some embodiments, the second level corresponds to the POLY level of integrated circuit 300. In some embodiments, the POLY level is higher than the OD level.

[0164] Other configurations in gate groups 304, 305 and 306, arrangements at other layout levels or the number of gates are within the scope of this disclosure.

[0165] The integrated circuit 300 also includes contact groups 310, 312 and 314.

[0166] The contact assembly 310 includes one or more of contacts 310a, 310b...310u or 310v.

[0167] The contact assembly 312 includes one or more of contacts 312a, 312b...312f or 312g.

[0168] The contact group 314 includes one or more of contacts 314a, 314b...314h or 314i.

[0169] Contact groups 310, 312, or 314 extend in a first direction X or a second direction Y. Each contact in contact group 310, 312, or 314 is separated from the adjacent contact in contact group 310, 312, or 314 at least in the first direction X or the second direction Y.

[0170] Contact groups 310, 312, or 314 overlap with a set of active regions 302. The contact groups are located on a third level. In some embodiments, the third level corresponds to a contact level or a diffusion-on-metal (MD) level of the integrated circuit 300. In some embodiments, the third level is higher than a second level. In some embodiments, the third level is different from a first level. In some embodiments, one or more contacts in contact groups 310, 312, or 314 are corresponding vias in a diffusion-on-via (VD) level of the integrated circuit 300.

[0171] Contact groups 310, 312, or 314 are configured to electrically couple the active region 302 and the conductor group 320 together. Contact groups 310, 312, or 314 are located between the active region 302 and the conductor group 320.

[0172] Each contact in contact group 310 corresponds to one or more drain or source terminals or body terminals of the PMOS or NMOS transistor of circuit 200. In some embodiments, one or more contacts in contact group 312 correspond to one or more drain or source terminals or body terminals of the PMOS or NMOS transistor of circuit 200.

[0173] In some embodiments, contact 310a is the drain terminal of NMOS transistor M17, contact 310b is the source terminal of NMOS transistors M18 and M6, and contact 310c is the drain terminal of NMOS transistor M6.

[0174] In some embodiments, contact 310d is the source terminal of NMOS transistor M14, and contact 310e is the drain terminal of NMOS transistor M14.

[0175] In some embodiments, contact 310f is the drain terminal of PMOS transistor M16, contact 310g is the source terminal of each of PMOS transistors M15 and M5, and contact 310h is the drain terminal of PMOS transistor M5.

[0176] In some embodiments, contact 310k is the drain terminal of PMOS transistor M10, contact 310l is the source terminal of PMOS transistor M8 and the drain terminal of PMOS transistor M7_2, and contact 310m is the source terminal of PMOS transistor M7_2.

[0177] In some embodiments, contact 310n is the source terminal of PMOS transistor M7_1, contact 310o is the drain terminal of PMOS transistor M7_1 and the source terminal of PMOS transistor M9, and contact 310p is the drain terminal of PMOS transistor M11.

[0178] In some embodiments, contacts 310i and 310j are body terminals of PMOS transistors M16, M15, M5, M10, M8, M7_2, M7_1, M9 and M11.

[0179] In some embodiments, contact 310q is the source terminal of NMOS transistor M12a, and contact 310r is the drain terminal of NMOS transistor M12a.

[0180] In some embodiments, contact 310s is the source terminal of NMOS transistor M13a, contact 310t is the drain terminal of each of NMOS transistors M13a and M13b, contact 310u is the source terminal of each of NMOS transistors M13b and M12b, and contact 310v is the drain terminal of NMOS transistor M12b.

[0181] In some embodiments, contact 312a is the source terminal of PMOS transistor M1, contact 312b is the drain terminal of each of PMOS transistors M1 and M3, contact 312c is the source terminal of PMOS transistor M3, and contact 312d is the body terminal of PMOS transistors M1 and M3.

[0182] In some embodiments, contact 312e is the drain terminal of NMOS transistor M2, contact 312f is the source terminal of each of NMOS transistors M2 and M4, and contact 312g is the drain terminal of NMOS transistor M4.

[0183] In some embodiments, contacts 314f and 314g are body terminals of NMOS transistors M17, M18, M6, and M14. In some embodiments, contacts 314h and 314i are body terminals of NMOS transistors M12a, M13a, M13b, M12b, M4, and M2.

[0184] In some embodiments, one or more contacts in contact groups 310, 312 or 314 overlap with corresponding active regions in a set of active regions 302, thereby electrically coupling the corresponding contacts in contact groups 310, 312 or 314 to the source or drain of the corresponding transistor.

[0185] Other lengths or widths of contact groups 310, 312, or 314 are within the scope of this disclosure. Other configurations, arrangements at other layout levels, or the number of conductors in contact groups 310, 312, or 314 are within the scope of this disclosure.

[0186] Integrated circuit 300 also includes via group 316.

[0187] Via group 316 includes one or more of vias 316a, 316b...316q or 316r.

[0188] Via group 316 extends in a first direction X or a second direction Y. Each via in via group 316 is separated from an adjacent via in via group 316 at least in the first direction X or the second direction Y.

[0189] Via group 316 overlaps with one or more of gate groups 304, 305, or 306. The via group is located on a fourth level. In some embodiments, the fourth level corresponds to the gate-on-gate (VG) level of integrated circuit 300. In some embodiments, the fourth level is above the first and second levels. In some embodiments, the fourth level is on the same level as the third level. In some embodiments, one or more vias in via group 316 are corresponding gate contacts of integrated circuit 300.

[0190] Via group 316 is configured to electrically couple gate group 304, 305 or 306 to conductor group 320. Via group 316 is located between gate group 304, 305 or 306 and conductor group 320.

[0191] Each via in via group 316 corresponds to one or more vias above one or more gates of one or more PMOS or NMOS transistors of circuit 200.

[0192] In some embodiments, one or more vias in via group 316 are located above the corresponding gates in gate group 304, 305 or 306, thereby electrically coupling the corresponding vias in via group 316 to the gates of the corresponding transistors.

[0193] Other lengths or widths of via group 316 are within the scope of this disclosure. Other configurations, arrangements at other layout levels, or the number of conductors in via group 316 are within the scope of this disclosure.

[0194] Integrated circuit 300 also includes conductor group 320.

[0195] The conductor group 320 includes one or more of conductors 320a, 320b, 320c...320o or 320p that extend at least in a first direction X or a second direction Y.

[0196] Each conductor in conductor group 320 is separated from each other at least in the first direction X or the second direction Y.

[0197] Conductor group 320 overlaps with gate group 304, 305 or 306, a group of active regions 302, contact group 310, 312, 314 and via group 316. In some embodiments, conductor group 320 is located on a fifth layer. In some embodiments, the fifth layer is different from the first, second, third and fourth layers. In some embodiments, the fifth layer corresponds to the M1 layer of integrated circuit 300. In some embodiments, the M1 layer is higher than the OD layer, POLY layer, MD layer, VG layer and VD layer, and lower than the M2 layer. Other layers are within the scope of this disclosure. In some embodiments, the fifth layer corresponds to the M0 layer of integrated circuit 300.

[0198] Conductor group 320 overlaps with gate group 304, 305, or 306, a set of active regions 302, contact groups 310, 312, 314, and via group 316. Conductor group 320 electrically connects one or more of the gate group 304, 305, or 306, the set of active regions 302, the contact groups 310, 312, 314, and via group 316. Conductor group 320 is configured to provide signal routing among gate group 304, 305, or 306, the set of active regions 302, the contact groups 310, 312, 314, and via group 316.

[0199] Conductor 320a corresponds to the output pin of integrated circuit 300, and is Figure 2 An embodiment of the output node ND0. Conductor 320a is configured to electrically couple the drain of NMOS transistor M17 and the drain of PMOS transistor M16. For example, conductor 320a is electrically coupled to the drain of NMOS transistor M17 via contact 310a, and conductor 320a is electrically coupled to the drain of PMOS transistor M16 via contact 310f.

[0200] Conductor 320b corresponds to Figure 2 The input terminal of region 208b. Conductor 320b is configured to electrically couple the gates 304c of NMOS transistor M17 and PMOS transistor M16, and the gates 304d of NMOS transistor M18 and PMOS transistor M15 together. For example, conductor 320b is electrically coupled to the gates 304c of NMOS transistor M17 and PMOS transistor M16 through via 316a, and conductor 320b is electrically coupled to the gates 304d of NMOS transistor M18 and PMOS transistor M15 through via 316b.

[0201] Conductor 320c corresponds to Figure 2 The input pin of the enable circuit 204 is configured to receive the NSLEEP signal. Conductor 320c is electrically coupled to the gate of NMOS transistor M6 and the gate of PMOS transistor M5 through via 316c.

[0202] Conductor 320d corresponds to the output pin of enable circuit 204, and is Figure 2An embodiment of node n3. Conductor 320d is configured to electrically couple each of the drain of NMOS transistor M6, the drain of PMOS transistor M5, the gate of PMOS transistor M7_1, and the gate of PMOS transistor M14 together. For example, conductor 320d is electrically coupled to the drain of NMOS transistor M6 via contact 310c, and conductor 320d is electrically coupled to the drain of PMOS transistor M5 via contact 310h. For example, conductor 320d is also electrically coupled to the gate 304f of PMOS transistor M7_1 via via 316d, and conductor 320d is electrically coupled to the gate 304g of PMOS transistor M14 via via 316e.

[0203] In some embodiments, conductor 330a corresponds to node n6. Conductor 330a is electrically coupled to conductor 320e through a via in layer V1 (unlabeled), and conductor 330a is electrically coupled to conductor 320b through a via in layer V1 (unlabeled).

[0204] Conductor 320e is electrically coupled to the drain of PMOS transistor M14 through contact 310e, and conductor 320e is coupled to gate 304m through via 316f. Gate 304m is electrically coupled to conductor 320j through via 316g, and to conductor 320i through 316o.

[0205] In some embodiments, conductors 320f, 320k, and 330b correspond to Figure 2 Node n5. Conductor 320f is configured to electrically couple the gate of PMOS transistor M9, the drain of NMOS transistor M12a, and the drain of PMOS transistor M10 together. For example, conductor 320f is electrically coupled to the gate 304g of PMOS transistor M9 through via 316r, and conductor 320f is electrically coupled to the drain of NMOS transistor M12a through contact 310r, and electrically coupled to the drain of PMOS transistor M10 through contact 310k.

[0206] Conductor 330b is electrically coupled to conductor 320f through a via in layer V1 (unlabeled), and conductor 330b is electrically coupled to conductor 320k through a via in layer V1 (unlabeled). Conductor 320k is electrically coupled to the drain of NMOS transistor M12b through contact 310v.

[0207] Conductor 320g corresponds to Figure 2Node n4. Conductor 320g is configured to electrically couple the drain of PMOS transistor M7_2 and the source of PMOS transistor M8 to the drain of PMOS transistor M7_1 and the source of PMOS transistor M9. For example, conductor 320g is electrically coupled to the drain of PMOS transistor M7_2 and the source of PMOS transistor M8 through contact 310l, and conductor 320g is electrically coupled to the drain of PMOS transistor M7_1 and the source of PMOS transistor M9 through contact 310o.

[0208] Conductor 320h is electrically coupled to the gate 304g of PMOS transistor M7_2 through via 316m, and conductor 320h is electrically coupled to the gate 304f of PMOS transistor M7_1 through via 316n.

[0209] Conductor 320i is electrically coupled to gate 304m through via 316o, and conductor 320i is electrically coupled to the source of NMOS transistors M13a and M13b through contact 310t.

[0210] Conductor 320j is electrically coupled to gate 304m through via 316g, and conductor 320j is electrically coupled to drain of PMOS transistor M11 through contact 310p.

[0211] Conductor 320l is electrically coupled to the gate 304b of NMOS transistor M12a and PMOS transistor M10 through via 316i, and conductor 320l is electrically coupled to the gate 304k of NMOS transistor M12b through via 316h, and conductor 320l is electrically coupled to conductor 330c through via in layer V1 (unlabeled).

[0212] Conductor 330c is electrically coupled to conductor 320l through a via in layer V1 (unlabeled), and conductor 330c is electrically coupled to conductor 320n through a via in layer V1 (unlabeled). Conductor 320n is electrically coupled to the drain of PMOS transistor M1 through contact 312a.

[0213] Conductor 320m corresponds to Figure 2 Node n2. Conductor 320m is electrically coupled to the gate 304h of NMOS transistor M11 through via 316l, conductor 320m is electrically coupled to the gate 304i of NMOS transistor M13a through via 316k, conductor 320m is electrically coupled to the gate 304j of NMOS transistor M13b through via 316j, conductor 320m is electrically coupled to the drain of PMOS transistor M3 through contact 312c, and conductor 320m is electrically coupled to the drain of NMOS transistor M4 through contact 312g.

[0214] Conductor 320n corresponds to Figure 2 Node n1. Conductor 320n is electrically coupled to the gate 305a of NMOS transistor M4 and PMOS transistor M3 through via 316p, conductor 320n is electrically coupled to the drain of PMOS transistor M1 through contact 312a, and conductor 320n is electrically coupled to the drain of NMOS transistor M2 through contact 312e.

[0215] Conductor 320° corresponds to Figure 2 The input pin of the input circuit 202 is configured to receive the signal IN. Conductor 320o is electrically coupled to the gate of NMOS transistor M2 and the gate of PMOS transistor M1 through via 316q.

[0216] Conductor 320p is electrically coupled to the active region (unmarked) via contacts 314a, 314b, 314c, 314d and 314e.

[0217] The number of other configurations, arrangements, or structures at other layout levels in conductor group 320 is within the scope of this disclosure.

[0218] Integrated circuit 300 also includes conductor group 322.

[0219] The conductor group 322 includes one or more of conductors 322a, 322b, 322c, or 322d extending in at least a first direction X or a second direction Y. In some embodiments, the conductor group is referred to as a power rail group.

[0220] Each conductor in conductor group 322 is separated from each other at least in the first direction X or the second direction Y.

[0221] Conductor group 322 overlaps with gate group 304, 305 or 306, a group of active regions 302, contact group 310, 312, 314 and via group 316. In some embodiments, conductor group 322 is located on a fifth layer.

[0222] Conductor group 322 overlaps with gate group 304, 305 or 306, a set of active regions 302, contact groups 310, 312, 314 and via group 316. Conductor group 322 is configured to supply power (VDDL, VDD or VSS) to one or more of the gate group 304, 305 or 306, the set of active regions 302, the contact groups 310, 312, 314 and via group 316.

[0223] Conductor 322a is configured to supply a reference voltage VSS to the source of NMOS transistors M18 and M6 via contact 310b, and to supply a reference voltage VSS to the source of NMOS transistor M14 via contact 310d. Conductor 322a is also configured to supply a reference voltage VSS to the body terminals of NMOS transistors M17, M18, M6, and M14 via contacts 314f and 314g.

[0224] Conductor 322a is electrically coupled to the source of NMOS transistors M18 and M6 through contact 310b, and conductor 322a is electrically coupled to the source of NMOS transistor M14 through contact 310d.

[0225] Conductor 322b is configured to supply a second power supply voltage VDD to the sources of PMOS transistors M15 and M5 via contact 310g, to the source of PMOS transistor M7_2 via contact 310m, and to the source of PMOS transistor M7_1 via contact 310n. Conductor 322b is also configured to supply the second power supply voltage VDD to the body terminals of PMOS transistors M10, M8, M7_2, M7_1, M9, and M11 via contacts 310i and 310j.

[0226] Conductor 322b is electrically coupled to the source of PMOS transistors M15 and M5 through contact 310g, and conductor 322b is electrically coupled to the source of PMOS transistor M7_2 through contact 310m, and electrically coupled to the source of PMOS transistor M7_1 through contact 310n.

[0227] Conductor 322c is configured to supply a reference voltage VSS to the source of NMOS transistor M12a via contact 310q, to ​​the source of NMOS transistor M13a via contact 310s, to the sources of NMOS transistors M12b and M13b via contact 310u, and to the sources of NMOS transistors M4 and M2 via contact 312f. Conductor 322c is also configured to supply a reference voltage VSS to the body terminals of NMOS transistors M12a, M13a, M13b, M12b, M4, and M2 via contacts 314h and 314i.

[0228] Conductor 322c is electrically coupled to the source of NMOS transistor M12a through contact 310q, and conductor 322c is electrically coupled to the source of NMOS transistor M13a through contact 310s, and conductor 322c is electrically coupled to the sources of NMOS transistors M13b and M13b through contact 310u, and conductor 322c is electrically coupled to the sources of NMOS transistors M4 and M2 through contact 312f.

[0229] Conductor 322d is configured to supply a first power supply voltage VDDL to the source terminals of PMOS transistors M3 and M1 via contact 312b. Conductor 322d is also configured to supply the first power supply voltage VDDL to the body terminals of PMOS transistors M3 and M1 via contact 312d.

[0230] Conductor 322d is electrically coupled to the source of PMOS transistors M3 and M1 through contact 312b.

[0231] The number of other configurations, arrangements or structures at other layout levels in conductor group 322 is within the scope of this disclosure.

[0232] Integrated circuit 300 also includes conductor group 330.

[0233] The conductor group 330 includes one or more of conductors 330a, 330b or 330c that extend at least in the first direction X.

[0234] Each conductor in conductor group 330 is separated from each other at least in the first direction X or the second direction Y.

[0235] Conductor group 330 overlaps with gate group 304, 305 or 306, a set of active regions 302, contact group 310, 312, 314, via group 316, and conductor group 320 or 322. In some embodiments, conductor group 330 is on a sixth level. In some embodiments, the sixth level is different from the first, second, third, fourth, and fifth levels. In some embodiments, the sixth level corresponds to the M2 level of integrated circuit 300. In some embodiments, the M2 level is higher than the OD level, POLY level, MD level, VG level, VD and V1 levels, and M1 level. Other levels are within the scope of this disclosure. In some embodiments, the fifth level corresponds to the M1 or M2 level of integrated circuit 300.

[0236] The conductor group 330 overlaps with the gate group 304, 305 or 306, a group of active regions 302, contact groups 310, 312, 314, via group 316 and conductor group 320 or 322.

[0237] The number of other configurations, arrangements, or structures at other layout levels in conductor group 330 is within the scope of this disclosure.

[0238] In some embodiments, at least one gate region of gate group 304, 305, or 306 is formed using doped or undoped polysilicon (or polysilicon). In some embodiments, at least one gate region of gate group 304, 305, or 306 comprises a metal, such as Al, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0239] In some embodiments, at least one conductor of contact group 310, 312, or 314, at least one conductor of conductor group 320, 322, or 330, and at least one via of via group 316 comprise one or more layers of conductive material, metal, metal compound, or doped semiconductor. In some embodiments, the conductive material comprises tungsten, cobalt, ruthenium, copper, or combinations thereof. In some embodiments, the metal comprises at least Cu (copper), Co, W, Ru, Al, etc. In some embodiments, the metal compound comprises at least AlCu, W-TiN, TiSix, NiSix, TiN, TaN, etc. In some embodiments, the doped semiconductor comprises at least doped silicon, etc.

[0240] Other materials, configurations, arrangements at other layout levels, or the number of elements in integrated circuit 300 are within the scope of this disclosure.

[0241] In some embodiments, integrated circuit 300 implements at least... Figures 1-2 and Figure 4 One or more advantages discussed in the text.

[0242] Figure 4 This is a circuit diagram of circuit 400 according to some embodiments. Circuit 400 is... Figure 1 An embodiment of the integrated circuit 100 is described, therefore a similar detailed description is omitted.

[0243] Circuit 400 is Figure 2 A variant of circuit 200, therefore a similar detailed description is omitted. Figure 2 Compared to circuit 200, enable circuit 404 replaces enable circuit 204, level shifter circuit 406 replaces level shifter circuit 206, and output circuit 408 replaces output circuit 208; therefore, similar detailed descriptions are omitted.

[0244] Circuit 400 includes input circuit 202, enable circuit 404, level shifter circuit 406 and output circuit 408.

[0245] and Figure 2Compared to enable circuit 204, enable circuit 404 also includes PMOS transistor M19 and NMOS transistor M20, therefore a similar detailed description is omitted.

[0246] The enable circuit 404 includes inverter 204a and inverter 404a. Inverter 404a includes PMOS transistor M19 and NMOS transistor M20.

[0247] Inverter 404a is coupled to inverter 204a via node n3, and to level shifter circuit 406 and output circuit 408 via node n7. Inverter 404a is configured to receive the signal SLEEP from inverter 204a and output the signal NSLEEPD to at least level shifter circuit 406 or output circuit 408. Inverter 404a is further coupled to a second voltage source node 2N. Inverter 404a is configured to operate in the VDD voltage domain. Inverter 404a is configured to generate the signal NSLEEPD in response to the signal SLEEP. The input terminals of inverter 404a are configured to receive the signal SLEEP from inverter 204a. The output terminals of inverter 404a are configured to output the signal NSLEEPD at node n7 to level shifter circuit 406 and output circuit 408. The output terminal of inverter 404a is coupled to level shifter circuit 406 and output circuit 408 at node n7.

[0248] The gate terminals of PMOS transistor M19 and NMOS transistor M20 are coupled together and configured as the input node (e.g., node n3) of inverter 404a. The gate terminals of PMOS transistor M19 and NMOS transistor M20 are coupled to the drain terminals of PMOS transistor M5 and NMOS transistor M6 via node n3. The gate terminals of PMOS transistor M19 and NMOS transistor M20 are configured to receive the SLEEP signal.

[0249] The source terminal of PMOS transistor M19 is coupled to a second voltage source node 2N having a second power supply voltage VDD. The source terminal of NMOS transistor M20 is coupled to a reference voltage source VSS. The body or body terminal of PMOS transistor M19 is coupled to a second voltage source node 2N having a second power supply voltage VDD. The body or body terminal of NMOS transistor M20 is coupled to a reference voltage source VSS.

[0250] The drain terminals of PMOS transistor M19 and NMOS transistor M20 are coupled together and configured as the output node (e.g., node n7) of output circuit 404. The drain terminals of PMOS transistor M19 and NMOS transistor M20 are configured to output the signal NSLEEPD at node n7.

[0251] Other transistor types or numbers in the enabling circuit 404 are within the scope of this disclosure.

[0252] and Figure 2 Compared to level shifter circuit 206, level shifter circuit 406 is disabled or enabled in response to signal NSLEEPD.

[0253] and Figure 2 Compared to the level shifter circuit 206, the level shifter circuit 406 uses an NMOS transistor M21 instead of a PMOS transistor M7, therefore a similar detailed description is omitted.

[0254] The level shifter circuit 206 includes PMOS transistors M8, M9, M10, and M11 and NMOS transistors M12, M13, and M21. Each of the PMOS transistors M8, M9, M10, and M11 and the NMOS transistors M12, M13, and M21 is configured to operate in the VDD voltage domain.

[0255] PMOS transistors M8, M9, M10, and M11 are part of region 406a of level shifter circuit 206. NMOS transistors M12, M13, and M21 are part of region 406b of level shifter circuit 206. Region 406a is similar to... Figure 2 Region 206a is used, therefore a similar detailed description is omitted. Region 406b is similar. Figure 2 Region 206b, therefore a similar detailed description is omitted.

[0256] and Figure 2 Compared to the level shifter circuit 206, Figure 4 The gate terminal of the NMOS transistor M12 and Figure 4 The gate terminal of the PMOS transistor M10 is configured to receive the input signal IBB, therefore a similar detailed description is omitted. Figure 4 The NMOS transistor M12 is turned on or off based on the input signal IBB. Figure 4 The PMOS transistor M10 is turned on or off based on the input signal IBB. The gate terminal of the PMOS transistor M10, the gate terminal of the NMOS transistor M12, the drain terminal of the PMOS transistor M3, the drain terminal of the NMOS transistor M4, and each of node n2 are coupled together.

[0257] and Figure 2 Compared to the level shifter circuit 206, Figure 4 The gate terminal of the NMOS transistor M13 and Figure 4 The gate terminal of the PMOS transistor M11 is configured to receive the input signal IB, therefore a similar detailed description is omitted. Figure 4 The NMOS transistor M13 is turned on or off based on the input signal IB. Figure 4 The PMOS transistor M11 is turned on or off based on the input signal IB. The gate terminal of the PMOS transistor M11, the gate terminal of the NMOS transistor M13, the drain terminal of the PMOS transistor M1, the drain terminal of the NMOS transistor M2, and each of node n1 are coupled together.

[0258] and Figure 2 Compared to the level shifter circuit 206, the level shifter circuit 404 excludes PMOS transistor M7, the source terminal of PMOS transistor M8, the source terminal of PMOS transistor M9, and node n4, which are coupled to a second voltage source node 2N having a second power supply voltage VDD.

[0259] and Figure 2 Compared to the level shifter circuit 206, the source terminals of NMOS transistor M21, NMOS transistor M12 and PMOS transistor M13 in the level shifter circuit 404 are not directly coupled to the reference voltage source VSS.

[0260] exist Figure 4 In the NMOS transistor M12, the source terminal and the source terminal of the PMOS transistor M13 are coupled together at node n8.

[0261] The NMOS transistor M21 is coupled between node n8 of the level shifter circuit 406 and the reference voltage source VSS. The voltage at node n8 corresponds to the voltage of the signal CCFT. The NMOS transistor M21 is also referred to as the pin circuit.

[0262] The source terminal of NMOS transistor M21 is coupled to a reference voltage source VSS having a second supply voltage VDD. The drain terminal of NMOS transistor M21, node n8, the source terminal of NMOS transistor M12, and the source terminal of NMOS transistor M13 are each coupled together. The body or body terminal of NMOS transistor M21 is coupled to the reference voltage source VSS.

[0263] The gate terminal of NMOS transistor M21 is coupled at node n7 to at least the drain terminal of PMOS transistor M19 and the drain terminal of NMOS transistor M20. The gate terminal of NMOS transistor M21 is configured to receive the signal NSLEEPD. NMOS transistor M21 is turned on or off based on the signal NSLEEPD. In response to being turned on by the signal NSLEEPD, NMOS transistor M21 electrically couples node n8 to a reference voltage source VSS, thereby setting the voltage of node n8 equal to that of the reference voltage source VSS. In response to being turned off by the signal NSLEEPD, NMOS transistor M21 electrically decouples node n8 and the reference voltage source VSS from each other.

[0264] Other transistor types or numbers in the level shifter circuit 406 are within the scope of this disclosure.

[0265] and Figure 2 Compared to the output circuit 208, the output circuit 408 replaces the NMOS transistor M14 with the PMOS transistor M22, and the output circuit 408 also includes PMOS transistors M23 and M24 as well as NMOS transistors M25 and M26, so similar detailed descriptions are omitted.

[0266] The output circuit 408 includes PMOS transistors M15, M16, M22, M23, and M24, and NMOS transistors M17, M18, M25, and M26. Each of the PMOS transistors M15, M16, M22, M23, and M24, and the NMOS transistors M17, M18, M25, and M26 is configured to operate in the VDD voltage domain.

[0267] Output circuit 408 is configured to receive at least signal NSLEEPD or a first signal SH1. Output circuit 408 is configured to generate output signals OUT1 and OUT2 in response to at least the first signal SH1 or signal NSLEEPD. Output circuit 408 is coupled at least to level shifter circuit 406, and to a second voltage source node 2N or a second node n6 of level shifter circuit 406.

[0268] Although PMOS transistor M22 is in Figure 4 While shown as part of output circuit 408, in some embodiments, PMOS transistor M22 is not part of output circuit 408. For example, in some embodiments, PMOS transistor M22 is part of level shifter circuit 406. In some embodiments, PMOS transistor M22 is neither part of level shifter circuit 406 nor part of output circuit 408.

[0269] PMOS transistor M22 is configured to set the voltage at the second node n6 corresponding to the first signal SH1. PMOS transistor M22 is coupled between node n6 of level shifter circuit 406 and node 2N of the second voltage source having the second power supply voltage VDD. PMOS transistor M22 is also referred to as the head circuit.

[0270] The source terminal of PMOS transistor M22 is coupled to the node of the second voltage source node 2N having the second power supply voltage VDD. The body or body terminal of PMOS transistor M22 is coupled to the node of the second voltage source node 2N having the second power supply voltage VDD.

[0271] The gate terminal of PMOS transistor M22 is coupled at node n7 to at least the drain terminal of NMOS transistor M19, the drain terminal of NMOS transistor M20, and the gate terminal of PMOS transistor M19. The gate terminal of PMOS transistor M22 is configured to receive the signal NSLEEPD. PMOS transistor M22 is turned on or off based on the signal NSLEEPD. In response to being turned on by the signal NSLEEPD, PMOS transistor M22 electrically couples node n6 to a node of the second voltage source node 2N having the second supply voltage VDD, thereby setting the voltage of node n6 to be equal to that of the second voltage source node 2N having the second supply voltage VDD. In response to being turned off by the signal NSLEEPD, PMOS transistor M22 couples node n6 and the drain terminal of PMOS transistor M22 with the second power supply voltage VDD, node n6, the gate terminal of PMOS transistor M8, the drain terminal of PMOS transistor M11, the drain terminal of NMOS transistor M13, the gate terminal of PMOS transistor M15, the gate terminal of PMOS transistor M16, the gate terminal of NMOS transistor M17, and the gate terminal of NMOS transistor M18 together.

[0272] and Figure 2 Compared to the output circuit 208, Figure 4 The output node ND0 of the output circuit 208 is coupled to the input of the circuit 408b, so a similar detailed description is omitted.

[0273] PMOS transistors M23 and M24, and NMOS transistors M25 and M26 are coupled to the drain terminal of PMOS transistor M16, the drain terminal of NMOS transistor M17, and the output node ND0 of output circuit 208. PMOS transistors M23 and M24, and NMOS transistors M25 and M26 are configured to generate output signal OUT2 in response to at least output signal OUT1.

[0274] Each of the gate terminals of PMOS transistor M23, PMOS transistor M24, NMOS transistor M25, and NMOS transistor M26 is at least coupled to the drain terminal of PMOS transistor M16, the drain terminal of NMOS transistor M17, and the output node ND0 of output circuit 208.

[0275] Each of the gate terminals of PMOS transistor M23, PMOS transistor M24, NMOS transistor M25, and NMOS transistor M26 is configured to receive the output signal OUT1. Each of PMOS transistors M23, M24, M25, and M26 is configured to be turned on or off based on the output signal OUT1. In some embodiments, PMOS transistors M23-M24 and NMOS transistors M25-M26 function as inverters.

[0276] For example, in some embodiments, if output signal OUT1 is logically high, PMOS transistors M23 and M24 are turned off, NMOS transistors M25 and M26 are turned on, and output signal OUT2 is logically low. For example, in some embodiments, if output signal OUT1 is logically low, PMOS transistors M23 and M24 are turned on, NMOS transistors M25 and M26 are turned off, and output signal OUT2 is logically high.

[0277] The source terminal of PMOS transistor M23 is coupled to the second voltage source node 2N. The drain terminal of PMOS transistor M23 is coupled to the source terminal of PMOS transistor M24. At least the body or body terminal of PMOS transistor M23 or the body or body terminal of PMOS transistor M24 is coupled to the second voltage source node 2N.

[0278] The drain terminals of PMOS transistor M24 and NMOS transistor M25 are coupled together and correspond to the output node ND1 of output circuit 408. Output node ND1 of output circuit 408 has an output signal OUT2.

[0279] The source terminal of NMOS transistor M25 and the drain terminal of NMOS transistor M26 are coupled to each other. The source terminal of NMOS transistor M26 is coupled to at least the reference voltage source node VSS. At least the body or body terminal of NMOS transistor M25 or the body or body terminal of NMOS transistor M26 is coupled to the reference voltage source VSS.

[0280] Other transistor types or numbers in the output circuit 408 are within the scope of this disclosure.

[0281] Circuit 400 is configured to operate in either a first mode or a second mode. For example, in the first mode, level shifter circuit 406 is enabled or activated, and output signal OUT2 corresponds to the level-shifted form of input signal IN. In the second mode, level shifter circuit 406 is disabled or in sleep mode, and output signal OUT2 is either a high logic value or a low logic value.

[0282] In some embodiments, the level shifter circuit 406 is enabled or turned on by a signal NSLEEP equal to a high logic value (e.g., "1"). In some embodiments, the level shifter circuit 406 is disabled or turned off by a signal NSLEEP equal to a low logic value (e.g., "0"). Other values ​​of the signal NSLEEP that cause the level shifter circuit 406 to be enabled or turned on are within the scope of this disclosure. Other values ​​of the signal NSLEEP that cause the level shifter circuit 406 to be disabled or turned off are within the scope of this disclosure.

[0283] In some embodiments, when the level shifter circuit 406 is disabled or in sleep mode, the PMOS transistor M22 is enabled or turned on, and the circuit 400 is configured to output a low logic value (e.g., "0"), regardless of the value of at least the input signals IN, IBB, or IBB. For example, in some embodiments, if the signal NSLEEP has a low logic value (e.g., "0"), the signal SLEEP has a high logic value (e.g., "1"), and the signal NSLEEPD has a low logic value (e.g., "0"), thereby disabling the NMOS transistor M21 and the level shifter circuit 406, and thereby enabling or turning on the PMOS transistor M22. In response to the PMOS transistor M22 being enabled or turned on, the PMOS transistor M22 pulls the voltage of node n6 towards the second supply voltage VDD, thereby setting the voltage of the first signal SH1 to equal the high logic value. In response to the voltage of the first signal SH1 being equal to a high logic value, NMOS transistors M17 and M18 are turned on, pulling the voltage of output node ND0 towards the reference voltage VSS, thereby setting the voltage of output signal OUT1 to be equal to a low logic value. In response to the voltage of output signal OUT1 being equal to a low logic value, PMOS transistors M23 and M24 are turned on, pulling the voltage of output node ND1 towards the second power supply voltage VDD, thereby setting the voltage of output signal OUT2 to be equal to a high logic value.

[0284] In some embodiments, when the level shifter circuit 406 is enabled or activated, the PMOS transistor M22 is disabled or turned off, and the circuit 400 is configured to output an output signal OUT2 corresponding to the level shifted form of the input signal IN (e.g., the first signal SH1).

[0285] For example, in some embodiments, if the signal NSLEEP has a high logic value (e.g., "1"), the signal SLEEP has a low logic value (e.g., "0"), and the signal NSLEEPD has a high logic value (e.g., "1"), thereby enabling the NMOS transistor M21 and the level shifter circuit 406, and disabling or turning off the PMOS transistor M22.

[0286] In response to NMOS transistor M21 being enabled or turned on, NMOS transistor M21 pulls the voltage of node n8 towards the reference voltage VSS, thereby setting the voltage of node n8 (e.g., the signal CCHD) to be equal to the reference voltage VSS. In response to PMOS transistor M22 being disabled or turned off, PMOS transistor M22 will not set the voltage of node n6. In these embodiments, the voltage of node n6 will be set based on the value of the input signal IN by: (1) NMOS transistors M13 and M21 or (2) PMOS transistors M9 and M11.

[0287] For example, in these embodiments, when the input signal IN has a low logic value (e.g., "0"), the input signal IB has a high logic value (e.g., "1"), and the input signal IBB has a low logic value (e.g., "0"). In response to the input signal IB being a high logic value (e.g., "1"), NMOS transistor M13 is turned on and electrically couples the second node n6 and node n8 together. In some embodiments, by electrically coupling the second node n6 and node n8 together, NMOS transistors M13 and M21 pull the voltage of the second node n6 towards the reference voltage VSS, thereby setting the voltage of the first signal SH1 to be equal to a low logic value. In response to the voltage of the first signal SH1 being equal to a low logic value, PMOS transistors M15 and M16 are turned on and pull the voltage of the output node ND0 towards the second power supply voltage VDD, thereby setting the voltage of the output signal OUT1 to be equal to a high logic value. In response to the output signal OUT1 having a high logic value, NMOS transistors M25 and M26 are turned on, pulling the voltage at output node ND1 towards the reference voltage VSS, thereby setting the voltage of output signal OUT2 to a low logic value. Therefore, when the input signal IN has a low logic value (e.g., "0") in the VDDL domain, the output signal OUT2 is a level-shifted form of the input signal IN and is equal to a low logic value in the VDD domain.

[0288] For example, in these embodiments, when the input signal IN has a high logic value (e.g., "1"), the input signal IB has a low logic value (e.g., "0"), and the input signal IBB has a high logic value (e.g., "1").

[0289] In response to the input signal IBB being a high logic value (e.g., "1"), PMOS transistor M10 is turned off and NMOS transistor M12 is turned on, thereby electrically coupling the first node n5 and node n8 together. In some embodiments, by electrically coupling the first node n5 and node n8 together, NMOS transistors M12 and M21 pull the voltage of the first node n5 towards the reference voltage VSS, thereby setting the voltage of the second signal SH2 to equal a low logic value and setting the gate voltage of PMOS transistor M9 to equal a low logic value. In response to the gate voltage of PMOS transistor M9 being equal to a low logic value, PMOS transistor M9 is turned on, thereby electrically coupling the source terminal of PMOS transistor M11 to node n4 and the second power supply VDD.

[0290] In response to the input signal IB being a low logic value (e.g., "0"), NMOS transistor M13 is turned off and PMOS transistor M11 is turned on. However, since node n4 and the second power supply VDD are electrically coupled to the source terminal of PMOS transistor M11, turning on PMOS transistor M11 causes node n4 and the second power supply VDD to be electrically coupled to the second node n6. By electrically coupling node n4 and the second power supply VDD to the second node n6, one or more of PMOS transistors M9 or M11 pull the voltage of the second node n6 towards the second power supply voltage VDD, thereby setting the voltage of the first signal SH1 to be equal to a high logic value.

[0291] In response to the voltage of the first signal SH1 being equal to a high logic value, NMOS transistors M17 and M18 are turned on, pulling the voltage of output node ND0 towards the reference supply voltage VSS, thereby setting the voltage of output signal OUT1 to be equal to a low logic value. In response to the voltage of output signal OUT1 being equal to a low logic value, PMOS transistors M23 and M24 are turned on, pulling the voltage of output node ND2 towards the second voltage source VDD, thereby setting the voltage of output signal OUT2 to be equal to a high logic value. Therefore, when the input signal IN has a high logic value (e.g., "1") in the VDDDL domain, the output signal OUT2 is a level-shifted form of the input signal IN and is equal to a high logic value in the VDD domain.

[0292] The signals NSLEEPD, NSLEEP, and SLEEP in the level shifter circuit 406 and the output circuit 408, as well as other values ​​for transistor type or configuration, are within the scope of this disclosure.

[0293] In some embodiments, each transistor in region 406b of the level shifter circuit 406 has a second threshold voltage. In some embodiments, each transistor in region 406b of the level shifter circuit 406 corresponds to a high threshold voltage device.

[0294] In some embodiments, each transistor in region 406a of the enable circuit 404, the output circuit 408, and the level shifter circuit 406 has a third threshold voltage. In some embodiments, each transistor in region 406a of the enable circuit 404, the output circuit 408, and the level shifter circuit 406 corresponds to an ultra-high threshold voltage device.

[0295] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first work function difference; NMOS transistors M6, M17, M18, M20, M25, and M26, having a second threshold voltage, have a corresponding second work function difference; and NMOS transistors M12, M13, and M21, having a third threshold voltage, have a corresponding third work function difference. In some embodiments, the first work function difference is less than the second and third work function differences. In some embodiments, the second work function difference is less than the third work function difference.

[0296] In some embodiments, PMOS transistors M1 and M3, which have a first threshold voltage, have a corresponding fourth work function difference, and PMOS transistors M5, M8, M9, M10, M11, M15, M16, M19, M22, M23, and M24, which have a second threshold voltage, have a corresponding fifth work function difference. In some embodiments, the fourth work function difference is greater than the fifth work function difference.

[0297] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first gate oxide thickness; NMOS transistors M6, M17, M18, M20, M25, and M26, having a second threshold voltage, have a corresponding second gate oxide thickness; and NMOS transistors M12, M13, and M21, having a third threshold voltage, have a corresponding third gate oxide thickness. In some embodiments, the first gate oxide thickness is less than the second and third gate oxide thicknesses. In some embodiments, the second gate oxide thickness is less than the third gate oxide thickness.

[0298] In some embodiments, PMOS transistors M1 and M3 having a first threshold voltage have a corresponding fourth gate oxide thickness, and PMOS transistors M5, M8, M9, M10, M11, M15, M16, M19, M22, M23, and M24 having a second threshold voltage have a corresponding fifth gate oxide thickness. In some embodiments, the fourth gate oxide thickness is less than the fifth gate oxide thickness.

[0299] In some embodiments, NMOS transistors M2 and M4, having a first threshold voltage, have a corresponding first P-type dopant concentration in their channels; NMOS transistors M6, M17, M18, M20, M25, and M26, having a second threshold voltage, have a corresponding second P-type dopant concentration in their channels; and NMOS transistors M12, M13, and M21, having a third threshold voltage, have a corresponding third P-type dopant concentration in their channels. In some embodiments, the first P-type dopant concentration in the channel is less than the second P-type dopant concentration and the third P-type dopant concentration in the channel. In some embodiments, the second P-type dopant concentration in the channel is less than the third P-type dopant concentration in the channel.

[0300] In some embodiments, by configuring the level shifter circuit 406 to include regions 406a and 406b with different threshold voltages, leakage current in the first path P1 or the second path P2 is reduced, thereby reducing the power consumption of the circuit 400 compared to other methods with higher leakage current and greater power consumption.

[0301] In some embodiments, by configuring the level shifter circuit 406 as a pin circuit (e.g., an NMOS transistor M21), leakage current in the first path P1 or the second path P2 is reduced when the level shifter circuit 406 is disabled or in a sleep mode, thereby reducing the power consumption of the circuit 400 compared to other methods with higher leakage current and greater power consumption.

[0302] Figures 5A-5B This is a flowchart of a method 500 for operating circuitry according to some embodiments. It should be understood that... Figures 5A-5B Additional operations are performed before, during, and / or after method 500 as shown herein; only some other procedures are briefly described herein. It should be understood that method 500 utilizes the corresponding... Figure 1 or Figures 3A-3D Integrated circuits 100 or 300, corresponding Figure 2 or Figure 4 Features of one or more of circuits 200 or 400. In some embodiments, method 500 is a method of operating at least integrated circuit 100 or 300, or at least circuit 200 or 400.

[0303] In operation 502 of method 500, at least a first enable signal or a group of input signals is received via level shifter circuit 206 or 406. In some embodiments, the first enable signal includes at least the signal SLEEP or the signal NSLEEPD. In some embodiments, the group of input signals includes at least the input signal IB or the input signal IBB.

[0304] In operation 504 of method 500, the level shifter circuit is enabled in response to a first enable signal. In some embodiments, operation 504 includes at least one or more of operations 506 or 508.

[0305] In operation 506 of method 500, in response to at least a first enable signal, a first circuit in a first path or a second path of at least a level shifter circuit is enabled, thereby electrically coupling the first path or the second path to a first voltage source (e.g., VDD) or a first reference power supply (e.g., VSS).

[0306] In some embodiments, the first circuit of method 500 includes at least a PMOS transistor M7 or an NMOS transistor M21. In some embodiments, the first path of method 500 includes at least path P1. In some embodiments, the second path of method 500 includes at least path P2.

[0307] In operation 508 of method 500, a first signal is generated in response to at least a first input signal. In some embodiments, the first signal of method 500 includes at least signal SH1 or signal SH2. In some embodiments, the first input signal of method 500 includes at least input signal IB or input signal IBB. In some embodiments, the first input signal has a first voltage swing. In some embodiments, the first signal has a second voltage swing different from the first voltage swing.

[0308] In operation 510 of method 500, the second circuit is disabled in response to a first enable signal. In some embodiments, the second circuit of method 500 includes at least a PMOS transistor M22 or an NMOS transistor M14. In some embodiments, the second circuit is coupled to a first output node (e.g., node n6) of a level shifter circuit.

[0309] In operation 512 of method 500, the level shifter circuit is disabled in response to a first enable signal. In some embodiments, operation 512 includes at least one or more of operations 514.

[0310] In operation 514 of method 500, in response to at least a first enable signal, a first circuit in at least a first path or a second path of a level shifter circuit is disabled, thereby electrically decoupling the first path or the second path from a first voltage source (e.g., VDD) or a first reference power supply (e.g., VSS).

[0311] In operation 516 of method 500, the second circuit is enabled in response to the first enable signal.

[0312] In operation 518 of method 500, a first signal is set in response to enabling the second circuit. In some embodiments, the first signal is set by the second circuit in response to operation 516.

[0313] In operation 520 of method 500, an output signal is generated in response to at least a first enable signal or a first signal. In some embodiments, the output signal of operation 520 is generated by output circuit 208 or 408. In some embodiments, the output signal of method 500 includes at least output signal OUT1 or output signal OUT2.

[0314] In some embodiments, one or more operations of method 500 are not performed.

[0315] also, Figures 2-4 The various PMOS or NMOS transistors shown are of specific dopant types (e.g., N-type or P-type) for illustrative purposes. The embodiments of this disclosure are not limited to specific transistor types, and... Figures 2-4 One or more PMOS or NMOS transistors shown can be replaced by corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values ​​of various signals used in the above description are also for illustration. Embodiments of the invention are not limited to specific logic values ​​when activating and / or deactivating signals. Different logic values ​​are selected within the range of various embodiments. Different numbers of inverters are selected in input circuit 202 within the range of various embodiments. Different numbers of inverters are selected in enable circuit 204 or 404 within the range of various embodiments. Different numbers of transistors are selected in output circuit 208 or 408 within the range of various embodiments. Different numbers of transistors are selected in circuits 200, 300, or 400 within the range of various embodiments.

[0316] Figure 6 This is a flowchart of a method 600 for forming or manufacturing an integrated circuit according to some embodiments. It should be understood that... Figure 6 Additional operations are performed before, during, and / or after the method 600 shown, and some other operations may be described only briefly herein. In some embodiments, the method 600 may be used to form an integrated circuit, such as at least integrated circuit 100 or 300 or at least circuit 200 or 400.

[0317] In operation 602 of method 600, a layout design for an integrated circuit is generated. This is performed by a processing device (e.g., processor 802) configured to execute instructions for generating the layout design. Figure 8 )) Perform operation 602. In some embodiments, the layout design of method 600 includes one or more structures or features similar to at least integrated circuit 300. In some embodiments, the layout design of this application adopts a Graphical Database System (GDSII) file format.

[0318] In operation 604 of method 600, an integrated circuit is manufactured based on a layout design. In some embodiments, operation 604 of method 600 includes manufacturing at least one mask based on a layout design, and manufacturing an integrated circuit based on the at least one mask.

[0319] In some embodiments, operation 604 results in the formation of integrated circuit 300. In some embodiments, at least one of operations 602 or 604 is not performed.

[0320] Figure 7 This is a flowchart of a method 700 for generating an integrated circuit layout design according to some embodiments. It should be understood that... Figure 7 Additional operations are performed before, during, and / or after method 700, and only some other processes are briefly described herein. In some embodiments, method 700 is an embodiment of operation 602 of method 600. In some embodiments, method 700 can be used to generate one or more layout patterns similar to at least integrated circuit 300.

[0321] In some embodiments, method 700 can be used to generate one or more layout patterns (having alignment, length, and width structural relationships) and at least the configuration and layers of integrated circuit 300, and for the sake of brevity, Figure 7 The lieutenant general did not provide a similar detailed description.

[0322] In operation 702 of method 700, a set of active region patterns is generated or placed on a layout design. In some embodiments, the set of active region patterns of method 700 includes one or more regions similar to a set of active regions 302. In some embodiments, the set of active region patterns of method 700 includes one or more active regions in an OD layer.

[0323] In operation 704 of method 700, a group of gate patterns is generated or placed on a layout design. In some embodiments, the group of gate patterns in method 700 includes one or more gate patterns similar to at least gate groups 304, 305, or 306. In some embodiments, the group of gate patterns in method 700 includes one or more gates in a POLY layer.

[0324] In operation 706 of method 700, a group of contact patterns is generated or placed on a layout design. In some embodiments, the group of contact patterns in method 700 includes one or more contacts similar to at least contact groups 310, 312, or 314. In some embodiments, the group of contact patterns in method 700 includes one or more vias in a VD layer similar to contact groups 310, 312, or 314.

[0325] In operation 708 of method 700, a first via pattern group is generated or placed on a layout design. In some embodiments, the first via pattern group of method 700 includes one or more via patterns similar to at least via group 316. In some embodiments, the first via pattern group of method 700 includes one or more vias similar to vias in at least a VG layer.

[0326] In operation 710 of method 700, a first conductive pattern set is generated or placed on a layout design. In some embodiments, the first conductive pattern set of method 700 includes one or more conductors similar to at least conductor group 320. In some embodiments, the first conductive pattern set of method 700 includes one or more conductors similar to conductors in at least M0 or M1 layers.

[0327] In operation 712 of method 700, a second conductive pattern set is generated or placed on a layout design. In some embodiments, the second conductive pattern set of method 700 includes one or more conductors similar to at least conductor group 322. In some embodiments, the second conductive pattern set of method 700 includes one or more conductors similar to conductors in at least layer M0 or M1.

[0328] In operation 714 of method 700, a second via pattern set is generated or placed on a layout design. In some embodiments, the second via pattern set of method 700 includes one or more via patterns resembling vias between layers M0 and M1 or between layers M1 and M2. In some embodiments, the second via pattern set of method 700 includes one or more vias resembling vias in at least layer V1.

[0329] In operation 716 of method 700, a third conductive pattern set is generated or placed on a layout design. In some embodiments, the third conductive pattern set of method 700 includes one or more conductors similar to at least conductor group 330. In some embodiments, the third conductive pattern set of method 700 includes one or more conductors similar to conductors in at least layer M1 or M2.

[0330] One or more operations of methods 600-700 are performed by a processing device configured to execute instructions for manufacturing an integrated circuit (e.g., at least integrated circuit 300). In some embodiments, the processing device used to perform one or more operations of methods 600-700 is the same as the processing device used in one or more different operations of methods 600-700. In some embodiments, different processing devices are used to perform one or more operations of methods 600-700, and different processing devices are used to perform different one or more operations of methods 600-700. In some embodiments, the order of other operations of methods 500, 600, or 700 is within the scope of this disclosure. Methods 500, 600, or 700 include exemplary operations, but the operations are not necessarily performed in the order shown. Operations in methods 500, 600, or 700 may be appropriately added, substituted, rearranged, and / or eliminated according to the spirit and scope of the disclosed embodiments.

[0331] Figure 8 This is a schematic diagram of a system 800 for designing IC layout and manufacturing IC circuits according to some embodiments.

[0332] In some embodiments, system 800 generates or places one or more IC layout designs as described herein. System 800 includes a hardware processor 802 and a non-transitory computer-readable storage medium 804 (e.g., memory 804) encoded with computer program code 806 (i.e., a set of executable instructions 806), i.e., storing computer program code 806. Computer-readable storage medium 804 is configured to interface with manufacturing machines used to produce integrated circuits. Processor 802 is electrically coupled to computer-readable storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable storage medium 804 to be connected to external components via network 814. The processor 802 is configured to execute computer program code 806 encoded in a computer-readable storage medium 804 so that the system 800 can be used to perform some or all of the operations described in methods 600-700.

[0333] In some embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0334] In some embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0335] In some embodiments, storage medium 804 stores computer program code 806 configured to cause system 800 to perform methods 600-700. In some embodiments, storage medium 804 also stores information required to perform methods 600-700, as well as information generated during the performance of methods 600-700, such as layout design 816, user interface 818, and manufacturing tool 820, and / or a set of executable instructions for performing the operations of methods 600-700. In some embodiments, layout design 816 includes one or more layout patterns of at least layout design 100 or 300, or features similar to at least integrated circuit 300.

[0336] In some embodiments, storage medium 804 stores instructions (e.g., computer program code 806) for interfacing with a manufacturing machine. The instructions (e.g., computer program code 806) enable processor 802 to generate manufacturing instructions readable by the manufacturing machine to efficiently implement methods 600-700 during the manufacturing process.

[0337] System 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In some embodiments, the I / O interface 810 includes a keyboard, buttons, a mouse, a trackball, a trackpad, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0338] System 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with a network 814 connected to one or more other computer systems. Network interface 812 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-2094. In some embodiments, methods 600-700 are implemented in two or more systems 800, and information such as layout design and user interface is exchanged between the different systems 800 via network 814.

[0339] System 800 is configured to receive information related to a layout design via I / O interface 810 or network interface 812. This information is transmitted to processor 802 via bus 808 to determine a layout design for generating at least integrated circuit 300. The layout design is then stored as layout design 816 in computer-readable medium 804. System 800 is configured to receive information related to a user interface via I / O interface 810 or network interface 812. This information is stored as user interface 818 in computer-readable medium 804. System 800 is configured to receive information related to a manufacturing tool 820 via I / O interface 810 or network interface 812. This information is stored as manufacturing tool 820 in computer-readable medium 804. In some embodiments, manufacturing tool 820 includes manufacturing information used by system 800. In some embodiments, manufacturing tool 820 corresponds to... Figure 9 Mask manufacturing 934.

[0340] In some embodiments, methods 600-700 are implemented as a standalone software application executed by a processor. In some embodiments, methods 600-700 are implemented as a software application as part of an additional software application. In some embodiments, methods 600-700 are implemented as a plug-in to a software application. In some embodiments, methods 600-700 are implemented as a software application as part of an EDA tool. In some embodiments, methods 600-700 are implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout of an integrated circuit device. In some embodiments, the layout is stored on a non-transitory computer-readable medium. In some embodiments, a solution provided by companies such as CADENCE DESIGN SYSTEMS is used. The layout is generated using tools such as [tool name missing] or other suitable layout generation tools. In some embodiments, the layout is generated from a netlist created based on a schematic design. In some embodiments, methods 600-700 are implemented by a manufacturing apparatus to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 800. In some embodiments, system 800 is a manufacturing apparatus configured to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs of this disclosure. In some embodiments, Figure 8 The System 800 generates layout designs for integrated circuits that are smaller than those produced by other methods. In some embodiments, Figure 8 The layout design of the integrated circuit structure generated by System 800 occupies less area and provides better routing resources compared to other methods.

[0341] Figure 9This is a block diagram of an integrated circuit (IC) manufacturing system 900 and its associated IC manufacturing process according to at least one embodiment of the present disclosure. In some embodiments, based on the layout diagram, the manufacturing system 900 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0342] exist Figure 9 In this system, IC manufacturing system 900 (hereinafter referred to as "System 900") includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960, such as design room 920, mask room 930, and IC manufacturer / fab ("fab") 940. Entities in System 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, one or more of design room 920, mask room 930, and IC fab 940 are owned by a single, larger company. In some embodiments, one or more of design room 920, mask room 930, and IC fab 940 coexist in a shared facility and use shared resources.

[0343] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. Different layers combine to form different IC features. For example, a portion of IC design layout 922 includes various IC features to be formed in a semiconductor substrate (e.g., a silicon wafer), such as active regions, gate electrodes, source electrodes, and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, and various material layers disposed on the semiconductor substrate. Design studio 920 implements appropriate design procedures to form IC design layout 922. Design procedures include one or more of logic design, physical design, or location and routing. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 may be represented in GDSII file format or DFII file format.

[0344] Mask chamber 930 includes data preparation 932 and mask fabrication 934. Mask chamber 930 uses an IC design layout 922 to fabricate one or more masks 945 for fabricating various layers of an IC device 960 according to the IC design layout 922. Mask chamber 930 performs mask data preparation 932, where the IC design layout 922 is converted into a representative data file (RDF). Mask data preparation 932 provides the RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 945 or a semiconductor wafer 942. The design layout 922 is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 940. Figure 9 In this embodiment, mask data preparation 932 and mask manufacturing 934 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 934 may be collectively referred to as mask data preparation.

[0345] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may arise from diffraction, interference, or other process effects. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0346] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout that has been processed in the OPC. These mask creation rules include certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 934, and may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0347] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates a process performed by an IC fab 940 to manufacture an IC device 960. The LPC simulates this process based on an IC design layout 922 to create a simulated manufactured device, such as IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, if the simulated shape is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0348] It should be understood that, for clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features, such as logical operations (LOPs) that modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0349] After mask data preparation 932 and during mask fabrication 934, a mask 945 or a set of masks 945 is fabricated based on a modified IC design layout 922. In some embodiments, mask fabrication 934 includes performing one or more photolithographic exposures based on the IC design 922. In some embodiments, based on the modified IC design layout 922, a pattern is formed on the mask (photomask or photomask plate) 945 using an electron beam (e-beam) or a plurality of electron beams. The mask 945 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 945. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image-sensitive material layer (e.g., a photoresist) coated on the wafer is blocked by the opaque regions and transmits through the transparent regions. In one example, the binary form of the mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form the mask 945. In the phase-shift mask (PSM) form of mask 945, various features in the pattern formed on the mask are configured with appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. One or more masks generated by mask fabrication 934 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in a semiconductor wafer using etching processes and / or other suitable processes for forming various etched regions in the semiconductor wafer.

[0350] IC Fab 940 is an IC manufacturing entity, comprising one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC Fab 940 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for interconnecting and packaging the IC products, and a third manufacturing facility may provide additional services to the foundry entity.

[0351] IC fab 940 includes wafer fabrication tool 952 (hereinafter referred to as "fabrication tool 952") configured to perform various fabrication operations on semiconductor wafer 942 to fabricate IC device 960 according to one or more masks (e.g., mask 945). In various embodiments, fabrication tool 952 includes a wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other fabrication device capable of performing one or more suitable fabrication processes discussed herein.

[0352] IC fab 940 uses one or more masks 945 manufactured by mask chamber 930 to fabricate IC device 960. Therefore, IC fab 940 uses IC design layout 922 at least indirectly to fabricate IC device 960. In some embodiments, semiconductor wafer 942 is fabricated by IC fab 940 using one or more masks 945 to form IC device 960. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 922. Semiconductor wafer 942 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 942 also includes one or more various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0353] System 900 is shown as having design chamber 920, mask chamber 930, or IC fab 940 as separate components or entities. However, it is understood that one or more of design chamber 920, mask chamber 930, or IC fab 940 are part of the same component or entity.

[0354] Regarding integrated circuit (IC) manufacturing systems (such as...) Figure 9 Detailed information on the System 900 and its related IC manufacturing processes can be found in U.S. Patent No. 9,256,709, granted on February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published on October 1, 2015; U.S. Pre-Grant Publication No. 20100040838, published on February 6, 2014; and U.S. Patent No. 7,260442, granted on August 21, 2007, the entire contents of which are incorporated herein by reference.

[0355] One aspect of this specification relates to a circuit. The circuit includes an input circuit, a level shifter circuit, and an output circuit. In some embodiments, the input circuit is coupled to a first voltage source and configured to receive a first input signal and generate at least a second input signal or a third input signal. In some embodiments, the level shifter circuit is coupled to at least the input circuit and a second voltage source different from the first voltage source, and is configured to receive at least a first enable signal, a second input signal, or a third input signal, and generate at least a first signal in response to at least the first enable signal, the second input signal, or the third input signal. In some embodiments, the level shifter circuit includes a header circuit coupled to a first node of the level shifter circuit. In some embodiments, the header circuit is configured to receive a first enable signal. In some embodiments, the header circuit is configured to enable or disable the level shifter circuit in response to the first enable signal. In some embodiments, the output circuit is coupled to at least the level shifter circuit and a second voltage source, and is configured to receive the first signal and generate at least an output signal.

[0356] Another aspect of this specification relates to a circuit. The circuit includes an input circuit, a level shifter circuit, and an output circuit. In some embodiments, the input circuit is coupled to a first voltage source and configured to receive a first input signal having a first voltage swing and generate at least a second input signal or a third input signal. In some embodiments, the level shifter circuit is coupled to at least the input circuit and a second voltage source different from the first voltage source, and configured to generate at least a first signal in response to at least a first enable signal, the second input signal, or the third input signal, the first signal having a second voltage swing different from the first voltage swing. In some embodiments, the level shifter circuit includes a first circuit and a foot circuit. In some embodiments, the first circuit is coupled between the second voltage source and a first node of the level shifter circuit, and the first circuit has a first threshold voltage. In some embodiments, the foot circuit is coupled to the first node of the level shifter circuit, the foot circuit being configured to enable or disable the level shifter circuit in response to a first enable signal, the foot circuit having a second threshold voltage different from the first threshold voltage. In some embodiments, the output circuit is coupled to at least the level shifter circuit and the second voltage source, and configured to generate at least an output signal in response to the first signal.

[0357] Another aspect of this specification relates to a method of operating a circuit. The method includes enabling a level shifter circuit in response to a first enable signal. In some embodiments, enabling the level shifter circuit includes: enabling a first circuit in a first or second path of at least the level shifter circuit in response to at least the first enable signal, thereby electrically coupling the first or second path to a first voltage source or a first reference power supply; and generating a first signal in response to at least a first input signal, the first input signal having a first voltage swing and the first signal having a second voltage swing different from the first voltage swing. In some embodiments, the method further includes disabling a second circuit in response to the first enable signal, the second circuit being coupled to a first output node of the level shifter circuit. In some embodiments, the method includes generating an output signal by an output circuit in response to at least the first enable signal or the first signal.

[0358] Many embodiments have been described. However, it should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, various transistors shown as having a specific dopant type (e.g., N-type or P-type metal-oxide-semiconductor (NMOS or PMOS)) are for illustrative purposes. Embodiments of the invention are not limited to a specific type. Different dopant types are selected for specific transistors within the scope of various embodiments. The low or high logic values ​​of various signals used in the above description are also for illustrative purposes. Various embodiments are not limited to specific logic values ​​when a signal is activated and / or deactivated. Different logic values ​​are selected within the scope of various embodiments. In various embodiments, the transistor is used as a switch. Switching circuits used instead of transistors are within the scope of various embodiments. In various embodiments, the source of the transistor can be configured as the drain, and the drain can be configured as the source. Therefore, the terms "source" and "drain" can be used interchangeably. Various signals are generated by corresponding circuits, but for simplicity, the circuits are not shown.

[0359] Various figures illustrate capacitor circuits using discrete capacitors for illustrative purposes. Equivalent circuits may be used. For example, a capacitor device, circuit, or network (e.g., a combination of capacitors, capacitor elements, devices, circuits, etc.) may be used instead of a discrete capacitor. The above figures include exemplary steps, but these steps are not necessarily performed in the order shown. Steps may be added, substituted, changed in order, and / or deleted as appropriate, according to the spirit and scope of the disclosed embodiments.

[0360] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

[0361] Example 1 is an integrated circuit comprising: an input circuit coupled to a first voltage source and configured to receive a first input signal and generate at least a second input signal or a third input signal; a level shifter circuit coupled to at least the input circuit and a second voltage source different from the first voltage source and configured to receive at least a first enable signal, the second input signal, or the third input signal, and generate at least a first signal in response to at least the first enable signal, the second input signal, or the third input signal, the level shifter circuit comprising: a header circuit coupled to a first node of the level shifter circuit and configured to receive the first enable signal and configured to enable or disable the level shifter circuit in response to the first enable signal; and an output circuit coupled to at least the level shifter circuit and the second voltage source and configured to receive the first signal and generate at least an output signal.

[0362] Example 2 is the circuit described in Example 1, further comprising: an enable circuit coupled to the second voltage source and the level shifter circuit, and the enable circuit being configured to generate at least the first enable signal in response to receiving a second enable signal.

[0363] Example 3 is the circuit described in Example 2, wherein the enabling circuit includes: a first inverter including an input terminal and an output terminal, the input terminal being configured to receive a second enabling signal, and the output terminal being configured to output a first enabling signal, the first enabling signal being inverted from the second enabling signal.

[0364] Example 4 is the circuit described in Example 2, wherein the input circuit has a first threshold voltage; the enable circuit has a second threshold voltage different from the first threshold voltage; a first portion of the level shifter circuit has the second threshold voltage, and the first portion of the level shifter circuit includes the head circuit; a second portion of the level shifter circuit has a third threshold voltage different from the first threshold voltage and the second threshold voltage; and the output circuit has the second threshold voltage.

[0365] Example 5 is the circuit described in Example 1, wherein the level shifter circuit further includes: a first path coupled between the first node and a reference voltage source node having a reference power supply voltage; and a second path parallel to the first path, the second path being coupled between the first node and the reference voltage source node.

[0366] Example 6 is the circuit described in Example 5, wherein the first path includes: a first p-type transistor having a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor coupled to the first node and the head circuit; a second p-type transistor having a first terminal configured to receive the second input signal, and a second terminal of the second p-type transistor coupled to a third terminal of the first p-type transistor, and a third terminal of the second p-type transistor coupled to at least a second node; and a first n-type transistor having a first terminal configured to receive the second input signal, and a second terminal of the first n-type transistor coupled to the second node and the third terminal of the second p-type transistor, and a third terminal of the first n-type transistor coupled to the reference voltage source node.

[0367] Example 7 is the circuit described in Example 6, wherein the second path includes: a third p-type transistor having a first terminal configured to receive a second signal inversely phase to the first signal, and a second terminal of the third p-type transistor coupled to a first node of the first p-type transistor, the head circuit, and the second terminal; a fourth p-type transistor having a first terminal configured to receive the third input signal, the second terminal of the fourth p-type transistor coupled to a third terminal of the third p-type transistor, and the third terminal of the fourth p-type transistor coupled to at least a third node; and a second n-type transistor having a first terminal configured to receive the third input signal, the second terminal of the second n-type transistor coupled to the third node and the third terminal of the fourth p-type transistor, and the third terminal of the second n-type transistor coupled to the reference voltage source node.

[0368] Example 8 is the circuit described in Example 1, wherein the head circuit includes: a first p-type transistor having a first terminal configured to receive the first enable signal, a second terminal of the first p-type transistor coupled to a second voltage source having a first power supply voltage, and a third terminal of the first p-type transistor coupled to the first node.

[0369] Example 9 is the circuit described in Example 1, wherein the output circuit includes: a first p-type transistor having a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor coupled to the second voltage source; a second p-type transistor having a first terminal configured to receive the first signal, the second terminal of the second p-type transistor coupled to a third terminal of the first p-type transistor, and the third terminal of the second p-type transistor coupled to at least an output node; and a first n-type transistor having a first terminal configured to receive the first signal, and a second terminal of the first n-type transistor coupled to the output node and the third terminal of the second p-type transistor; and a second n-type transistor having a first terminal configured to receive the first signal, and a second terminal of the second n-type transistor coupled to the third terminal of the first n-type transistor, and the third terminal of the second n-type transistor coupled to a reference voltage source node.

[0370] Example 10 is the circuit described in Example 9, wherein the output circuit further includes: a third n-type transistor having a first terminal configured to receive the first enable signal, a second terminal of the third n-type transistor coupled to each of the first terminal of the first p-type transistor, the first terminal of the second p-type transistor, the first terminal of the first n-type transistor, and the first terminal of the second n-type transistor, and a third terminal of the third n-type transistor coupled to the reference voltage source node.

[0371] Example 11 is an integrated circuit comprising: an input circuit coupled to a first voltage source and configured to receive a first input signal having a first voltage swing and generate at least a second input signal or a third input signal; a level shifter circuit coupled to at least the input circuit and a second voltage source different from the first voltage source and configured to generate at least a first signal in response to at least a first enable signal, the second input signal, or the third input signal, the first signal having a second voltage swing different from the first voltage swing, the level shifter circuit comprising: a first circuit coupled between the second voltage source and a first node of the level shifter circuit, the first circuit having a first threshold voltage; and a foot circuit coupled to the first node of the level shifter circuit, the foot circuit being configured to enable or disable the level shifter circuit in response to the first enable signal, the foot circuit having a second threshold voltage different from the first threshold voltage; and an output circuit coupled to at least the level shifter circuit and the second voltage source, the output circuit being configured to generate at least an output signal in response to the first signal.

[0372] Example 12 is the circuit described in Example 11, wherein the foot circuit includes: a first n-type transistor having a first terminal configured to receive the first enable signal, a second terminal of the first n-type transistor coupled to the first node, and a third terminal of the first n-type transistor coupled to a reference voltage source node.

[0373] Example 13 is the circuit described in Example 11, further comprising: an enable circuit coupled to the second voltage source and the level shifter circuit, and the enable circuit being configured to generate at least the first enable signal in response to a second enable signal and a third enable signal.

[0374] Example 14 is the circuit described in Example 13, wherein the enabling circuit includes: a first inverter including a first input terminal and a first output terminal, the first input terminal being configured to receive a second enabling signal, and the first output terminal being configured to output the third enabling signal, the third enabling signal being inverted from the second enabling signal; and a second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal and configured to receive the third enabling signal, and the second output terminal being configured to output the first enabling signal, the first enabling signal being inverted from the third enabling signal.

[0375] Example 15 is the circuit described in Example 11, wherein the output circuit includes: a first p-type transistor having a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor coupled to a second voltage source; a second p-type transistor having a first terminal configured to receive the first signal, and a second terminal of the second p-type transistor coupled to a third terminal of the first p-type transistor, and the third terminal of the second p-type transistor coupled to at least a first output node; and a first n-type transistor having a first terminal configured to receive the first signal, and a second terminal of the first n-type transistor coupled to the first output node and the third terminal of the second p-type transistor; and a second n-type transistor having a first terminal configured to receive the first signal, and a second terminal of the second n-type transistor coupled to the third terminal of the first n-type transistor, and the third terminal of the second n-type transistor coupled to a reference voltage source node, wherein the third terminal of the second p-type transistor and the second terminal of the first n-type transistor are configured to output a first output signal at the first output node.

[0376] Example 16 is the circuit described in Example 15, wherein the output circuit further includes: a third p-type transistor having a first terminal configured to receive the first output signal, and a second terminal of the third p-type transistor coupled to the second voltage source; a fourth p-type transistor having a first terminal configured to receive the first output signal, the second terminal of the fourth p-type transistor coupled to a third terminal of the third p-type transistor, and the third terminal of the fourth p-type transistor coupled to at least a second output node; and a third n-type transistor having a first terminal configured to receive the first output signal, the second terminal of the third n-type transistor coupled to the second output node and the third terminal of the fourth p-type transistor; and a fourth An n-type transistor has a first terminal configured to receive the first output signal, a second terminal of the fourth n-type transistor coupled to a third terminal of the third n-type transistor, and the third terminal of the fourth n-type transistor coupled to the reference voltage source node; wherein each of the first terminal of the third p-type transistor, the first terminal of the fourth p-type transistor, the first terminal of the third n-type transistor, and the first terminal of the fourth n-type transistor is coupled to the first output node, the third terminal of the second p-type transistor, and the second terminal of the first n-type transistor, and the third terminal of the fourth p-type transistor and the second terminal of the third n-type transistor are configured to output the output signal at the second output node.

[0377] Example 17 is the circuit described in Example 16, wherein the output circuit further includes: a fifth p-type transistor having a first terminal configured to receive the first enable signal, a second terminal of the fifth p-type transistor coupled to each of the first terminal of the first p-type transistor, the first terminal of the second p-type transistor, the first terminal of the first n-type transistor, and the first terminal of the second n-type transistor, and a third terminal of the fifth p-type transistor coupled to the second voltage source.

[0378] Example 18 is the circuit described in Example 11, wherein the input circuit includes: a first inverter including a first input terminal and a first output terminal, the first input terminal being configured to receive the first input signal, and the first output terminal being configured to output a second input signal, the second input signal being inverted from the first input signal; and a second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal and configured to receive the second input signal, and the second output terminal being configured to output the third input signal, the third input signal being inverted from the second input signal.

[0379] Example 19 is a method of operating a circuit, the method comprising: enabling a level shifter circuit in response to a first enable signal, wherein enabling the level shifter circuit comprises: enabling a first circuit in a first path or a second path of at least the level shifter circuit in response to at least the first enable signal, thereby electrically coupling the first path or the second path to a first voltage source or a first reference power supply; generating a first signal in response to at least a first input signal, the first input signal having a first voltage swing and the first signal having a second voltage swing different from the first voltage swing; disabling a second circuit in response to the first enable signal, the second circuit being coupled to a first output node of the level shifter circuit; and generating an output signal by an output circuit in response to at least the first enable signal or the first signal.

[0380] Example 20 is the method of Example 19, further comprising: disabling the level shifter circuit in response to the first enable signal, wherein disabling the level shifter circuit comprises: disabling a first circuit in at least the first path or the second path of the level shifter circuit in response to at least the first enable signal, thereby electrically decoupling the first path or the second path from the first voltage source or the first reference power supply; enabling the second circuit in response to the first enable signal; and setting the first signal in response to enabling the second circuit.

Claims

1. An integrated circuit, comprising: An input circuit is coupled to a first voltage source and is configured to receive a first input signal and generate at least a second or a third input signal. A level shifter circuit, coupled to at least the input circuit and a second voltage source different from the first voltage source, and configured to receive at least a first enable signal, a second input signal, or the third input signal, and to generate at least a first signal in response to at least the first enable signal, the second input signal, or the third input signal, the level shifter circuit comprising: A head circuit, coupled to a first node of the level shifter circuit, is configured to receive the first enable signal and to enable or disable the level shifter circuit in response to the first enable signal. An output circuit, coupled to at least the level shifter circuit and the second voltage source, and the output circuit is configured to receive the first signal and generate at least an output signal; and An enabling circuit, coupled to the second voltage source and the level shifter circuit, is configured to generate at least the first enabling signal in response to receiving a second enabling signal. The input circuit has a first threshold voltage; The enabling circuit has a second threshold voltage that is different from the first threshold voltage; The first portion of the level shifter circuit has the second threshold voltage, and the first portion of the level shifter circuit includes the head circuit; The second part of the level shifter circuit has a third threshold voltage that is different from the first threshold voltage and the second threshold voltage.

2. The circuit according to claim 1, wherein, The enabling circuit includes: A first inverter includes an input terminal and an output terminal, the input terminal being configured to receive a second enable signal, and the output terminal being configured to output a first enable signal, the first enable signal being inverted from the second enable signal.

3. The circuit according to claim 1, wherein, The output circuit has the second threshold voltage.

4. The circuit according to claim 1, wherein, The level shifter circuit also includes: The first path is coupled between the first node and a reference voltage source node having a reference supply voltage; and The second path is parallel to the first path and is coupled between the first node and the reference voltage source node.

5. The circuit according to claim 4, wherein, The first path includes: A first p-type transistor has a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor is coupled to the first node and the head circuit. The second p-type transistor has a first terminal configured to receive the second input signal, and a second terminal of the second p-type transistor is coupled to a third terminal of the first p-type transistor, and the third terminal of the second p-type transistor is coupled to at least a second node; and The first n-type transistor has a first terminal configured to receive the second input signal, and a second terminal of the first n-type transistor is coupled to the second node and a third terminal of the second p-type transistor, and the third terminal of the first n-type transistor is coupled to the reference voltage source node.

6. The circuit according to claim 5, wherein, The second path includes: The third p-type transistor has a first terminal configured to receive a second signal that is inversely related to the first signal, and the second terminal of the third p-type transistor is coupled to a first node of the first p-type transistor, the head circuit and the second terminal; A fourth p-type transistor has a first terminal configured to receive the third input signal, a second terminal of the fourth p-type transistor coupled to a third terminal of the third p-type transistor, and the third terminal of the fourth p-type transistor coupled to at least a third node; and The second n-type transistor has a first terminal configured to receive the third input signal, a second terminal of the second n-type transistor is coupled to the third node and the third terminal of the fourth p-type transistor, and the third terminal of the second n-type transistor is coupled to the reference voltage source node.

7. The circuit according to claim 1, wherein, The head circuitry includes: A first p-type transistor has a first terminal configured to receive the first enable signal, a second terminal of the first p-type transistor coupled to a second voltage source having a first power supply voltage, and a third terminal of the first p-type transistor coupled to the first node.

8. The circuit according to claim 1, wherein, The output circuit includes: A first p-type transistor has a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor is coupled to the second voltage source; The second p-type transistor has a first terminal configured to receive the first signal, a second terminal of the second p-type transistor coupled to a third terminal of the first p-type transistor, and the third terminal of the second p-type transistor coupled to at least an output node; and A first n-type transistor has a first terminal configured to receive the first signal, and a second terminal of the first n-type transistor is coupled to the output node and a third terminal of the second p-type transistor; and The second n-type transistor has a first terminal configured to receive the first signal, and a second terminal of the second n-type transistor is coupled to a third terminal of the first n-type transistor, and the third terminal of the second n-type transistor is coupled to a reference voltage source node.

9. The circuit according to claim 8, wherein, The output circuit also includes: The third n-type transistor has a first terminal configured to receive the first enable signal, a second terminal of the third n-type transistor coupled to each of the first terminal of the first p-type transistor, the first terminal of the second p-type transistor, the first terminal of the first n-type transistor, and the first terminal of the second n-type transistor, and a third terminal of the third n-type transistor coupled to the reference voltage source node.

10. An integrated circuit, comprising: An input circuit is coupled to a first voltage source and is configured to receive a first input signal having a first voltage swing and generate at least a second or a third input signal. A level shifter circuit, coupled to at least the input circuit and a second voltage source different from the first voltage source, and the level shifter circuit is configured to generate at least a first signal in response to at least a first enable signal, a second input signal, or the third input signal, the first signal having a second voltage swing different from the first voltage swing, the level shifter circuit comprising: A first circuit is coupled between the second voltage source and a first node of the level shifter circuit, and the first circuit has a first threshold voltage; and A foot circuit, coupled to a first node of the level shifter circuit, the foot circuit being configured to enable or disable the level shifter circuit in response to a first enable signal, the foot circuit having a second threshold voltage different from the first threshold voltage; An output circuit, coupled to at least the level shifter circuit and the second voltage source, and the output circuit is configured to generate at least an output signal in response to the first signal; and An enabling circuit, coupled to the second voltage source and the level shifter circuit, is configured to generate at least the first enabling signal in response to a second enabling signal and a third enabling signal. The input circuit has a third threshold voltage that is different from the first threshold voltage and the second threshold voltage. The enabling circuit has the first threshold voltage.

11. The circuit according to claim 10, wherein, The foot circuitry includes: A first n-type transistor has a first terminal configured to receive the first enable signal, a second terminal of the first n-type transistor coupled to the first node, and a third terminal of the first n-type transistor coupled to a reference voltage source node.

12. The circuit according to claim 10, wherein, The enabling circuit includes: A first inverter includes a first input terminal and a first output terminal, the first input terminal being configured to receive a second enable signal, and the first output terminal being configured to output the third enable signal, the third enable signal being inverted compared to the second enable signal; and The second inverter includes a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal and configured to receive the third enable signal, and the second output terminal being configured to output the first enable signal, the first enable signal being inverted from the third enable signal.

13. The circuit according to claim 10, wherein, The output circuit includes: A first p-type transistor has a first terminal configured to receive the first signal, and a second terminal of the first p-type transistor is coupled to the second voltage source; The second p-type transistor has a first terminal configured to receive the first signal, and a second terminal of the second p-type transistor is coupled to a third terminal of the first p-type transistor, and the third terminal of the second p-type transistor is coupled to at least a first output node; and A first n-type transistor has a first terminal configured to receive the first signal, and a second terminal of the first n-type transistor is coupled to the first output node and a third terminal of the second p-type transistor; and The second n-type transistor has a first terminal configured to receive the first signal, and a second terminal of the second n-type transistor is coupled to a third terminal of the first n-type transistor, and the third terminal of the second n-type transistor is coupled to a reference voltage source node. The third terminal of the second p-type transistor and the second terminal of the first n-type transistor are configured to output a first output signal at the first output node.

14. The circuit according to claim 13, wherein, The output circuit also includes: The third p-type transistor has a first terminal configured to receive the first output signal, and a second terminal of the third p-type transistor is coupled to the second voltage source; A fourth p-type transistor has a first terminal configured to receive the first output signal, a second terminal of the fourth p-type transistor coupled to a third terminal of the third p-type transistor, and a third terminal of the fourth p-type transistor coupled to at least a second output node; and A third n-type transistor has a first terminal configured to receive the first output signal, and a second terminal of the third n-type transistor is coupled to the second output node and the third terminal of the fourth p-type transistor; and A fourth n-type transistor has a first terminal configured to receive the first output signal, a second terminal of the fourth n-type transistor coupled to a third terminal of the third n-type transistor, and a third terminal of the fourth n-type transistor coupled to the reference voltage source node; Wherein, each of the first terminal of the third p-type transistor, the first terminal of the fourth p-type transistor, the first terminal of the third n-type transistor, and the first terminal of the fourth n-type transistor is coupled to the first output node, the third terminal of the second p-type transistor, and the second terminal of the first n-type transistor, and The third terminal of the fourth p-type transistor and the second terminal of the third n-type transistor are configured to output the output signal at the second output node.

15. The circuit according to claim 14, wherein, The output circuit also includes: The fifth p-type transistor has a first terminal configured to receive the first enable signal, a second terminal of the fifth p-type transistor coupled to each of the first terminal of the first p-type transistor, the first terminal of the second p-type transistor, the first terminal of the first n-type transistor, and the first terminal of the second n-type transistor, and a third terminal of the fifth p-type transistor coupled to the second voltage source.

16. The circuit according to claim 10, wherein, The input circuit includes: A first inverter includes a first input terminal and a first output terminal, the first input terminal being configured to receive a first input signal, and the first output terminal being configured to output a second input signal, the second input signal being inverted compared to the first input signal; and The second inverter includes a second input terminal and a second output terminal, the second input terminal being coupled to the first output terminal and configured to receive the second input signal, and the second output terminal being configured to output the third input signal, the third input signal being inverted from the second input signal.

17. A method of operating a circuit, the method comprising: A level shifter circuit is enabled in response to a first enable signal, the first enable signal being generated by an enable circuit having a first threshold voltage, wherein enabling the level shifter circuit includes: In response to at least the first enable signal, a first circuit is enabled in a first or second path of at least the level shifter circuit, thereby electrically coupling the first or second path to a first voltage source or a first reference power supply, the first circuit having a second threshold voltage different from the first threshold voltage; and A first signal is generated in response to at least a first input signal, the first input signal having a first voltage swing and the first signal having a second voltage swing different from the first voltage swing, the first input signal being generated by an input circuit having a third threshold voltage different from the first threshold voltage and the second threshold voltage; In response to the first enable signal, the second circuit is disabled, the second circuit being coupled to the first output node of the level shifter circuit; and The output circuit generates an output signal in response to at least the first enable signal or the first signal.

18. The method of claim 17, further comprising: Disabling the level shifter circuit in response to the first enable signal, wherein disabling the level shifter circuit includes: In response to at least the first enable signal, disable the first circuit in the first path or the first circuit in the second path of at least the level shifter circuit, thereby electrically decoupling the first path or the second path from the first voltage source or the first reference power supply. The second circuit is enabled in response to the first enable signal; and The first signal is set in response to enabling the second circuit.

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