A high speed trigger control device and method
By designing a high-speed trigger control device with an integrated FPGA logic processing unit, and utilizing B-code time provided by a GPS/BeiDou receiver, the device enables free configuration and synchronous triggering of multiple high-speed cameras. This solves the problem of the lack of integrated configuration, triggering, and timing functions in existing technologies, and improves shooting accuracy and data analysis efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN TECH UNIV
- Filing Date
- 2023-04-25
- Publication Date
- 2026-07-14
AI Technical Summary
There is a lack of high-speed trigger control devices on the market that integrate configuration, triggering, and timing functions, making it impossible to achieve free control and synchronous shooting of multiple high-speed cameras.
A high-speed trigger control device was designed, including an FPGA logic processing unit, an input module, and an output module. It uses a GPS/BeiDou receiver to provide B-code time and combines it with key aircraft action signals to achieve free configuration and synchronous triggering of five high-speed cameras.
It enables the free configuration and synchronous shooting of multiple high-speed cameras, improving shooting accuracy, and can perform time synchronization based on GPS/BeiDou satellite signals, facilitating subsequent data analysis.
Smart Images
Figure CN116506725B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of testing technology, specifically relating to a high-speed trigger control device and method. Background Technology
[0002] The critical aircraft maneuvers such as door opening and closing, beam separation, and loss of connection are of paramount importance for flight testing. High-speed cameras capture images of relevant aircraft components after these maneuvers for flight test data processing. Currently, there is no high-speed trigger control device on the market that integrates configuration, triggering, and timing functions. Against this backdrop, this invention provides a high-speed trigger control device and method that enables free control of shooting from five camera positions, and can simultaneously analyze GPS / BeiDou time for timing synchronization of the high-speed cameras. Summary of the Invention
[0003] The present invention aims to address the above-mentioned problems by proposing a high-speed triggering control device and method.
[0004] The technical solution of this invention is as follows:
[0005] This invention proposes a high-speed trigger control device.
[0006] A high-speed trigger control device includes an FPGA logic processing unit; it also includes an input module and an output module connected to the FPGA logic processing unit.
[0007] The input module includes a B-code time input circuit, an input circuit for the mapping relationship between key aircraft actions and high-speed camera operation, and a key aircraft action signal input circuit.
[0008] The B-code time input circuit includes a GPS / BeiDou receiver, which connects to GPS / BeiDou satellite signals through the GPS / BeiDou interface on the device panel, and connects to the FPGA logic processing unit at the other end.
[0009] The input circuit for mapping the key aircraft maneuvers to the operation of the high-speed camera includes an interface circuit, which receives the mapping relationship between the key aircraft maneuvers and the operation of the high-speed camera through a serial port on the device panel.
[0010] The aircraft critical action signal input circuit is connected to the aircraft critical action signals, including the door opening / closing signal, the beam separation signal, and the loss of contact signal. The aircraft critical action signal input circuit includes a door opening / closing signal conditioning circuit, a beam separation signal conditioning circuit, and a loss of contact signal conditioning circuit. The door opening / closing signal is transmitted to the FPGA logic processing unit through the door opening / closing signal conditioning circuit, the beam separation signal is transmitted to the FPGA logic processing unit through the beam separation signal conditioning circuit, and the loss of contact signal is transmitted to the FPGA logic processing unit through the loss of contact signal conditioning circuit.
[0011] The output module includes a trigger drive circuit, a B-code conversion circuit, a high-speed camera working indicator light drive circuit, and an aircraft key action signal valid indicator light drive circuit for driving the high-speed camera. The input terminals of the trigger drive circuit, the B-code conversion circuit, the high-speed camera working indicator light drive circuit, and the aircraft key action signal valid indicator light drive circuit are all connected to the FPGA logic processing unit. The output terminals of the trigger drive circuit and the B-code conversion circuit are all connected to the high-speed camera. The output terminal of the high-speed camera working indicator light drive circuit is connected to the high-speed camera working indicator light, and the output terminal of the aircraft key action signal valid indicator light drive circuit is connected to the aircraft key action signal indicator light.
[0012] It also includes a power module, which is connected to the FPGA logic processing unit, the input module, and the output module.
[0013] The B-code conversion circuit includes a B-code generation circuit and a B-code allocation circuit connected in sequence; wherein, the B-code generation circuit is connected to the FPGA logic processing unit, and one end of the B-code allocation circuit is connected to the B-code generation circuit, and the other end is connected to the high-speed camera.
[0014] The system has five high-speed cameras, each corresponding to a trigger drive circuit and a high-speed camera working indicator light. The trigger drive circuit and the high-speed camera working indicator light are all one-to-one with the high-speed cameras. The B code allocation circuit is connected to each of the five high-speed cameras.
[0015] The power module includes a power conversion circuit and a secondary power conversion circuit connected in sequence. The input terminal of the power conversion circuit is connected to an external 28V airborne power supply, and the output terminal of the power conversion circuit is connected to the input terminal of the secondary power conversion circuit. The output terminal of the secondary power conversion circuit is connected to the input module, the output module, and the FPGA logic processing unit, respectively.
[0016] This invention proposes a high-speed trigger control method.
[0017] A high-speed trigger control method, using the high-speed trigger control device described above, the control method is as follows:
[0018] Step 1: Install 5 high-speed cameras on the aircraft;
[0019] The mapping relationship between three key aircraft maneuvers and the operation of five high-speed cameras is configured by computer. The configuration file for the mapping relationship is either pre-configured or pre-saved in the device. The mapping relationship is received through the serial port on the device panel and then converted into a 3.3V RS232 level signal through the interface circuit and sent to the FPGA logic processing unit.
[0020] Step 2: While triggering the high-speed camera to work, the GPS / BeiDou satellite signal provides the B code time for superposition. The B code time is parsed by the GPS / BeiDou receiver, and after parsing, it is processed into DC code signal by the FPGA logic processing unit. Then, it is converted into 1 AC code by the B code generation circuit, and then distributed into 5 channels by the B code distribution circuit, which are sent to high-speed cameras 1 to 5 respectively.
[0021] Step 3: The FPGA logic processing unit waits for the door opening signal transmitted by the door opening signal conditioning circuit, the beam separation signal transmitted by the beam separation signal conditioning circuit, and the disconnection signal transmitted by the disconnection signal conditioning circuit, and illuminates the corresponding aircraft key action signal valid indicator light.
[0022] Step 4: The FPGA logic processing unit generates a high-speed camera drive signal according to the mapping relationship, and then drives the corresponding high-speed camera to work by triggering the drive circuit, and lights up the high-speed camera's working indicator light.
[0023] In the mapping relationship, the three key aircraft actions include the door opening / closing signal, the beam separation signal, and the disconnection signal. The operation of the five high-speed cameras includes the working relationship and working time, which consists of a 2-bit array. The first bit is the correspondence, which can be 0 or 1; the second bit is the shooting time. When the first bit is 0, the second bit x=0. When the first bit is 1, the second bit x is an integer in milliseconds. 0 represents not working, and 1 represents working; as shown in the table below.
[0024] ;
[0025] The door switch signal is characterized by a ground signal of less than 0.7V and an amplitude of greater than 12V; the door opening signal is a rising edge signal, and the door closing signal is a falling edge signal. The beam separation signal is characterized by a rising edge pulse signal, a ground signal of less than 0.7V, and an amplitude of greater than 12V. The disconnection signal is characterized by a falling edge signal, a ground signal of less than 0.7V, and an amplitude of greater than 12V. The door switch signal conditioning circuit receives a door switch signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit. The beam separation signal conditioning circuit receives a beam separation signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit. The disconnection signal conditioning circuit receives a disconnection signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit.
[0026] Specifically, the FPGA logic processing unit illuminates the door switch signal indicator when the door switch signal changes from low to high or from high to low; illuminates the beam departure signal indicator when the beam departure signal changes from low to high; and illuminates the disconnection signal indicator when the disconnection signal changes from high to low.
[0027] When the aircraft key action signal valid indicator light driving circuit drives the aircraft key action signal indicator light, the aircraft key action signal valid indicator light driving circuit outputs a 500ms high level to light up the corresponding aircraft key action signal valid indicator light.
[0028] The power conversion circuit receives the onboard 28V power supply and converts it to 5V. The secondary power conversion circuit converts the 5V power supply to 3.3V, 2.5V, 1.25V and 1.2V. The 3.3V is used to power the FPGA logic processing unit, GPS / BeiDou receiver, interface circuit, aircraft key action signal input circuit, B code generation circuit and B code distribution circuit. The 2.5V, 1.25V and 1.2V are also used to power the FPGA logic processing unit.
[0029] The technical advantages of this invention are as follows:
[0030] 1) It can freely configure one or more of the five cameras to work when three key aircraft maneuvers are effective, and the shooting time can be configured.
[0031] 2) It can generate B codes based on GPS / BeiDou satellite signals, synchronize the timing with the high-speed camera, and overlay them onto the video footage for easier post-processing analysis; thus improving shooting accuracy.
[0032] 3) This invention can meet the trigger control of high-speed cameras for capturing three key aircraft maneuvers, but is not limited to these three signals. When the signal characteristics of other key aircraft maneuvers are consistent with the characteristics of these three signals, they can also be used to trigger high-speed camera capture. Attached Figure Description
[0033] Figure 1 A flowchart of a high-speed trigger control method is provided for an embodiment of the present invention.
[0034] Figure 2 This invention provides a diagram illustrating key aircraft motion characteristics of a high-speed trigger control device, as shown in this embodiment.
[0035] Figure 3 A schematic diagram of a high-speed trigger control device is provided for an embodiment of the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0037] Example 1
[0038] A high-speed trigger control device includes an FPGA logic processing unit; it also includes an input module and an output module connected to the FPGA logic processing unit.
[0039] The input module includes a B-code time input circuit, an input circuit for the mapping relationship between key aircraft actions and high-speed camera operation, and a key aircraft action signal input circuit.
[0040] The B-code time input circuit includes a GPS / BeiDou receiver, which connects to GPS / BeiDou satellite signals through the GPS / BeiDou interface on the device panel, and connects to the FPGA logic processing unit at the other end.
[0041] The input circuit for mapping the key aircraft maneuvers to the operation of the high-speed camera includes an interface circuit, which receives the mapping relationship between the key aircraft maneuvers and the operation of the high-speed camera through a serial port on the device panel.
[0042] The aircraft critical action signal input circuit is connected to the aircraft critical action signals, including the door opening / closing signal, the beam separation signal, and the loss of contact signal. The aircraft critical action signal input circuit includes a door opening / closing signal conditioning circuit, a beam separation signal conditioning circuit, and a loss of contact signal conditioning circuit. The door opening / closing signal is transmitted to the FPGA logic processing unit through the door opening / closing signal conditioning circuit, the beam separation signal is transmitted to the FPGA logic processing unit through the beam separation signal conditioning circuit, and the loss of contact signal is transmitted to the FPGA logic processing unit through the loss of contact signal conditioning circuit.
[0043] The output module includes a trigger drive circuit, a B-code conversion circuit, a high-speed camera working indicator light drive circuit, and an aircraft key action signal valid indicator light drive circuit for driving the high-speed camera. The input terminals of the trigger drive circuit, the B-code conversion circuit, the high-speed camera working indicator light drive circuit, and the aircraft key action signal valid indicator light drive circuit are all connected to the FPGA logic processing unit. The output terminals of the trigger drive circuit and the B-code conversion circuit are all connected to the high-speed camera. The output terminal of the high-speed camera working indicator light drive circuit is connected to the high-speed camera working indicator light, and the output terminal of the aircraft key action signal valid indicator light drive circuit is connected to the aircraft key action signal indicator light.
[0044] It also includes a power module, which is connected to the FPGA logic processing unit, the input module, and the output module.
[0045] The specific implementation process of this embodiment is as follows:
[0046] Step 1: Install the high-speed camera on the aircraft;
[0047] The mapping relationship between three key aircraft maneuvers and the operation of the high-speed camera is configured by computer. The configuration file for the mapping relationship is either pre-configured or pre-saved in the device. The mapping relationship is received through the serial port on the device panel and then converted into a 3.3V RS232 level signal through the interface circuit and sent to the FPGA logic processing unit.
[0048] Step 2: While the high-speed camera is activated, the GPS / BeiDou satellite signal provides B-code time for superposition. The B-code time is parsed by the GPS / BeiDou receiver, processed into DC code signal by the FPGA logic processing unit, and then converted into 1 AC code by the B-code conversion circuit and sent to the high-speed camera.
[0049] Step 3: The FPGA logic processing unit waits for the door opening signal transmitted by the door opening signal conditioning circuit, the beam separation signal transmitted by the beam separation signal conditioning circuit, and the disconnection signal transmitted by the disconnection signal conditioning circuit, and illuminates the corresponding aircraft key action signal valid indicator light.
[0050] Step 4: The FPGA logic processing unit generates a high-speed camera drive signal according to the mapping relationship, and then drives the high-speed camera to work by triggering the drive circuit, and lights up the high-speed camera's working indicator light.
[0051] Example 2
[0052] Based on Example 1, it also includes:
[0053] The B-code conversion circuit includes a B-code generation circuit and a B-code allocation circuit connected in sequence; wherein, the B-code generation circuit is connected to the FPGA logic processing unit, and one end of the B-code allocation circuit is connected to the B-code generation circuit, and the other end is connected to the high-speed camera.
[0054] The system has five high-speed cameras, each corresponding to a trigger drive circuit and a high-speed camera working indicator light. The trigger drive circuit and the high-speed camera working indicator light are all one-to-one with the high-speed cameras. The B code allocation circuit is connected to each of the five high-speed cameras.
[0055] The power module includes a power conversion circuit and a secondary power conversion circuit connected in sequence. The input terminal of the power conversion circuit is connected to an external 28V airborne power supply, and the output terminal of the power conversion circuit is connected to the input terminal of the secondary power conversion circuit. The output terminal of the secondary power conversion circuit is connected to the input module, the output module, and the FPGA logic processing unit, respectively.
[0056] Example 3
[0057] A high-speed trigger control method, as described in Embodiment 2 above, includes the following control method:
[0058] Step 1: Install 5 high-speed cameras on the aircraft;
[0059] The mapping relationship between three key aircraft maneuvers and the operation of five high-speed cameras is configured by computer. The configuration file for the mapping relationship is either pre-configured or pre-saved in the device. The mapping relationship is received through the serial port on the device panel and then converted into a 3.3V RS232 level signal through the interface circuit and sent to the FPGA logic processing unit.
[0060] Among them, the three key aircraft actions include the door opening / closing signal, the beam separation signal, and the loss of contact signal;
[0061] The operation of the 5 high-speed cameras includes their working relationship and working time, which consists of a 2-bit array. The first bit represents the correspondence and can be either 0 or 1; the second bit represents the shooting time. When the first bit is 0, the second bit x = 0; when the first bit is 1, the second bit x is an integer in milliseconds. 0 represents no operation, and 1 represents operation, as shown in the table below.
[0062] ;
[0063] Step 2: While triggering the high-speed camera to work, the GPS / BeiDou satellite signal provides the B code time for superposition. The B code time is parsed by the GPS / BeiDou receiver, and after parsing, it is processed into DC code signal by the FPGA logic processing unit. Then, it is converted into 1 AC code by the B code generation circuit, and then distributed into 5 channels by the B code distribution circuit, which are sent to high-speed cameras 1 to 5 respectively.
[0064] The specific process is as follows: The B code generation circuit converts the DC code signal OUT(6) into a 1-channel AC code signal; the B code distribution circuit distributes the 1-channel AC code signal into 5 channels of AC code signals: B code 1 is output to the 1st high-speed camera, B code 2 is output to the 2nd high-speed camera, B code 3 is output to the 3rd high-speed camera, B code 4 is output to the 4th high-speed camera, and B code 5 is output to the 5th high-speed camera.
[0065] Step 3: The FPGA logic processing unit waits for the door opening signal transmitted by the door opening signal conditioning circuit, the beam separation signal transmitted by the beam separation signal conditioning circuit, and the disconnection signal transmitted by the disconnection signal conditioning circuit, and illuminates the corresponding aircraft key action signal valid indicator light.
[0066] The specific process is as follows:
[0067] The hatch switch signal is characterized by a ground signal of less than 0.7V and an amplitude of greater than 12V, a hatch opening signal as a rising edge and a hatch closing signal as a falling edge; the beam separation signal is characterized by a rising edge pulse signal, a ground signal of less than 0.7V and an amplitude of greater than 12V; the disconnection signal is characterized by a falling edge signal, a ground signal of less than 0.7V and an amplitude of greater than 12V; the hatch switch signal conditioning circuit receives a hatch switch signal greater than 12V and converts it into a 3.3V level signal IN(1) and sends it to the FPGA logic processing unit; the beam separation signal conditioning circuit receives a beam separation signal greater than 12V and converts it into a 3.3V level signal IN(2) and sends it to the FPGA logic processing unit; the disconnection signal conditioning circuit receives a disconnection signal greater than 12V and converts it into a 3.3V level signal IN(3) and sends it to the FPGA logic processing unit;
[0068] The FPGA logic processing unit parses and demodulates the GPS / BeiDou satellite signal 232-TTL1(1) and generates DC code signal OUT(6); receives serial port configuration information 232-TTL(2) and establishes a mapping relationship between 3 key aircraft actions and 5 high-speed cameras; detects the validity of the conditioned signals IN1(1)~IN1(3) of the 3 key aircraft actions and generates OUT(12)~OUT(14); the aircraft key action signal validity indicator drive illuminates the door switch signal indicator when OUT(12) is high, the beam departure signal indicator when OUT(13) is high, and the disconnection signal indicator when OUT(14) is high.
[0069] Step 4: The FPGA logic processing unit generates a high-speed camera drive signal according to the mapping relationship, and then drives the corresponding high-speed camera to work by triggering the drive circuit, and lights up the high-speed camera's working indicator light.
[0070] The specific process is as follows:
[0071] The FPGA logic processing unit detects the validity of the three key aircraft actions after conditioning the signals IN1(1)~IN1(3), sends the high-speed camera working signals OUT(1)~OUT(5) according to the configuration information, and drives the corresponding high-speed camera to work through the trigger drive circuit; at the same time, it sends the high-speed camera working indicator light drive signals OUT(7)~OUT(11), and lights up the high-speed camera working indicator light through the high-speed camera working indicator light drive circuit.
[0072] The first trigger drive circuit receives the high level of OUT(1) output by the FPGA logic processing unit and drives the No. 1 high-speed camera to work; the second trigger drive circuit receives the high level of OUT(2) output by the FPGA logic processing unit and drives the No. 2 high-speed camera to work; the third trigger drive circuit receives the high level of OUT(3) output by the FPGA logic processing unit and drives the No. 3 high-speed camera to work; the fourth trigger drive circuit receives the high level of OUT(4) output by the FPGA logic processing unit and drives the No. 4 high-speed camera to work; the fifth trigger drive circuit receives the high level of OUT(5) output by the FPGA logic processing unit and drives the No. 5 high-speed camera to work.
[0073] When OUT(7) is high, indicator light 1 of the high-speed camera is lit; when OUT(8) is high, indicator light 2 of the high-speed camera is lit; when OUT(9) is high, indicator light 3 of the high-speed camera is lit; when OUT(10) is high, indicator light 4 of the high-speed camera is lit; when OUT(11) is high, indicator light 5 of the high-speed camera is lit.
[0074] Example 4
[0075] Based on Example 3, it also includes:
[0076] The key aircraft action signal indicator is driven by the FPGA logic processing unit. Since the key aircraft action signal is characterized by rising or falling edge, in order to facilitate visual observation, when the FPGA logic processing unit detects the rising edge of the door switch signal IN(1), it outputs OUT(12) high level for 500ms, which illuminates the door switch signal valid indicator for 500ms (door open); when the FPGA logic processing unit detects the falling edge of the door switch signal IN(1), it outputs OUT(12) high level for 500ms, which illuminates the door switch signal valid indicator for 500ms (door closed); when the FPGA logic processing unit detects that the beam separation signal IN(2) is high level, it outputs OUT(13) high level for 500ms, which illuminates the beam separation signal valid indicator for 500ms; when the FPGA logic processing unit detects the falling edge of the disconnection signal IN(3), it outputs OUT(14) high level for 500ms, which illuminates the disconnection signal valid indicator for 500ms.
[0077] Example 5
[0078] Based on Example 4, it also includes:
[0079] The driving signal OUT(1) and the working indicator signal OUT(7) of the No. 1 high-speed camera are both high or low. The driving signal OUT(3) and the working indicator signal OUT(8) of the No. 2 high-speed camera are both high or low. The driving signal OUT(3) and the working indicator signal OUT(9) of the No. 3 high-speed camera are both high or low. The driving signal OUT(4) and the working indicator signal OUT(10) of the No. 4 high-speed camera are both high or low. The driving signal OUT(5) and the working indicator signal OUT(11) of the No. 5 high-speed camera are both high or low.
[0080] Example 6
[0081] Based on Example 5, it also includes:
[0082] The panel is equipped with a DC28V power input port for connecting to the onboard 28V power supply; the panel also has a POWER indicator light to show that the internal 5V power supply is normal; a GPS / BeiDou interface is used to connect to a GPS / BeiDou antenna; the door switch signal interface is used to connect to the aircraft's door switch signal; the beam separation interface is used to connect to the aircraft's beam separation signal; the disconnection interface is used to connect to the aircraft's disconnection signal; the first trigger drive circuit is used to connect to the trigger of camera 1; B code 1 is used to connect to the B code of camera 1; the second trigger drive circuit is used to connect to the trigger of camera 2; B code 2 is used to connect to the B code of camera 2; the third trigger drive circuit is used to connect to the trigger of camera 3; B code 3 is used to connect to the B code of camera 3; the fourth trigger drive circuit is used to connect to the trigger of camera 4; B code 4 is used to connect to the B code of camera 4; the fifth trigger drive circuit is used to connect to the trigger of camera 5; B code 5 is used to connect to the B code of camera 5.
[0083] The serial port interface on the side panel connects to the RS232 interface of the computer for receiving configurations; the switch is used to turn the device power on or off.
[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.
Claims
1. A high-speed trigger control device, comprising an FPGA logic processing unit; characterized in that: It also includes input and output modules connected to the FPGA logic processing unit; The input module includes a B-code time input circuit, an input circuit for the mapping relationship between key aircraft actions and high-speed camera operation, and a key aircraft action signal input circuit. The B-code time input circuit includes a GPS / BeiDou receiver, which connects to GPS / BeiDou satellite signals through the GPS / BeiDou interface on the device panel, and connects to the FPGA logic processing unit at the other end. The input circuit for mapping the key aircraft maneuvers to the operation of the high-speed camera includes an interface circuit, which receives the mapping relationship between the key aircraft maneuvers and the operation of the high-speed camera through a serial port on the device panel. The aircraft critical action signal input circuit is connected to the aircraft critical action signals, including the door opening / closing signal, the beam separation signal, and the loss of contact signal. The aircraft critical action signal input circuit includes a door opening / closing signal conditioning circuit, a beam separation signal conditioning circuit, and a loss of contact signal conditioning circuit. The door opening / closing signal is transmitted to the FPGA logic processing unit through the door opening / closing signal conditioning circuit, the beam separation signal is transmitted to the FPGA logic processing unit through the beam separation signal conditioning circuit, and the loss of contact signal is transmitted to the FPGA logic processing unit through the loss of contact signal conditioning circuit. The output module includes a trigger drive circuit, a B-code conversion circuit, a high-speed camera working indicator light drive circuit, and an aircraft key action signal valid indicator light drive circuit for driving the high-speed camera. The input terminals of the trigger drive circuit, the B-code conversion circuit, the high-speed camera working indicator light drive circuit, and the aircraft key action signal valid indicator light drive circuit are all connected to the FPGA logic processing unit. The output terminals of the trigger drive circuit and the B-code conversion circuit are all connected to the high-speed camera. The output terminal of the high-speed camera working indicator light drive circuit is connected to the high-speed camera working indicator light, and the output terminal of the aircraft key action signal valid indicator light drive circuit is connected to the aircraft key action signal indicator light. It also includes a power module, which is connected to the FPGA logic processing unit, the input module, and the output module.
2. The high-speed trigger control device according to claim 1, characterized in that: The B-code conversion circuit includes a B-code generation circuit and a B-code allocation circuit connected in sequence; wherein, the B-code generation circuit is connected to the FPGA logic processing unit, and one end of the B-code allocation circuit is connected to the B-code generation circuit, and the other end is connected to the high-speed camera.
3. The high-speed trigger control device according to claim 2, characterized in that: The system has five high-speed cameras, each corresponding to a trigger drive circuit and a high-speed camera working indicator light. The trigger drive circuit and the high-speed camera working indicator light are all one-to-one with the high-speed cameras. The B code allocation circuit is connected to each of the five high-speed cameras.
4. The high-speed trigger control device according to claim 3, characterized in that: The power module includes a power conversion circuit and a secondary power conversion circuit connected in sequence. The input terminal of the power conversion circuit is connected to an external 28V airborne power supply, and the output terminal of the power conversion circuit is connected to the input terminal of the secondary power conversion circuit. The output terminal of the secondary power conversion circuit is connected to the input module, the output module, and the FPGA logic processing unit, respectively.
5. A high-speed triggering control method, characterized in that: Using the high-speed trigger control device as described in claim 4 above, the control method is as follows: Step 1: Install 5 high-speed cameras on the aircraft; The computer configures the mapping relationship between three key aircraft maneuvers and the operation of five high-speed cameras. The mapping relationship is received through the serial port on the device panel and then converted into a 3.3V RS232 level signal through the interface circuit and sent to the FPGA logic processing unit. Step 2: While triggering the high-speed camera to work, the GPS / BeiDou satellite signal provides the B code time for superposition. The B code time is parsed by the GPS / BeiDou receiver, and after parsing, it is processed into DC code signal by the FPGA logic processing unit. Then, it is converted into 1 AC code by the B code generation circuit, and then distributed into 5 channels by the B code distribution circuit, which are sent to high-speed cameras 1 to 5 respectively. Step 3: The FPGA logic processing unit waits for the door opening signal transmitted by the door opening signal conditioning circuit, the beam separation signal transmitted by the beam separation signal conditioning circuit, and the disconnection signal transmitted by the disconnection signal conditioning circuit, and illuminates the corresponding aircraft key action signal valid indicator light. Step 4: The FPGA logic processing unit generates a high-speed camera drive signal according to the mapping relationship, and then drives the corresponding high-speed camera to work by triggering the drive circuit, and lights up the high-speed camera's working indicator light.
6. The high-speed trigger control method according to claim 5, characterized in that: In the mapping relationship, the three key aircraft actions include the door opening / closing signal, the beam separation signal, and the disconnection signal. The operation of the five high-speed cameras includes the working relationship and working time, which consists of a 2-bit array. The first bit is the correspondence, which can be 0 or 1; the second bit is the shooting time. When the first bit is 0, the second bit x=0. When the first bit is 1, the second bit x is an integer in milliseconds. 0 represents not working, and 1 represents working; as shown in the table below. 。 7. The high-speed trigger control method according to claim 6, characterized in that: The hatch switch signal is characterized by a ground signal of less than 0.7V and an amplitude of greater than 12V; the hatch opening signal is a rising edge, and the hatch closing signal is a falling edge. The beam separation signal is characterized by a rising edge pulse signal, a ground signal of less than 0.7V, and an amplitude of greater than 12V. The disconnection signal is characterized by a falling edge signal, a ground signal of less than 0.7V, and an amplitude of greater than 12V. The hatch switch signal conditioning circuit receives a hatch switch signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit. The beam separation signal conditioning circuit receives a beam separation signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit. The disconnection signal conditioning circuit receives a disconnection signal greater than 12V, converts it into a 3.3V level signal, and sends it to the FPGA logic processing unit.
8. The high-speed trigger control method according to claim 7, characterized in that: The FPGA logic processing unit illuminates the door switch signal indicator when the door switch signal changes from low to high or from high to low; illuminates the beam departure signal indicator when the beam departure signal changes from low to high; and illuminates the disconnection signal indicator when the disconnection signal changes from high to low.
9. The high-speed triggering control method according to claim 8, characterized in that: When the aircraft key action signal valid indicator light driver circuit drives the aircraft key action signal indicator light, the aircraft key action signal valid indicator light driver circuit outputs a 500ms high level to light up the corresponding aircraft key action signal valid indicator light.
10. The high-speed triggering control method according to claim 9, characterized in that: The power conversion circuit receives the onboard 28V power supply and converts it to 5V; the secondary power conversion circuit converts the 5V power supply to 3.3V, 2.5V, 1.25V and 1.2V. The 3.3V is used to power the FPGA logic processing unit, GPS / BeiDou receiver, interface circuit, aircraft key action signal input circuit, B code generation circuit and B code distribution circuit; the 2.5V, 1.25V and 1.2V are also used to power the FPGA logic processing unit.