Drift and noise corrected memristive devices

Abstract

A memristor memory device (100) comprising a memristive memory cell (102), an input terminal (104), an output terminal (108), and a gate terminal (112). The input terminal (104) and the output terminal (108) are directly attached to the memristive memory cell (102), and the gate terminal (112) is electrically isolated from the memristive memory cell (102). The gate terminal (112) is configured to receive an electrical signal for a volatile modulation of an electrical conductance of the memristive memory cell (102), by which a correction of a non-ideal conductance modulation of the memristor memory device (100) is achieved.

Description

Background Technology

[0001] This document discloses a memristor memory device including memristor memory cells. More specifically, the present invention relates to a method for operating a memristor memory device including memristor memory cells.

[0002] Multilevel cell (MLC) memory is a typical approach to achieving increased capacity and thus lower cost per bit in memory technology. To this end, phase-change memory (PCM) is a novel solid-state memory technology that utilizes, for example, the thermal resistivity variation of chalcogenide components used for non-volatile data storage. PCM possesses certain characteristics, such as high cycle endurance, low read / write latency, and excellent scalability, making it an interesting candidate not only for expanding and eventually replacing current flash memory, but also for enabling disruptive changes in future computing systems. The latter stems from PCM's potential to act as both storage (non-volatile, inexpensive, high capacity) and memory (fast, durable) due to its versatility. Summary of the Invention

[0003] According to one aspect disclosed herein, a memristor memory device comprising memristor memory cells can be provided. The memristor memory device may include an input terminal, an output terminal, and a gate terminal. The input and output terminals may be directly attached to the memristor memory cells, and the gate terminal may be electrically isolated from the memristor memory cells. The gate terminal may be configured to receive an electrical signal that volatilely modulates the conductance of the memristor memory cells. This allows for the correction of non-ideal conductance modulation of the memristor memory device.

[0004] According to another aspect disclosed herein, a method for operating a memristor memory device including memristor memory cells can be provided. The memristor memory device may include input terminals, output terminals, and a gate terminal, wherein the input terminals and output terminals may be directly attached to the memristor memory cells. The gate terminal may be electrically isolated from the memristor memory cells. The method may further include providing an electrical signal for volatile modulation of the conductance of the memristor memory cells. This allows for correction of non-ideal conductance modulation of the memristor memory device. Attached Figure Description

[0005] Embodiments of the invention are described with reference to different subject matter. Specifically, some embodiments are described with reference to method type claims, while others are described with reference to apparatus type claims. However, those skilled in the art will conclude from the above and below description that, unless otherwise indicated, any combination of features relating to different subject matter (specifically, features of method type claims and features of apparatus type claims) is also considered to be disclosed herein, except for any combination of features belonging to one type of subject matter.

[0006] The aspects defined above and other aspects of the various embodiments are apparent from the examples of the embodiments described below, and are explained with reference to the examples of embodiments, but the invention is not limited thereto. Various embodiments may be described as having certain advantages; however, some embodiments may not have these potential advantages, and these potential advantages are not essential to all embodiments.

[0007] The embodiments will be described by way of example only and with reference to the following figures:

[0008] Figure 1 This is a block diagram of an embodiment of the memristor memory device of the present invention, including memristor memory cells, according to some embodiments.

[0009] Figure 2 It is a block diagram illustrating the functional principles of the system and method proposed according to some embodiments.

[0010] Figure 3 This is a block diagram of an embodiment of a cross-shaped array having memristor memory devices, according to some embodiments.

[0011] Figure 4 This is a block diagram of an embodiment of a cross array having a temperature noise and resistance drift compensation device, according to some embodiments.

[0012] Figure 5 This is a diagram illustrating the first experimental evidence of the system and method proposed according to some embodiments.

[0013] Figure 6 This is a diagram illustrating second experimental evidence of the system and method proposed according to some embodiments.

[0014] Figure 7 This is a flowchart of an embodiment of a method for operating a memristor memory device including memristor memory cells, according to some embodiments. Detailed Implementation

[0015] To make PCM a viable technology for large-scale manufacturing, several issues may need to be addressed. First, the reliability of this technology should reach a level similar to that of existing technologies. Experimental results and simulations show that thermal interference and resistance drift are the most significant potential reliability problems for PCM memory technology. Thermal interference refers to the problem of inappropriately altering the state of a cell by programming another cell and its surrounding area (thermal process talk). On the other hand, resistance drift is a phenomenon according to which the resistivity of the amorphous phase of many chalcogenide materials increases over time. Drift is attributed to structural relaxation and stress release in the amorphous matrix and is particularly detrimental in multi-level cell memory because random fluctuations in the programming resistances of closely spaced levels can cause them to overlap and thus lead to decoding errors. This task can be addressed through the technical solutions proposed here.

[0016] In the context of this specification, the following conventions, terms and / or expressions may be used:

[0017] The term "memristor memory device" (memristor = a combination of memory resistors) can refer to a memory device based on memristor cells (i.e., memristors). It can represent a nonlinear, typically two-terminal electrical component associated with charge and magnetic flux linkages, but is implemented here as a three-terminal device. For the device, a phase change material (PCMT) can typically be used. This PCMT can change its resistivity between multiple different levels by changing from an amorphous phase to a crystalline phase. This change can be thermally induced. In this way, multilevel cell (MLC) memory devices comprising multiple memristor memory cells can be created.

[0018] The term "memristor memory cell" can refer to the memristor core device or memristor memory cell of a memory device. A memristor memory cell can include a phase-change material and can store data by changing its resistivity. Typically, during readout, a selected bit line of a cross-array comprising multiple memristor memory cells at the crossover point is biased to a constant voltage (typically several 100mV) by a voltage regulator. The sensed current i read The voltage can be integrated using a capacitor, and the resulting voltage is then digitized by an on-chip cyclic analog-to-digital converter. Furthermore, the readout characteristics can be calibrated using an on-chip reference polysilicon resistor. For programming, the voltage generated off-chip can be converted into a programming current i on-chip. prog Then, the count can be mirrored onto the selected bit line for the desired duration of the programming pulse, which can alter the mixing of crystalline and amorphous phases in the PCM.

[0019] The term "gate terminal" can refer to a (third) electrode that is adjacent to but electrically isolated from the PCM of a memristor memory cell. Depending on the wiring of the gates of multiple individual memristor memory cells, the charge at the gate terminal and the gate itself affect the behavior of the PCM (i.e., each individual memristor memory cell), and therefore also the behavior of the PCM within the memristor memory device.

[0020] The term "volatile modulation" (specifically, those volatile modulations induced by the gate) can refer to the forced change in resistivity of a memristor memory cell device due to the applied gate voltage.

[0021] The term “nonideal conductance modulation” can refer to an effect in PCM-based devices (such as memristor memory devices) that include multiple memristor memory cells that utilize PCM through temperature and resistance drift effects.

[0022] The term "resistivity drift" can describe the phenomenon that the resistivity of the amorphous phase of a phase change material (e.g., chalcogenides) increases over time. Drift can be caused by structural relaxation and stress release in the amorphous matrix of a PCM and is particularly detrimental in multi-level cell memory devices due to the random fluctuations in resistance programmed to closely spaced resistance levels. Despite the use of adaptive level thresholds, the bit error rate in MLC PCMs deteriorates over time due to the increasing noise margin between adjacent levels. This is because drift is a stochastic process, and therefore the resistance of each cell increases in a random manner. Furthermore, the rate of increase (i.e., the drift exponent) is itself a random variable. While it is true that the average drift exponent increases with cell resistance, significant variability is typically observed around the average value. Thus, a small number of cells from each resistance distribution exhibit drift exponents that are significantly different from the rest of the cells. The drift-to-time trajectories of two such cells programmed, for example, in adjacent levels "2" and "3", may eventually move closer together and eventually intersect each other at a later time instance, and the cell levels are significantly separated after programming due to the drift exponent deviating from the average behavior.

[0023] The term "thermal interference drift of resistors" can describe the undesirable effects of thermal variations on a memristor memory cell, which inadvertently alters the cell's state by programming another nearby cell; it is related to PCM because PCM depends on state changes in home and use, which can cause thermal interference between adjacent cells at small device sizes. Interference with the resistive state can also be caused by variations in chip temperature due to thermal changes from the environment.

[0024] The term "filamentary memristor" can be associated with the memristor resistance switching effect in an insulating or semi-conductive solid electrolyte that occurs by forming a conductive channel (filament).

[0025] The term "cross-array" refers to a structure of conductive lines that intersect each other. Horizontal lines may define word lines, while vertically oriented lines may be represented as bit lines. Each intersection of a word line and a bit line may include an electrical or electronic device, one end of which is connected to both the word line and the corresponding bit line. In this concept, each intersection includes a memristor memory cell, such that a cross-array comprising multiple memristor memory cells can form the core component of a memristor memory device.

[0026] The term "temperature effect control device" can refer to an electronic device adapted to counteract the aforementioned thermal disturbance effects.

[0027] The term "resistance drift correction device" can refer to an electronic device adapted to counteract the aforementioned resistance drift effect present in a PCM.

[0028] The proposed memristor memory device, which includes memristor memory cells, offers several advantages, contributions, and technical benefits.

[0029] Essentially, this lays the foundation for overcoming the current challenges of PCM-based memristor memory devices, making it a viable technology for manufacturing larger capacity memories and potential computing devices (potentially replacing flash memory). It can increase the reliability of PCM-based memory technology by overcoming the negative effects caused by thermal interference and resistance drift (i.e., volatile conductance modulation). Specifically, the randomly occurring resistance drift effect has a significant negative impact on currently available PCM-based memristor memory devices, which can be overcome by the proposed concept.

[0030] Specifically, the gate terminal can be used to counteract the resistance drift effect. As experimental evidence shows, the additional electronic components required in the form of temperature compensation devices and resistance drift compensation devices are negligible compared to the resulting technical effect. Compensation devices can be used in multiple memristor memory devices, or even larger memristor memory devices comprising multiple memristor memory devices. Specifically, the dynamically adapted gate signal that can be generated by the resistance drift compensation device utilizes the resistance drift effect based on a stochastic process.

[0031] Additional embodiments of memristor memory devices that are also applicable to the related methods are described below.

[0032] According to embodiments of memristor memory devices, non-ideal conductance modulation can include at least time-resistance drift and / or temperature-induced interference in the resistor. These can be major impacts negatively affecting the reliability of memristor memory devices. However, other non-ideal conductance modulations can be addressed and potentially repaired by using a gate structure adjacent to the PCM of the memristor memory cell.

[0033] According to one embodiment of a memristor memory, the memristor memory cell may include a phase change material or a filamentary electrolyte. These can be typical examples of PCMs. However, other types of substrate materials for memristor memory cells may also be used to apply the inventive concepts presented herein, provided that negative temperature effects and / or resistance drift affect the PCM and related devices.

[0034] According to useful embodiments of memristor memory devices, a memristor memory device may include a plurality of memristor memory cells, particularly two or more, wherein a gate terminal is shared by the plurality of memristor memory cells. In industrial-scale memristor memory devices, potentially millions of memristor memory cells can be combined to form a memristor memory device. At least a portion of the memristor memory cells may have electrically connected gates. They can affect memristor memory cells connected to a common gate line. Therefore, a group of memristor memory cells in a memristor memory device may be affected by gate charge to counteract negative temperature effects and resistance drift.

[0035] According to an advantageous embodiment of a memristor memory device, multiple memristor memory devices can be arranged in a cross-array to form a memristor memory device. The memristor memory device can be the core component of the memristor memory device. Thus, if one of the memristor memory cells can be located at each intersection of the word line and the bit line, the memristor memory cell becomes addressable by both the word line and the bit line.

[0036] According to another advantageous embodiment, the memristor memory device may further include a temperature effect control device whose output is adapted to provide a temperature effect control signal corresponding to the temperature difference ΔT between the ideal operating temperature of the memristor memory device and the non-ideal dynamically changing temperature of the memristor memory device. This can advantageously reflect the temperature development of the memristor memory device over time, particularly the actual temperature during a read operation and the historical temperature development after a write (i.e., programming) operation. By accessing the temperature development over time, the temperature effect control device can compensate for related effects by anticipating the effects associated with the temperature development over time.

[0037] According to another advantageous embodiment of the memristor memory device, the temperature effect control device may further include a temperature sensor electrically connected to the temperature effect control device, and a pre-calibrated ΔT to V. T,gate A conversion device, the conversion unit providing a value V to a set of gate terminals of a selected memristor memory device among a plurality of memristor memory devices. T,gateThe voltage is used as a temperature-dependent control signal. This group can range from a single memristor memory cell to all memristor memory cells. Advantageously, those memristor memory cells can be grouped together to show a closely related temperature dependence. The temperature sensor can generate a signal based on the actual temperature of one or more memristor memory devices.

[0038] According to a further enhanced embodiment of the memristor memory device, the pre-calibrated ΔT to V T,gate The conversion device may further include a first digital-to-analog converter adapted to convert the digital temperature effect control signal into an analog value V. T,gate The signal, the first digital-to-analog converter, is connected to the gate terminals of a plurality of memristor memory devices that constitute a memristor memory device. Therefore, volatile modulation caused by the temperature effect of the resistance of the memristor memory cell group (i.e., the device) can be corrected and / or compensated.

[0039] According to another advantageous embodiment, the memristor memory device may further include a resistance drift correction device whose output is adapted to provide a resistance drift control signal corresponding to the resistance difference ΔR between the target resistance of the memristor memory device and the read resistance of the memristor memory device. The read resistance can be measured directly after the programming / writing operation. This can define a reference value for the resistivity of the corresponding memristor memory cell. Based on this value, a correction or compensation signal for the gate can be generated.

[0040] According to a further enhanced embodiment of the memristor memory device, the resistance drift correction device may further include: ΔR to V R,gate A conversion unit device that provides a value V to a set of gate terminals of a selected memristor memory device among the plurality of memristor memory devices. R,gate The voltage is used as a control signal for resistance drift correction. Similar to the temperature compensation case, this group can range from a single memristor memory cell to all memristor memory cells. Advantageously, those memristor memory cells can be grouped together to show a closely related temperature dependence.

[0041] According to another further enhanced embodiment of the memristor memory device, ΔR to V R,gate The conversion device may further include a second digital-to-analog converter, which is adapted to convert the digital resistive effect control signal into an analog value V. R,gate A signal is connected to the gate terminals of multiple memristor memory devices to construct a memristor memory device. Therefore, volatile modulation caused by resistive drift effects of the resistance of the memristor memory cell array can be corrected and / or compensated.

[0042] According to another embodiment, the memristor memory device may include a plurality of memristor memory devices arranged in a cross-array, wherein each memristor memory device includes a memristor memory cell, wherein the memristor memory device includes an input terminal, an output terminal, and a gate terminal, the gate terminal being specifically adjacent to the memristor memory cell, and wherein the input terminal and the output terminal may be directly attached to the memristor memory cell. Therefore, the gate terminal may be electrically isolated from the memristor memory cell, and the gate terminal may be configured to receive an electrical signal for volatile modulation of the conductance of the memristor memory cell. This can compensate for non-ideal conductance modulation of the memristor memory device. The memristor memory device may further include: a temperature effect control device adapted to generate a portion of the received electrical signal based on a temperature-based resistance drift effect of each memristor memory device; and a resistance drift correction device adapted to generate another portion of the received electrical signal based on a time-dependent resistance drift effect of each memristor memory device. Therefore, in a memristor memory device that includes multiple memristor memory devices, each memristor memory device may include a separate correction / compensation device, so that different regions within the memristor memory device can be processed differently based on, for example, local differences between memristor memory devices.

[0043] A detailed description of the accompanying drawings is given below. All instructions in the drawings are schematic. First, a block diagram of an embodiment of the memristor memory device of the present invention, including memristor memory cells, is given. Then, other embodiments and embodiments of methods for operating the memristor memory device including memristor memory cells will be described.

[0044] Figure 1 This is a block diagram of an embodiment of a memristor memory device 100 including a memristor memory cell 102. The memristor memory device (MME) may be based on, for example, PCM or filament electrolyte. The memristor memory device 100 includes at least a memristor memory cell 102, an input terminal (drain via electrical connection 106) 104, an output terminal (source via electrical connection 110) 108, and a gate terminal 112.

[0045] Input terminal 104 and output terminal 108 are directly attached to memristor memory cell 102, wherein gate terminal 112 is electrically isolated from memristor memory cell 102 via, for example, a dielectric (non-conductive) layer 116. Gate terminal 112 is configured to receive, via line 114, an electrical signal for volatilely modulating the conductance of the memristor memory cell, the volatile modulation causing correction or compensation of non-ideal conductance modulation in memristor memory device 102.

[0046] Figure 2 This is a block diagram illustrating the functional principle 200 of the proposed system and method. The memristor memory cell 202, which is the core of the memristor memory device, can be programmed via signal 204. After programming the memristor memory cell to a certain resistance level, the target resistance 206 is known (either by reading it directly after programming or, for example, from a lookup table). To correct for resistance drift effects during read operations, the gate 212 of the memristor memory cell 202 can be used for volatile modulation of the device conductance. Therefore, the gate V... gate The output is scaled proportionally to the difference ΔR between the measured resistance and the target resistance. A proportional constant can be defined to correct for drift with varying accuracy. The reference device 208 can transmit the value ΔR. ref The corresponding required signal.

[0047] Furthermore, gate 212 can also be used to correct the temperature noise effect (temperature-induced drift) on the resistance of the memristor cell 202 during the read process. For this purpose, gate 212 is used for volatile modulation of the device conductance (equivalent to resistance drift). The gate output V gate The chip temperature is scaled proportionally to the difference ΔT between the chip temperature under ideal conditions and the chip temperature 210 (measured by a sensor) under non-ideal dynamic conditions (e.g., affected by "programming heat" or other ambient temperature variations). A proportional constant can be defined to correct for drift with varying accuracy.

[0048] Therefore, the memristor memory cell device can be corrected for both resistance drift and thermal interference during read operations. Furthermore, any non-ideal conductance modulation can be corrected and / or compensated by gate signal operation, independent of the conductance state of the PCM of the memristor in memory cell 202.

[0049] Figure 3 This is a block diagram of an embodiment of a cross-array 300 having memristor memory devices 302. The cross-array 300 includes horizontal word lines 304 (only one of which is labeled) and vertical bit lines 310 (only one of which is labeled) for addressing a plurality of memristor memory devices 302 at corresponding intersections. The word lines 304 and bit lines 310 are used for addressing the corresponding memristor memory devices 302. The word lines 304 can be activated by terminals 306, 308, and 312. The terminals of the bit lines 310 are not explicitly shown. The cross-array 300 represents an ixj matrix of rows having memristor memory devices 302.

[0050] Furthermore, gate contacts (not specified) for each memristor memory device 302 are shown. These gate contacts are diagonally connected compared to word lines 304 and bit lines 310. Diagonal gate lines (not explicitly specified) connect multiple memristor memory devices 302 across the diagonally located intersections of word lines 304 and bit lines 310. Gate voltages can be applied to gate terminals 314, ..., 320. The corresponding gate voltages will only be effective for the addressed memristor memory device 302. During readout, the current I of bit line 310... i (For example, using a pair of 100mV bias voltages) can be integrated and converted by an analog-to-digital converter. Memristor element R ij The rightmost column 322 can be implemented as a reference resistor.

[0051] Figure 4 Block diagram 400 shows an embodiment of a cross-array 300 with temperature noise and resistance drift compensation devices 402, 404. The output signal of the cross-array 300 includes the output signal of column 322 with reference resistors (see...). Figure 3 - Converted into a differential signal R by analog-to-digital converter 406 11 -R ij This is fed back to the resistance drift compensation device 404, where a pre-calibrated ΔR to V is generated. R,gate The signal is converted by a digital-to-analog converter 408, which is connected to a gate (control) signal device 410 to address the corresponding gate line in the cross array 300 via symbol connection 412 to correct for the effects of resistance drift during read operations.

[0052] Furthermore, the temperature correction device 402 includes a temperature sensor and converts the measured temperature of the cross-array 300 into a signal corresponding to the temperature difference between the measured temperature of the cross-array 300 and the ideal temperature of the memristor memory cell or the cross-array 300, thereby compensating for thermal interference effects that negatively affect the expected resistance level of one or more memristor memory cells of the cross-array 300. Also here, pre-calibration is performed on ΔT to V. T,gate The conversion is performed by the digital-to-analog converter 414 and passed to the gate (control) signal device 410 so as to address the corresponding gate line in the cross array 300 via the symbol connection 412.

[0053] Figure 5 Figure 500 shows the first experimental evidence of the proposed system and method. The X-axis shows the change in resistance (Y-axis, left side) over time. On the right Y-axis, the voltage V is shown. gate Furthermore, a corresponding change in resistance drift can be observed after approximately 100 seconds. Using gate drift correction, the drift coefficient can be reduced by more than three orders of magnitude.

[0054] Figure 6 Figure 600 shows second experimental evidence of the proposed system and method. The topmost graph shows the typical uncorrected resistance drift effect over time. The middle graph shows the corrected resistance value with only the drift coefficient of -0.006 shown. The bottommost graph shows the standard deviation of the drift coefficient of approximately 0.02.

[0055] Therefore, the experimental results demonstrate that the methods and related systems presented here can very effectively solve thermal interference and resistance drift for the practical use of memristor memory devices in industrial applications.

[0056] Figure 7 This is a flowchart of an embodiment of a method 700 for operating a memristor memory device including memristor memory cells. Method 700 includes, in operation 702, providing a memristor memory device including an input terminal, an output terminal, and a gate terminal, wherein the input terminal and the output terminal are directly attached to the memristor memory cell, and wherein the gate terminal is electrically isolated from the memristor memory cell.

[0057] Method 700 further includes providing an electrical signal in operation 704 for volatile modulation of the conductance of the memristor memory cell, thereby correcting the non-ideal conductance modulation of the memristor memory device as described above in operation 706.

[0058] Various embodiments have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements over those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0059] Various embodiments can be implemented as systems and methods. Aspects of different embodiments are described herein with reference to flowchart illustrations and / or block diagrams of methods and apparatus (systems). It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0060] The flowcharts and / or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. Each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a non-linear order. For example, depending on the functions involved, two consecutively shown blocks may actually execute substantially simultaneously, or these blocks may sometimes execute in reverse order. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0061] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It should also be understood that when the terms “comprises” and / or “comprising” are used in this specification, they specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0062] All means or steps in the following claims, plus corresponding structures, materials, actions, and equivalents of the functional elements, are intended to include any structure, material, or action for performing the said function in conjunction with other claimed elements as specifically claimed. Descriptions of various embodiments have been presented for purposes of illustration and description, but are not intended to be exhaustive or limited to the invention as disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention. These embodiments were chosen and described in order to best explain the principles and practical application of the invention and to enable others skilled in the art to understand the different embodiments of the invention with different modifications, as suited to the particular intended use.

Claims

1. A memristor memory device including memristor memory cells, the memristor memory device comprising: Input terminals; Output terminals; Gate terminal; as well as A temperature effect control device, wherein the temperature effect control device outputs a temperature effect control signal adapted to provide a temperature effect control signal corresponding to the temperature difference ΔT between the ideal operating temperature of the memristor memory device and the non-ideal dynamic temperature variation of the memristor memory device; in: The input terminal and the output terminal are directly attached to the memristor memory cell; The gate terminal is electrically isolated from the memristor memory cell; and The gate terminal is configured to receive an electrical signal that is volatilely modulated for the conductance of the memristor memory cell, in order to correct for non-ideal conductance modulation of the memristor memory device.

2. The memristor memory device according to claim 1, wherein, The non-ideal conductivity modulation includes at least one of time resistance drift and interference caused by the temperature of the resistor.

3. The memristor memory device according to claim 1, wherein, The memristor memory cell includes a phase change material or a filament electrolyte.

4. The memristor memory device according to claim 1, wherein: The memristor memory device includes a plurality of the memristor memory cells; and The gate terminal is shared by the plurality of memristor memory cells.

5. The memristor memory device according to claim 4, wherein, The plurality of memristor memory cells are arranged in a cross-shaped array to construct a memristor memory device.

6. The memristor memory device according to claim 1, wherein, The temperature effect control device further includes: A temperature sensor, electrically connected to the temperature effect control device; and A pre-calibrated ΔT to VT gate switching device provides a voltage of value VT as a temperature effect control signal to a set of gate terminals of a selected memristor memory device among a plurality of memristor memory devices.

7. The memristor memory device according to claim 6, wherein, The pre-calibrated ΔT to VT gate conversion device further includes: A first digital-to-analog converter is adapted to convert a digital temperature effect control signal into an analog value VT gate signal, the analog value VT gate signal being connected to the gate terminal of the plurality of memristor memory devices that constitute a memristor memory device.

8. The memristor memory device according to claim 1, further comprising: A resistance drift correction device whose output is adapted to provide a resistance drift control signal corresponding to the resistance difference ΔR between the target resistance of the memristor memory device and the read resistance of the memristor memory device.

9. The memristor memory device according to claim 8, wherein, The resistance drift correction device further includes: A ΔR to VR gate switching device provides a voltage of value VR to a set of gate terminals of a selected memristor memory device among a plurality of memristor memory devices as the resistance drift correction control signal.

10. The memristor memory device according to claim 9, wherein, The ΔR to VR gate conversion device further includes: A second digital-to-analog converter is adapted to convert a digital resistor effect control signal into an analog value VR gate signal, the analog value VR gate signal being connected to the gate terminals of the plurality of memristor memory devices that constitute a memristor memory device.

11. A memristor memory device comprising a plurality of memristor memory devices arranged in a cross-array, wherein, Each memristor memory device includes: Memristor memory cells; Input terminals; Output terminals; and Gate terminal; in: The input terminal and the output terminal are directly attached to the memristor memory cell; The gate terminal is electrically isolated from the memristor memory cell; The gate terminal is configured to receive an electrical signal that is volatilely modulated for the conductance of the memristor memory cell, so as to correct the non-ideal conductance modulation of the memristor memory device. The memristor memory device further includes: A temperature-effect control device adapted to generate a portion of the received electrical signal based on the temperature-based resistance drift effect of each of the memristor memory devices; and A resistance drift correction device adapted to generate another portion of the received electrical signal based on the time-dependent resistance drift effect of each of the memristor memory devices.

12. A method for operating a memristor memory device including memristor memory cells, the memristor memory device comprising: The device includes an input terminal, an output terminal, and a gate terminal, wherein the input terminal and the output terminal are directly attached to the memristor memory cell, and the gate terminal is electrically isolated from the memristor memory cell. The method includes: Provide an electrical signal for volatile modulation of the conductance of the memristor memory cell to correct for non-ideal conductance modulation of the memristor memory device; and A temperature effect control signal is provided by a temperature effect control device, corresponding to the temperature difference ΔT between the ideal operating temperature and the non-ideal dynamic temperature of the memristor memory device.

13. The method according to claim 12, wherein, The temperature effect control device further includes a temperature sensor electrically connected to the temperature effect control device, and the method further includes: A voltage of value VT is provided to the gate terminal as the temperature effect control signal through a pre-calibrated ΔT to VT gate switching device.

14. The method according to claim 13, wherein, The method further includes: The digital temperature effect control signal is converted into an analog value VT gate signal connected to the gate terminal by a first digital-to-analog converter, which is part of the pre-calibrated ΔT to VT gate conversion device.

15. The method of claim 12, further comprising: A resistance drift control signal corresponding to the resistance difference ΔR between the target resistance of the memristor memory device and the read resistance of the memristor memory device is provided by a resistance drift correction device.

16. The method of claim 15, further comprising: A voltage of value VR is provided to the gate terminal as the resistance drift correction control signal by a ΔR to VR gate switching device, which is part of the resistance drift correction device.

17. The method according to claim 16, wherein, The ΔR to VR gate conversion device further includes: The digital resistance effect control signal is converted into an analog value VR gate signal connected to the gate terminal by a second digital-to-analog converter.

18. The method according to claim 12, wherein: There exists a condition selected from the group consisting of: a) the memristor memory cell includes a phase change material or a filamentary electrolyte, and b) the memristor memory device includes a plurality of the memristor memory cells, and the gate terminal is shared by the plurality of the memristor memory cells.

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