Data processing system

Abstract

A data processing system comprising a plurality of processing units 10-17 is disclosed. The system comprises functional units 20, 22-27 having different processing capacities. A set of one or more processing units can be operated in combination with one of the functional units 20, 22-27 depending on the processing capacity required by the set of one or more processing units.

Description

Background Technology

[0001] The technology described herein relates to data processing systems, and more specifically to data processing systems that include multiple processing units such as graphics processing units (graphics processors) (GPUs).

[0002] It is becoming increasingly common for data processing systems to require multiple independent data processing operations. For example, a vehicle may have displays for the main instrument console, additional navigation and / or entertainment screens, and advanced driver assistance systems (ADAS). Each of these systems may need to perform its own data processing operations, and, for example, for formal safety requirements, they may need to be able to operate independently of each other.

[0003] One approach to such systems is to provide a single graphics processing unit (GPU) that shares time among the different data processing functions required. This time sharing can be complex and error-prone, and may not provide completely independent execution of the different data processing functions.

[0004] Alternatively, a completely independent graphics processing unit can be provided for each required data processing function. However, this may have negative impacts, such as in terms of the number of processing components and / or the required cost, because this would require creating a partition of time-fixed resources on the SoC (System-on-Chip).

[0005] When generating data processing output (e.g., frames for display), data processing systems typically utilize various functional units. For example, in a tile-based graphics processing system, generating rendering output (e.g., frames) typically involves the combined operation of tiling units and a set of one or more execution units (e.g., shader cores) of a graphics processing unit (GPU). For instance, generating rendering output typically includes the GPU's execution units performing vertex processing operations to generate processed vertex data, and the tiling unit using the processed vertex data to prepare a primitive list. The GPU's execution units can then use the prepared primitive list to perform fragment processing operations. In some arrangements, vertex processing and primitive list preparation operations are effectively combined. In such arrangements, the tiling unit may assign vertex processing tasks to execution units to generate processed vertex data for primitive list preparation when the tiling unit actually needs the processed vertex data.

[0006] The applicant believes there is still room for improvement in the data processing system. Attached Figure Description

[0007] Implementations of the technology described herein will now be described by way of example only, with reference to the accompanying drawings, wherein: Figure 1A data processing system according to one embodiment of the technology described herein is shown; Figure 2A and Figure 2B The illustration schematically depicts operation according to one embodiment of the technology described herein. Figure 1 Data processing system; Figure 3 A data processing system according to one embodiment of the technology described herein is illustrated schematically and in more detail. Figure 4 An embodiment of the technology described herein is illustrated schematically. Figure 3 The various operating modes of the data processing system; and Figure 5 A data processing system according to another embodiment of the technology described herein is shown.

[0008] Where appropriate in the accompanying drawings, similar reference numerals are used for similar parts. Detailed Implementation

[0009] A first embodiment of the technology described herein includes a data processing system, the data processing system comprising: A plurality of graphics processing units, wherein one or more of the graphics processing units are operable in combination with at least one other graphics processing unit among the plurality of graphics processing units, such that a corresponding set of the one or more graphics processing units among the plurality of graphics processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same processing operations, each functional unit being able to operate in combination with a set of one or more graphics processing units in the graphics processing unit when generating data processing output; The throughput of at least one of the plurality of functional units when performing the processing operation is greater than the throughput of at least one other functional unit when performing the processing operation.

[0010] A second embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: A plurality of graphics processing units, wherein one or more of the graphics processing units are operable in combination with at least one other graphics processing unit among the plurality of graphics processing units, such that a corresponding set of the one or more graphics processing units among the plurality of graphics processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same processing operations, each functional unit being able to operate in combination with a set of one or more graphics processing units in the graphics processing unit when generating data processing output; Wherein at least one of the plurality of functional units has a throughput greater than at least one other functional unit among the plurality of functional units when performing the processing operation; The method includes: Configure a collection of one or more graphics processing units from the plurality of graphics processing units to generate data processing output; The functional unit among the plurality of functional units, which has the throughput when performing the processing operation, is configured to operate in combination with the set of one or more graphics processing units when generating the data processing output, the processing capacity being sufficient to match the processing capacity of the set of one or more graphics processing units for generating the data processing output; and When the data processing output is generated, the functional unit performs the processing operation when operating in combination with a set of one or more data processing units.

[0011] The technology described herein relates to a data processing system comprising a plurality of graphics processing units, at least some of which are operable in combination with at least one other graphics processing unit to generate data processing output (e.g., frames for display). As will be discussed in more detail below, some of the graphics processing units (and in one embodiment, all graphics processing units) are also operable to generate data processing output (e.g., frames) independently (i.e., independently of any other graphics processing unit among the plurality of graphics processing units).

[0012] Therefore, the data processing system of the technology described herein can use a set of only a single graphics processing unit (which operates independently) or a set of multiple graphics processing units (which operate in combination) to generate data processing output (e.g., a frame for display).

[0013] Similarly, the data processing system of the technology described herein should be operable (and in one embodiment, operable) such that different sets of one or more graphics processing units among a plurality of graphics processing units can generate data processing outputs independently of each other. That is, the plurality of graphics processing units should be divisible (and in one embodiment, divisible into) one or more sets (“partitions”) of one or more graphics processors, wherein each set (partition) of one or more graphics processing units is operable to generate data processing outputs independently of any other set (partition) of one or more sets (partitions ...

[0014] For example, this means that in one implementation, different sets (partitions) of one or more graphics processing units can simultaneously generate different data processing outputs, such as different frames for display on different displays. For example, in one implementation, the data processing system can be used in automotive applications. In this case, there may be corresponding "partitions" to generate data processing outputs for each of one or more of the following: a display for the main instrument console, additional navigation and / or entertainment screens, and advanced driver assistance systems (ADAS), etc.

[0015] To facilitate the generation of data processing output, the data processing system of the technology described herein includes multiple functional units, each of which performs a (same) (type) processing operation that, in one embodiment, generates output (or multiple outputs) to be used when generating data processing output (e.g., a frame). When generating data processing output (e.g., a frame), a set (partition) of one or more (e.g., combined) graphics processing units (and in one embodiment, each set (partition) should (and in one embodiment, does) operate in combination with only one functional unit among the multiple functional units. For example, and in one embodiment, and as will be further discussed below, each functional unit may be a tiling unit that uses processed vertex data generated by the set (partition) of one or more graphics processing units to prepare a primitive list (i.e., a list of geometry (e.g., primitives) to be rendered for the corresponding area of ​​the rendering output) for use tile-by-tile by the set (partition) of one or more graphics processing units when generating the rendering output (e.g., a frame).

[0016] (As will be discussed further below, functional units may be provided as part of the graphics processing unit itself, or, for example, may exist as separate functional unit "pools".)

[0017] The data processing system described herein includes multiple such functional units (e.g., tiling units) such that different functional units among the multiple functional units (e.g., different tiling units) can operate in combination with different sets (partitions) of one or more (e.g., combined) graphics processing units that are (simultaneously) generating different data processing outputs.

[0018] In the technology described herein, the multiple functional units include functional units with different throughputs (when performing the processing operation under consideration). That is, the maximum rate at which at least one of the multiple functional units can receive input to the processing operation and / or (to the received input) perform the processing operation and / or generate the output of the processing operation is greater than the maximum rate at which at least one other of the multiple functional units can receive input to the processing operation and / or (to the received input) perform the processing operation and / or generate the output of the processing operation.

[0019] For example, and in one implementation, and as will be discussed in more detail below, the system may include: one or more “small” tiling units, each having relatively low throughput and thus capable of preparing primitive lists only at a relatively slow rate; and one or more “large” tiling units, each having high processing capacity and thus capable of preparing primitive lists at a faster rate.

[0020] Accordingly, references to the throughput of a functional unit when performing a processing operation are intended to refer to the throughput of the type of processing operation that the functional unit is configured to achieve (support), and therefore, unless the context otherwise requires, to the (maximum) supported throughput (processing capacity) of the processing operation (type) that the functional unit is capable of performing (i.e., the processing capacity of the functional unit used to perform the processing operation).

[0021] Therefore, the reference in this paper that the throughput of a functional unit when performing a processing operation is greater than the throughput of another functional unit when performing a processing operation is intended to refer to a functional unit having a higher (maximum) supported (achievable) throughput (processing capacity) than another functional unit used to perform the type of processing operation under consideration.

[0022] Similarly, the reference in this paper to the throughput of a set of one or more processing units in generating data processing output is intended to refer to the (maximum) throughput (i.e. the processing capacity of the set of one or more processing units used to generate data processing output) that the set of one or more processing units can generate when operating in combination with each other.

[0023] Therefore, another embodiment of the technology described herein includes a data processing system comprising: A plurality of graphics processing units, wherein one or more of the graphics processing units are operable in combination with at least one other graphics processing unit among the plurality of graphics processing units, such that a corresponding set of the one or more graphics processing units among the plurality of graphics processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same type of processing operations, each functional unit being able to operate in combination with a set of one or more graphics processing units when generating data processing output; The processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other functional unit for performing the processing operation.

[0024] Another embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: A plurality of graphics processing units, wherein one or more of the graphics processing units are operable in combination with at least one other graphics processing unit among the plurality of graphics processing units, such that a corresponding set of the one or more graphics processing units among the plurality of graphics processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same type of processing operations, each functional unit being able to operate in combination with a set of one or more graphics processing units when generating data processing output; The processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other functional unit for performing the processing operation. The method includes: Configure a collection of one or more graphics processing units from the plurality of graphics processing units to generate data processing output; The functional unit among the plurality of functional units, having a processing capacity for performing the processing operation, is configured to operate in combination with the set of one or more graphics processing units when generating data processing output, the processing capacity being sufficient to match the processing capacity of the set of one or more graphics processing units for generating the data processing output; and When the data processing output is generated, the functional unit performs the processing operation when operating in combination with a set of one or more data processing units.

[0025] The applicant has recognized that in a data processing system comprising graphics processing units that can operate independently or in combination, data processing outputs (e.g., frames) with different possible performance levels corresponding to different graphics processing units can be generated, and that data processing outputs (e.g., frames) can be generated using combinations of graphics processing units. For example, when multiple graphics processing units are used in combination to generate frames, frames can be generated with higher performance (e.g., at relatively higher speed and / or resolution) compared to frames generated by a single graphics processing unit among those operating independently. Furthermore, when the maximum possible number of graphics processing units that can be used in combination are used in combination, the data processing system is generally able to generate data processing outputs (e.g., frames) with the maximum possible performance.

[0026] This means that, when multiple graphics processing units (GPUs) are used in combination to generate such data processing outputs (e.g., frames), the functional unit (e.g., a tiling unit) performing the processing operation should be able to receive the input of the processing operation and / or perform the processing operation and / or generate the output of the processing operation at a rate fast enough to match the performance level of the multiple GPUs. In other words, it is desirable that the throughput (processing capacity) of the functional unit matches the throughput (processing capacity) of the multiple GPUs operating in combination, for example, to avoid a "bottleneck" and performance degradation.

[0027] While all functional units in a plurality of functional units can be configured to have sufficiently high (maximum supported) throughput (processing capacity) for any combination of available graphics processing units, the applicant has recognized that such high system performance is typically only achievable when the maximum possible number of graphics processing units are operated in combination, and that lower performance levels are generally resulted whenever fewer graphics processing units are used to generate data processing output. Therefore, and as will be discussed in more detail below, not all of the plurality of functional units (e.g., tiling units) require such relatively high throughput (processing capacity). Instead, one or more functional units in a plurality of functional units may have lower (maximum) throughput (processing capacity).

[0028] Therefore, the techniques described herein provide functional units with varying (maximum) throughput (processing capacity). As discussed in more detail below, different (maximum supported) throughputs (processing capacities) of different functional units can be tuned to match different possible system performance levels corresponding to different graphics processing units and combinations of graphics processing units used to generate data processing outputs (e.g., frames). This can result in a reduction in the overall hardware / silicon area cost associated with the functional units, while still providing the desired system performance.

[0029] Therefore, it should be understood that the techniques described herein provide improved data processing systems.

[0030] The data processing system described herein may include any desired number of graphics processing units. In one embodiment, there are multiple graphics processing units in powers of 2 (e.g., two, four, or eight). However, other numbers of graphics processing units are also possible, such as three or six.

[0031] The graphics processing unit may include any suitable and desired form of graphics processing unit (graphics processor (GPU)). These graphics processing units can perform any suitable and desired form of graphics processing, such as raster-based rendering, ray tracing, hybrid ray tracing, etc. In one embodiment, each graphics processing unit is a tile-based graphics processing unit.

[0032] In one embodiment, each graphics processing unit includes one or more programmable circuits that can be programmed to perform desired graphics processing operations. For example, in one embodiment, each graphics processing unit includes a collection of one or more execution units (such as, and in one embodiment, one or more shader (programmable processing) cores). In one embodiment, each such execution unit (e.g., a shader core) is operable to execute (e.g., shader) program instructions to perform processing operations (such as, and in one embodiment, vertex processing operations (such as vertex shading) and / or fragment processing operations (such as fragment shading)) indicated by the program instructions.

[0033] Different graphics processing units (GPUs) in a plurality of GPUs may have the same or different numbers of execution units (e.g., shader cores). In one embodiment, a GPU (and in another embodiment, each GPU) includes a plurality of execution units, such as three or four execution units (programmable processing (shader) cores). It should be understood here that, in one embodiment, the (maximum supported) throughput (processing capacity) of a GPU and therefore a set (partition) of one or more GPUs will be proportional to the number of execution units included in the GPU or the set (partition) of one or more GPUs.

[0034] As discussed above, in the techniques described herein, some graphics processing units (and in one embodiment, all graphics processing units) should be able to operate in combination with at least one other graphics processing unit among a plurality of graphics processing units to generate the same data processing output (e.g., a frame).

[0035] In one implementation, the combined operation of graphics processing units includes execution units of different graphics processing units performing processing operations to generate the same data processing output, such as an output frame for display. For example, execution units of different graphics processing units may perform vertex and / or fragment processing operations (e.g., vertex or fragment shading) to generate the same rendering output (frame), for example, in parallel.

[0036] The graphics processing unit (GPU) can operate in combination with some, but not all, of the other GPUs in a plurality of GPUs, or in combination with all other GPUs in a plurality of GPUs. Furthermore, as will be discussed in more detail below, the system can be configured such that the GPU can operate in combination with a different number of other GPUs in a plurality of GPUs.

[0037] Therefore, a set of multiple graphics processing units that operate in combination to generate the (identical) data processing output may include two or more graphics processing units from a plurality of graphics processing units. This set may include all graphics processing units within the plurality of graphics processing units included in the data processing system, or only a subset of those graphics processing units.

[0038] To facilitate combined operation, in one embodiment, the graphics processing units that can operate in combination with each other are interconnected, enabling them to communicate with each other. Therefore, in one embodiment, the combination of graphics processing units to generate data processing output will include communication between the graphics processing units.

[0039] In one embodiment, each graphics processing unit includes an interconnect, and the graphics processing units are interconnected to each other via their respective interconnects.

[0040] Each graphics processing unit (GPU) can be directly connected to each and every other GPU that it can operate in combination with (and thus communicate directly with). GPUs can be connected in a “star” topology or via packet-based interconnects. However, in one embodiment, GPUs are connected in a “daisy-chain” topology.

[0041] Therefore, in one embodiment, the graphics processing units are arranged in sequence, and only the interconnects of adjacent pairs of graphics processing units in the sequence are directly connected to each other. In one embodiment, all graphics processing units of a plurality of graphics processing units are connected in such a way that they are connected in a "daisy-chain" sequence.

[0042] Therefore, in one embodiment, the interconnect of each graphics processing unit is connected to the interconnect of any one or two other graphics processing units. Each interconnect may also be configured to facilitate communication with internal components of the respective graphics processing unit, such as, and in one embodiment, a collection of one or more execution units.

[0043] Communication between graphics processing units operating in combination can take any suitable form. In one implementation, a master-slave relationship exists between the communicating graphics processing units.

[0044] Therefore, in one embodiment, some or all of the graphics processing units (and in one embodiment, each graphics processing unit) are operable to act as a primary (main) graphics processing unit and / or a secondary (subordinate) graphics processing unit. When operating as a primary (main) graphics processing unit, the graphics processing unit can control processing operations on one or more other graphics processing units, each of which acts as a secondary (subordinate) graphics processing unit. When operating as a secondary (subordinate) graphics processing unit, the graphics processing unit can perform processing operations under the control of another graphics processing unit that acts as a primary (main) graphics processing unit.

[0045] Therefore, in one embodiment, the set of multiple graphics processing units that generate data processing outputs in combination with each other includes (only) one graphics processing unit that acts as a primary (main) graphics processing unit, and one or more other graphics processing units that each act as a secondary (minor) graphics processing unit.

[0046] Therefore, in one embodiment, some or all of the graphics processing units (and in one embodiment, each graphics processing unit) are operable to generate data processing output in combination with at least one other graphics processing unit among a plurality of graphics processing units, under the control of the respective graphics processing unit or under the control of one of the graphics processing units in at least one other graphics processing unit.

[0047] In one embodiment, the graphics processing unit (GPU) may control only the GPU following the GPU in a daisy-chain sequence (i.e., acting as a master device). Correspondingly, in one embodiment, the GPU may be controlled only by the GPU preceding the GPU in a daisy-chain sequence (i.e., acting as a slave device). In one embodiment, this arrangement allows the GPU to control only a consecutive set of one or more other GPUs (i.e., acting as master devices), which in turn follow the GPU in a daisy-chain sequence (and each act as a slave device).

[0048] Therefore, in one implementation, the set of multiple graphics processing units that generate data processing outputs in combination with each other is a set of consecutive graphics processing units (in the form of a "daisy chain" sequence).

[0049] As already mentioned, some of the graphics processing units (and in one embodiment, all of the graphics processing units) should also be able to operate (and in one embodiment, be able to operate) to generate data processing outputs (e.g., frames) independently of each of the other graphics processing units (without combining with any of the other graphics processing units).

[0050] In other words, in one implementation, some of the multiple graphics processing units (and in another implementation, all graphics processing units) are able to operate in an “independent” mode. In this mode, the graphics processing units (a collection of only one graphics processing unit) can generate data processing outputs (e.g., frames) in a substantially normal manner for the type of graphics processing unit under consideration.

[0051] To facilitate this, in one implementation, when the graphics processing unit operates in stand-alone mode, communication between the graphics processing unit and any other graphics processing units it is connected to (via their interconnects) is disabled.

[0052] Therefore, in one embodiment, each of the plurality of graphics processing units (GPUs) can operate in master mode and / or slave mode and / or independent mode. A GPU may be able to operate in only one mode (e.g., slave-only), in only two different modes (e.g., independent or master mode, or independent or slave mode), or in each of three modes (i.e., independent, master, or slave mode), depending on, for example, and in one embodiment, the layout of the GPUs and the number of GPUs present in the data processing system.

[0053] In cases where there may be multiple different modes, in one implementation, the operating mode of the graphics processing unit can be set in use, for example, and in another implementation, it can be set in use by appropriately configuring the graphics processing unit using, for example, software.

[0054] Therefore, in one embodiment, one or more graphics processing units (and in one embodiment, each graphics processing unit) may be configured to operate in at least two different operating modes, and the system includes control circuitry configured to configure each configurable graphics processing unit to operate in a selected operating mode of at least two different operating modes. In one embodiment, the at least two different operating modes include two or all of the following operating modes: independent operating mode, master operating mode, and slave operating mode.

[0055] In one embodiment, the control circuitry includes a set of control registers, which can be set, for example, and in one embodiment by software executed on the (host) processor, to configure each graphics processing unit to operate in a desired mode.

[0056] As already mentioned, the data processing system should be operable (and in one embodiment, operable) such that different sets of one or more graphics processing units among a plurality of graphics processing units can perform processing operations independently of each other. That is, the plurality of graphics processing units should be divisible (and in one embodiment, divisible into) one or more sets (partitions) of one or more graphics processors, wherein each set (partition) of one or more graphics processing units is operable to generate data processing output independently of any other set of one or more processing units among the one or more sets of one or more sets of one or more processing units. In one embodiment, different sets (partitions) can simultaneously generate different data processing outputs (e.g., different frames for display on different displays).

[0057] In one implementation, there are multiple possible operating modes in which the system can operate, wherein in each different operating mode, the multiple graphics processing units are divided in a different manner (in other words, each operating mode corresponds to a different division (subdivision into different partitions) of the set of all graphics processing units). For example, in one operating mode, all graphics processing units may be included in a single partition (and therefore all graphics processors can operate together in combination); in another operating mode, a first subset of graphics processing units may be included in one partition and the remaining graphics processing units may be included in another partition; in yet another operating mode, a second distinct subset of graphics processing units may be included in one partition and the remaining graphics processing units may be included in another partition, and so on. In other operating modes, the graphics processing units may be divided into three, four, or more partitions, etc.

[0058] Therefore, multiple graphics processing units can be divided by the control circuit into (and into) any suitable and desired number of (independently functioning) partitions, such as one, two, three, four, or more partitions. In one embodiment, there exists a maximum number of partitions that the system can support at any given time. In this case, in one embodiment, the graphics processing units can be divided into a number of partitions, up to and including the maximum number of partitions. The maximum number of partitions can be, for example, two, four, eight, or another number of partitions at any given time.

[0059] To facilitate this implementation, in one embodiment, the control circuitry is configured to configure each configurable graphics processing unit such that the plurality of graphics processing units are divided into one or more sets (partitions) of one or more graphics processing units (corresponding to one of a plurality of possible operating modes). For example, in one embodiment, the control circuitry configures each configurable graphics processing unit such that each set (partition) of one or more graphics processing units includes only one graphics processing unit operating in an independent mode, or a master graphics processing unit and one or more slave graphics processing units.

[0060] Therefore, in one embodiment, a plurality of graphics processing units are divided by a control circuit into one or more sets (partitions) of one or more graphics processing units (corresponding to one of a plurality of possible operating modes), wherein each set (partition) of one or more graphics processing units is operable to (independently) generate data processing output (e.g., frames).

[0061] In one implementation, each graphics processing unit (GPU) capable of operating in independent mode may receive graphics processing instructions, for example, from a host processor or virtual machine (a driver executing on the host processor or virtual machine) that requires data processing output, and execute the received instructions independently. For example, in one implementation, each GPU with independent capabilities has associated (task) management circuitry (e.g., a job manager) that provides a suitable software interface for the GPU operating in independent mode.

[0062] Accordingly, in one embodiment, each graphics processing unit (GPU) capable of master mode operation may receive graphics processing instructions, for example, from a host processor or virtual machine (a driver executing on the host processor or virtual machine) that requires data processing output, and cause the instructions to be executed by the master GPU and one or more slave GPUs that it is controlling in combination. In one embodiment, each GPU with master capabilities has associated management circuitry (e.g., a job manager) that provides a suitable software interface for itself and the set of one or more slave GPUs that it is controlling. In one embodiment, this has the effect that for any external application and driver using the data processing system, it appears as if only a single GPU exists.

[0063] The data processing system and / or graphics processing unit of the technology described herein may, as appropriate, include one or more features described in the following applications: US 2017 / 0236244, the entire contents of which are incorporated herein by reference; and / or US 2019 / 0056955, the entire contents of which are incorporated herein by reference.

[0064] The system comprises multiple functional units, each operable to perform (and execute) the same (type of) processing operation to generate data processing output (e.g., frames). (It should be understood that while each functional unit is configured to perform the same type of processing operation, such as tiling, in use, each functional unit will perform the operation for its own set of input data and produce its own corresponding output based on that input data.)

[0065] Each functional unit is capable of operating in combination with a set (partition) of one or more graphics processing units. The functional unit should be able to (and in one embodiment, be able to) operate in combination with only one partition at any given time, but may operate in combination with different partitions at different times. When operating in combination with a set (partition) of one or more graphics processing units, the functional unit should perform (and in one embodiment, will perform) a processing operation. This arrangement should be such that (and in one embodiment, such that) when performing a processing operation, the functional unit consumes input to the processing operation from the set (partition) of one or more graphics processing units (the execution unit) with which it is operating in combination, and / or generates output for the processing operation.

[0066] Each of the multiple functional units is configured to perform the same (type) of processing operation, but one or more of the multiple functional units have a higher supported (maximum) throughput (processing capacity) than one or more other functional units in the multiple functional units used to perform the processing operation under consideration (i.e., at least some of the functional units will have different maximum (possible) throughput when performing the processing operation (processing capacity used to perform the processing operation) (for a given set of input data).

[0067] For example, a functional unit may be able to perform processing operations in a shorter time than another functional unit, and / or a functional unit may be able to perform more instances of processing operations at the same time (e.g., in parallel) than another functional unit. Therefore, in one embodiment, there is at least one “higher throughput” (processing capacity) functional unit and at least one “lower throughput” (processing capacity) functional unit.

[0068] The throughput (processing capacity) of a functional unit can be related to and correspond to the rate at which the functional unit (from a given set of input data) produces (provides) the output (of which) for a processing operation. Therefore, a functional unit with higher throughput (processing capacity) can produce the output of a processing operation at a faster rate than a functional unit with lower throughput (processing capacity). Similarly, the throughput (processing capacity) of a functional unit can be related to and correspond to the rate at which the functional unit receives and processes the input data (of a given set) for a processing operation. Therefore, a functional unit with higher throughput (processing capacity) can consume the input of a processing operation at a faster rate than a functional unit with lower throughput (processing capacity).

[0069] This arrangement should ensure (and in one embodiment, ensure) that, whenever possible, each set (partition) of one or more graphics processing units will operate in combination with functional units of a plurality of functional units that have sufficient (maximum supported) throughput (processing capacity) for that set (partition) of one or more graphics processing units. Thus, in one embodiment, the (maximum supported) throughput (processing capacity) of the functional units is such that the output of the processing operation is generated at a rate (at least) as fast as the rate at which the (associated) set (partition) of one or more graphics processing units will (be able to or expect to) consume the output, and / or that the input of the processing operation is consumed at a rate (at least) as fast as the rate at which the (associated) set (partition) of one or more graphics processing units will (be able to or expect to) generate the input.

[0070] For example, in the case of a tiling unit, the time expected to be spent by the tiling unit preparing the primitive list for a typical frame may be approximately equal to or less than the time expected to be spent by the execution units of a set (partition) of one or more graphics processing units performing vertex processing operations to generate the processed vertex data used by the tiling unit to prepare the primitive list and / or the time expected to be spent by the execution units performing fragment processing operations using the primitive list prepared by the tiling unit.

[0071] Different functional units can be provided with different (maximum supported) processing capacities (throughput) in any suitable and desired manner. For example, in one embodiment, different functional units may have different hardware capabilities, such as due to different numbers of transistors and / or different clock speeds. Thus, in one embodiment, at least one "higher throughput" functional unit includes a higher transistor count and / or can operate at a higher clock speed than at least one "lower throughput" functional unit.

[0072] Multiple functional units can include any suitable and desired number of functional units, such as two, four, eight, or another number of functional units. The number of functional units in multiple functional units can be greater than or equal to the maximum number of partitions that the system can support at any given time, for example, such that each partition can be independently combined with a corresponding functional unit in the functional unit for operation. However, fewer functional units can be provided.

[0073] Different (maximum supported) throughput (processing capacity) of functional units can be selected as needed.

[0074] In one implementation, there exists a maximum possible number of graphics processing units (GPUs) that can operate in combination with each other to generate data processing output (as a single partition), and in one implementation, this operation corresponds to the maximum possible system performance. The maximum possible number of GPUs that can operate in combination may correspond to only some of the multiple GPUs, or it may correspond to all GPUs that operate in combination with each other.

[0075] To facilitate this, in one embodiment, the (maximum supported) throughput (processing capacity) of at least one (“higher throughput”) functional unit (each of the multiple functional units) is sufficient to match the throughput (processing capacity) of the maximum possible number (e.g., all) graphics processing units operating in combination (to generate the same data processing output). (Therefore, in one embodiment, the throughput (processing capacity) of the functional unit is such that the output of the processing operation is generated at a rate (at least) as fast as the rate at which the maximum possible number (e.g., all) graphics processing units operating in combination (to generate the same data processing output) would (be able to or expect to) consume the output, and / or the input of the processing operation is consumed at a rate (at least) as fast as the rate at which the maximum possible number (e.g., all) graphics processing units operating in combination (to generate the same data processing output) would (be able to or expect to) generate the input.) In one embodiment, such a (“highest throughput”) functional unit will operate in combination with a set (partition) of the maximum possible number (e.g., all) graphics processing units that generate data processing output.

[0076] Accordingly, in one implementation, the (maximum supported) throughput (processing capacity) of at least one (“higher throughput”) functional unit (each of the multiple functional units) is sufficient to match the throughput (processing capacity) of the maximum possible number (e.g., all) execution units (of the maximum possible number of graphics processing units) that operate in combination (to generate the same data processing output).

[0077] As discussed above, the applicant recognizes that not all of the multiple functional units require (support) such a relatively high (maximum) throughput (processing capacity). Therefore, in one embodiment, the (maximum supported) throughput (processing capacity) of at least one other (“lower throughput”) functional unit (each of the multiple functional units) is insufficient (different from) the throughput (processing capacity) of the maximum possible number (e.g., all) graphics processing units operating in a matched combination. (Therefore, in one embodiment, the (maximum supported) throughput (processing capacity) of the functional unit is such that the output of the processing operation is produced at a rate less than the rate at which the maximum possible number (e.g., all) graphics processing units operating in a combined manner (to generate the same data processing output) would (be able to or expect to) consume that output, and / or the input of the processing operation is consumed at a rate less than the rate at which the maximum possible number (e.g., all) graphics processing units operating in a combined manner (to generate the same data processing output) would (be able to or expect to) generate that input.)

[0078] For example, the time that such a (“lower throughput” tiling unit is expected to take to prepare a list of primitives for a typical frame should be greater than (and in one implementation, greater than) the time that the maximum possible number (e.g., all) of execution units operating in combination are expected to take to perform vertex or fragment processing operations for that frame.

[0079] In one implementation, the arrangement is such that the (maximum supported) throughput (processing capacity) of at least one other (“lower throughput”) functional unit (each of the multiple functional units) is sufficient to match the throughput (processing capacity) of some, but not all, of the maximum possible number of execution units (of the maximum possible number of graphics processing units) operating in combination.

[0080] In one implementation, the (maximum supported) throughput (processing capacity) of at least one other ("lower throughput") functional unit (each of the multiple functional units) matches the throughput (processing capacity) of a selected number of execution units among the maximum possible number of execution units operating in combination (the maximum possible number of graphics processing units). (Therefore, in one implementation, the throughput (processing capacity) of the functional unit is such that the output of the processing operation is produced at a rate matching the rate at which the selected number of graphics processing units operating in combination (to generate the same data processing output) will (be able to or expect to) consume the output, and / or the input of the processing operation is consumed at a rate matching the rate at which the selected number of graphics processing units operating in combination (to generate the same data processing output) will (be able to or expect to) generate the input.)

[0081] For example, in one implementation, the time that such a (“lower throughput” tiling unit is expected to take to prepare a list of primitives for a typical frame is roughly equal to the time that the selected number of execution units is expected to take to perform vertex or fragment processing operations for that frame.

[0082] In this context, in one implementation, when generating data processing output, at least one (“higher throughput”) functional unit will operate in combination with a set (partition) of one or more graphics processing units that include more than the selected number of execution units.

[0083] In the case of a set (partition) comprising one or more graphics processing units comprising less than or equal to the selected number of execution units, at least one (“higher throughput”) functional unit may operate in combination with the set, but in one embodiment, at least one (“lower throughput”) functional unit will operate in combination with the set.

[0084] The selected number of execution units can be, for example, two, three, four, five, six, seven, eight, or more execution units. When each graphics processing unit includes the same number of execution units, the selected number of execution units can be a positive integer multiple of the number of execution units included in each graphics processing unit, such as one, two, three, or more times the number of execution units included in each graphics processing unit.

[0085] Although two different (maximum supported) throughput (processing capacity) values, namely "higher" and "lower," were mentioned above, multiple functional units can include more than two different throughput (processing capacity) functional units. Therefore, there can be two or more (such as three or four) functional units with different throughput (processing capacity). In this case, the different possible throughputs (processing capacities) of the functional units can be matched with the throughputs (processing capacities) corresponding to different selected numbers of graphics processing units and / or execution units.

[0086] However, in one implementation, only two distinct throughput (processing capacity) functional units exist. Therefore, in one implementation, the (maximum supported) throughput (processing capacity) of each of the multiple functional units is either a first throughput (processing capacity) or a second lower throughput (processing capacity). In one implementation, the multiple functional units consist of (only) at least one (“higher throughput”) functional unit and at least one other (“lower throughput”) functional unit. Having fewer possible throughputs (processing capacities) reduces system complexity.

[0087] Multiple functional units can be provided in any suitable and desired manner.

[0088] In one embodiment, the functional unit is provided as part of a corresponding graphics processing unit. Therefore, in one embodiment, each of the plurality of functional units is included in a corresponding (different) graphics processing unit among the plurality of graphics processing units. Only some of the graphics processing units (but in one embodiment, all graphics processing units) may include the corresponding functional unit. (It should be understood here that when a graphics processing unit includes a functional unit, the graphics processing unit will be able to operate independently, and in one embodiment, as a “standalone” graphics processing unit. On the other hand, any graphics processing unit that does not itself include a functional unit may only be able to operate in combination with another graphics processing unit (including a functional unit).)

[0089] The functional units included in the graphics processing unit may be provided as separate circuit elements to the set of execution units of the graphics processing unit, or the set of functional units and execution units may share at least some processing circuitry. The functional units included in the graphics processing unit may be connected to (and communicate via) the interconnects of the graphics processing unit.

[0090] In this context, the (maximum supported) throughput (processing capacity) of each functional unit should (at least) match the specific requirements of the graphics processing unit to which that functional unit is included. For example, in an implementation where the graphics processing unit can operate in standalone mode rather than master mode, the graphics processing unit may include a "minimum throughput" functional unit, because in this case, the functional unit may at most need to match the throughput (processing capacity) of a single graphics processing unit operating independently.

[0091] On the other hand, when the graphics processing unit (GPU) can operate in master mode, the GPU may include (and in one embodiment, does include) functional units having a throughput (processing capacity) depending on the maximum number of other GPUs it can control. For example, and in one embodiment, GPUs that can control more than a selected number of other GPUs (and in one embodiment, each GPU) include “higher throughput” functional units, and GPUs that can control only a number less than or equal to the selected number of other GPUs (and in one embodiment, each GPU) include “lower throughput” functional units. The selected number may be, for example, one, two, or more other GPUs.

[0092] Therefore, in one implementation, the throughput (processing capacity) of each of the plurality of functional units is matched with the throughput (processing capacity) of the graphics processing unit in which the respective functional unit is included, and the throughput (processing capacity) of any other graphics processing unit among the plurality of graphics processing units that the graphics processing unit in which the respective functional unit is included can control.

[0093] For example, when graphics processing units are connected in a "daisy-chain" sequence (e.g., as discussed above), the first graphics processing unit in the sequence may, for example, include a "highest throughput" functional unit and be able to control the maximum possible number of other graphics processing units. Similarly, the last graphics processing unit in the sequence (which can operate in independent mode) may, for example, include a "lowest throughput" functional unit and cannot control any other graphics processing units. This can, for example, simplify the scope of system verification. (However, in general, there are no restrictions on the capabilities of the units and their position in the "daisy-chain" sequence.)

[0094] It should be understood that a graphics processing unit operating in a mode can operate in combination with functional units included in a corresponding main graphics processing unit under its control. Therefore, a graphics processing unit that can only operate in a mode does not need to include a corresponding functional unit. Thus, in one embodiment, any graphics processing unit that can only operate in a mode may not include a corresponding functional unit. This reduces the total number of functional units and thus lowers silicon / hardware area costs.

[0095] In another embodiment, instead of including every functional unit within the graphics processing unit, multiple functional units are arranged in a functional unit pool, which in one embodiment is external to (separate from) the multiple graphics processing units. In this case, the system can be configured such that functional units can be assigned to partitions in use and as needed (e.g., under software control). For example, a first functional unit in the pool can be assigned to a first set (partition) of one or more graphics processing units, while a second functional unit in the pool is assigned to a second set (partition) of one or more graphics processing units (and so on, if needed).

[0096] (It should be noted in this regard that, in this case, a collection (partition) of one or more graphics processing units may only be able to operate to generate data processing output when operating in combination with (associated) functional units (from the pool). Therefore, in this case, the graphics processing unit itself may not be "complete," but may also require the operation of functional units.)

[0097] In this context, the functional units in the pool should have (and in one embodiment, indeed have) an appropriate allocation of (maximum supported) throughput (processing capacity) to enable the use and execution of desired combinations of graphics processing units, such as each desired operating mode (where sufficient functional unit throughput (processing capacity) is available for each partition), as will be described below. Therefore, in one embodiment, the allocation of functional unit throughput (processing capacity) in the pool is based on the throughput (processing capacity) of the (desired / allowed) combinations of graphics processing units (operating modes) that the system is intended to support.

[0098] In these implementations, when a collection (partition) of one or more graphics processing units is to generate data output, a functional unit from the pool is selected and assigned to that partition in one implementation.

[0099] In one implementation, a functional unit is selected (in use) for a set (partition) of one or more graphics processing units based on the throughput (processing capacity) of the set (partition) of one or more graphics processing units when generating data processing output (and the throughput (processing capacity) of the functional unit when performing processing operations).

[0100] The function unit to be used can be selected based on the rate at which the set (partition) of one or more graphics processing units consumes the output of the function unit processing operation (which will need to be provided with the output of the function unit processing operation (to avoid bottlenecks)) when generating data processing output (and the rate at which different function units will produce the output of the function unit processing operation when the processing operation is executed) and / or based on the rate at which the set (partition) of one or more graphics processing units will produce the input of the function unit processing operation (to avoid bottlenecks) when generating data processing output (and the rate at which different function units will consume the input of the function unit processing operation when the processing operation is executed).

[0101] For example, in one implementation, a “higher throughput” function unit is selected for a partition that includes a relatively large number of graphics processing units (and / or execution units), and in another implementation, a “lower throughput” function unit is selected for a partition that includes a relatively small number of graphics processing units (and / or execution units).

[0102] This operation can be implemented in any suitable and desired manner. In one embodiment, the system includes: a configurable interconnect that routes communication between functional units in a pool and graphics processing units; and control circuitry that can select functional units in the pool based on the throughput (processing capacity) of a set (partition) of one or more graphics processing units, and can configure the configurable interconnection to appropriately route communication between the selected functional units and the set (partition) of one or more graphics processing units.

[0103] As discussed above, each of at least one (“higher throughput”) functional unit will typically occupy a larger silicon area than each of at least one other (“lower throughput”) functional unit. Therefore, in one embodiment, the overall hardware / silicon area cost associated with the multiple functional units should be less than (and in one embodiment, less than) the cost originally required if all functional units were (“higher throughput”) functional units (e.g., the throughput (processing capacity) of the maximum possible number (e.g., all) graphics processing units that can be operated in a matched combination).

[0104] In one implementation, the number of "higher throughput" functional units is minimized, for example, to minimize the hardware / silicon costs associated with the "higher throughput" functional units. This can be achieved in any suitable and desirable manner.

[0105] In one implementation, the number of operable operating modes of the system is limited, such that the number of “higher throughput” functional units required to operate in each of these modes is less than the number of “higher throughput” functional units originally required for more possible operating modes.

[0106] Therefore, in one embodiment, multiple graphics processing units may be partitioned (by control circuitry) according to each of a selected (in one embodiment, limited) set of multiple different operating modes. In one embodiment, the selected set of multiple different operating modes is selected (limited) such that the number of “higher throughput” functional units required to operate in each of these modes (where sufficient functional unit throughput (processing capacity) is available for each partition) is less than the number of “higher throughput” functional units would originally be required in the case of more permitted operating modes (included in the selected set).

[0107] Accordingly, in one implementation, the (maximum supported) throughput (processing capacity) of each of the plurality of functional units is selected based on possible operating modes, for example, based on a selected set of a plurality of different operating modes. In one implementation, the selection of throughput (processing capacity) is such that all operating modes (in the selected set of a plurality of different operating modes) can operate with sufficient functional unit throughput (processing capacity) for each partition, that is, in each operating mode, each set (partition) of one or more graphics processing units will operate in combination with functional units of the plurality of functional units that have sufficient throughput (processing capacity) for that set (partition) of one or more graphics processing units.

[0108] In one implementation, the minimum possible functional unit throughput (processing capacity) is selected, which allows all operating modes (in the selected set of multiple different operating modes) to operate with sufficient functional unit throughput (processing capacity) in each partition.

[0109] It is believed that the idea of ​​selecting and providing different functional unit throughputs (processing capacities) in this way is itself novel and creative.

[0110] Another embodiment of the technology described herein includes a method for providing a data processing system, the data processing system including a plurality of graphics processing units and a plurality of functional units configured to perform the same processing operations, the method comprising: The plurality of graphics processing units are provided, wherein one or more of the graphics processing units are capable of operating in combination with at least one other graphics processing unit among the plurality of graphics processing units; A control circuit is provided, configured to divide a plurality of graphics processing units into one or more sets of one or more graphics processing units according to an operating mode in a selected set of a plurality of different operating modes, such that each set of one or more graphics processing units can operate to generate data processing output; and The plurality of functional units are provided, each of which can operate in combination with a set of one or more graphics processing units when generating data processing output, and wherein at least one of the plurality of functional units has a throughput greater than at least one other of the plurality of functional units when performing the processing operation. The multiple functional units include a selection set based on multiple different operating modes to select the throughput of the functional unit when performing the processing operation.

[0111] Another embodiment of the technology described herein includes a method for providing a data processing system, the data processing system comprising a plurality of graphics processing units and a plurality of functional units configured to perform the same type of processing operations, the method comprising: The plurality of graphics processing units are provided, wherein one or more of the graphics processing units are capable of operating in combination with at least one other graphics processing unit among the plurality of graphics processing units; A control circuit is provided, configured to divide a plurality of graphics processing units into one or more sets of one or more graphics processing units according to an operating mode in a selected set of a plurality of different operating modes, such that each set of one or more graphics processing units can operate to generate data processing output; and The plurality of functional units are provided, each of which can operate in combination with a set of one or more graphics processing units when generating data processing output, and wherein the processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other of the plurality of functional units for performing the processing operation. The multiple functional units include a selection of the processing capacity of the functional unit for performing the processing operation based on a selection set of multiple different operating modes.

[0112] These implementation schemes may include any one or more, or all, of the optional features described herein, as appropriate.

[0113] A functional unit can be any suitable functional unit that can perform any appropriate processing operation when operating in combination with a graphics processing unit while generating data processing output.

[0114] In one implementation, each functional unit is a fixed functional unit or accelerator, i.e., a circuit dedicated to one or more fixed functions (i.e., functions that cannot be changed).

[0115] In one implementation, each functional unit is a memory management unit (MMU), and the processing operation in one implementation is a memory management operation (such as memory address translation). The input of the processing operation can be a memory address, and the output of the processing operation can be a translated memory address. In this case, in one implementation, generating data processing output (when a set of one or more functional units and graphics processing units operates in combination) includes one memory management unit in the memory management unit (MMU) performing one or more memory management operations, such as generating one or more translated memory addresses, and execution units of a set (partition) of one or more graphics processing units performing processing operations using the output of the memory management operations (e.g., one or more translated memory addresses), for example, when reading data from or writing data to external memory.

[0116] In another embodiment, each functional unit is a (task) management circuit (e.g., a job manager), and the processing operation is to divide (process) the task into subtasks and assign the subtasks to execution units. In this case, in one embodiment, generating data processing output (when the functional unit operates in combination with a set of one or more graphics processing units) includes a management circuit dividing the task into subtasks and assigning the subtasks to an execution unit of a set (partition) of one or more graphics processing units, and the execution unit executing the assigned subtask.

[0117] As mentioned, in one embodiment, each functional unit is a tile unit (tile), the processing operation in one embodiment is preparing a list of primitives for tile-based rendering, the input of the processing operation is the processed vertex data, and the output of the processing operation in one embodiment is a list of geometry (e.g., primitives) for the corresponding region (area) of the output being generated. Therefore, in one embodiment, the data processing system is a tile-based graphics processing system, and each graphics processing unit is a tile-based graphics processing unit.

[0118] In this context, in one implementation, generating data processing output (when the functional unit operates in combination with a set of one or more graphics processing units in the graphics processing unit) includes an execution unit of a set of one or more graphics processing units (partitions) performing vertex processing operations to generate processed vertex data, a tile in a tiling unit preparing a list of output region geometry (e.g., primitives) using the processed vertex data, and in one implementation, an execution unit of a set of one or more graphics processing units (partitions) using the list of geometry (e.g., primitives) prepared by the tiling unit to perform fragment processing operations.

[0119] In one implementation, vertex processing and geometry (e.g., primitive) list preparation operations are efficiently combined. For example, in one implementation, a tiling unit assigns vertex processing tasks to an execution unit to generate processed vertex data, which the tiling unit uses to prepare a geometry (e.g., primitive) list. In this case, each tiling unit can effectively operate as a task management circuit, for example, as described above in one implementation. Other arrangements are possible.

[0120] It is believed that, in the context of a graphics processing system comprising multiple composable graphics processing units, the idea of ​​tiling units having different (maximum supported) tiling throughput (processing capacity) is itself novel and inventive.

[0121] Therefore, another embodiment of the technology described herein includes a graphics processing system comprising: A plurality of graphics processing units, each operable to perform tile-based rendering, wherein two or more of the graphics processing units are operable in combination with at least one other graphics processing unit; and Multiple tiled units; The throughput of at least one of the plurality of tiled units is greater than the throughput of at least one other tiled unit among the plurality of tiled units.

[0122] Another embodiment of the technology described herein includes a method of operating a graphics processing system, the graphics processing system comprising: A plurality of graphics processing units, each operable to perform tile-based rendering, wherein two or more of the graphics processing units are operable in combination with at least one other graphics processing unit; and Multiple tiled units; Where the throughput of at least one of the plurality of tiled units is greater than the throughput of at least one other tiled unit among the plurality of tiled units; The method includes: One of the tiling units operates in combination with one or more of the plurality of graphics processing units when generating the rendered output.

[0123] Another embodiment of the technology described herein includes a graphics processing system comprising: A plurality of graphics processing units, each operable to perform tile-based rendering, wherein two or more of the graphics processing units are operable in combination with at least one other graphics processing unit; and Multiple tiled units; The processing capacity of at least one of the multiple tiled units is greater than the processing capacity of at least one other tiled unit.

[0124] Another embodiment of the technology described herein includes a method of operating a graphics processing system, the graphics processing system comprising: A plurality of graphics processing units, each operable to perform tile-based rendering, wherein two or more of the graphics processing units are operable in combination with at least one other graphics processing unit; and Multiple tiled units; The processing capacity of at least one of the plurality of tiled units is greater than the processing capacity of at least one other tiled unit among the plurality of tiled units; The method includes: One of the tiling units operates in combination with one or more of the plurality of graphics processing units when generating the rendered output.

[0125] These implementations may, as appropriate, include one or more or all of the optional features described herein. For example, one or more graphics processing units may generate processed vertex data used by tiling units to prepare a list of primitives, and one or more graphics processing units may use the prepared list of primitives when generating render output. Similarly, a set of one or more graphics processing units may be configured in one implementation to generate render output (data processing output), and tiling units (functional units) among a plurality of tiling units may be configured in one implementation to prepare a list of output region geometry (e.g., primitives). In one implementation, a set of one or more graphics processing units may operate in combination with tiling units among a plurality of tiling units having a throughput (processing capacity) sufficient to match (and in one implementation, based on) the throughput (processing capacity) of the set of one or more graphics processing units.

[0126] In one implementation, when performing data processing operations, in addition to functional units with different (maximum supported) throughput (processing capacity), the graphics processing unit may also include graphics processing units with different capabilities, such as in one implementation in terms of their performance, and in another implementation in terms of throughput (processing capacity). For example, in one implementation, different graphics processing units may have different numbers of execution units (shader cores). This can then provide further flexibility in terms of the operating modes that can be supported, while still facilitating, for example, a reduction in silicon area.

[0127] Therefore, in one embodiment, the plurality of graphics processing units includes one or more graphics processing units having higher performance than the other graphics processing units among the plurality of graphics processing units, and in another embodiment, it includes one or more graphics processing units having more execution units (shader cores) than the other graphics processing units among the plurality of graphics processing units. For example, each graphics processing unit may have 1 to 3 execution units (shader cores).

[0128] In one implementation, the functional unit throughput (processing capacity) and the number of execution units in different graphics processing units are selected such that desired combinations of graphics processing units and functional units are available and executed, such as each desired operating mode (wherein the functional unit and graphics processing unit throughput (processing capacity) are matched for each partition). Therefore, in one implementation, the allocation of functional unit throughput (processing capacity) and the allocation of the number of execution units are based on the throughput (processing capacity) of the (desired / allowed) combinations of graphics processing units and functional units (operating modes) that the system is intended to support.

[0129] In addition to the graphics processing units, functional units, etc. necessary for operation in the manner described herein, the data (graphics) processing system may also include any other suitable and desirable components, elements, units, etc. that the data processing system may include.

[0130] Therefore, a data processing system may include, for example, one or more peripheral devices, such as one or more output devices (e.g., displays, vehicle controllers, etc.) and / or one or more input devices (e.g., human-machine interfaces, vehicle sensors, etc.).

[0131] In one embodiment, the overall data processing system includes appropriate (system) memory for storing data used by the graphics processing unit and / or functional units during processing and / or for storing data generated by the graphics processing unit and / or functional units as a result of processing. Different groups of graphics processing units and / or functional units may be configured to connect to the same (system) memory, or separate system memories may be provided for different groups.

[0132] Accordingly, different groups of graphics processing units and / or functional units may be connected to external system memory via the same or different memory interconnects.

[0133] In one implementation, the data processing system includes one or more host data processing units (processors) (e.g., central processing units). One or more virtual machines may execute on the host processor. In one implementation, one or more drivers for the graphics processing unit execute on the host processor.

[0134] In one embodiment, the data processing system and / or data and / or graphics processing unit and / or functional module includes one or more memory and / or memory devices for storing the data described herein and / or storing software for performing the processes described herein, and / or communicating with said one or more memory and / or memory devices.

[0135] The techniques described herein can be used for all forms of data processing output that a graphics processing unit (GPU) can output. Therefore, they can be used to generate frames for display, render to texture output, etc. However, the techniques described herein can also be used where the GPU will be used to provide other processing and operations and data processing outputs, such as those that may not involve a display or image. For example, the techniques described herein can also be used in non-graphics use cases, such as ADAS (Advanced Driver Assistance Systems), which may not have a display and can process input data (e.g., sensor data such as radar data) and / or output data (e.g., vehicle control data) that do not involve an image. Similarly, data processing output can be computational data for image recognition or neutral network applications. Generally, the techniques described herein can be used for any desired GPU data processing operations, such as GPGPU (General Purpose GPU) operations.

[0136] In one implementation, the various functions of the technology described herein are performed on a single system-on-chip (SoC) data processing system.

[0137] Although the above description has specifically described functional units that operate in combination with graphics processing units, the techniques described herein are more generally extended to functional units that operate in combination with other (programmable) processing units such as central processing units (CPUs), video processing units, neural network processing units, etc.

[0138] Therefore, another embodiment of the technology described herein includes a data processing system comprising: A plurality of processing units, wherein one or more of the processing units are operable in combination with at least one other processing unit, such that a corresponding set of the one or more processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same processing operation, each functional unit being able to operate in combination with a set of one or more processing units when generating data processing output; The throughput of at least one of the plurality of functional units when performing the processing operation is greater than the throughput of at least one other functional unit when performing the processing operation.

[0139] Another embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: A plurality of processing units, wherein one or more of the processing units are operable in combination with at least one other processing unit, such that a corresponding set of the one or more processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same processing operation, each functional unit being able to operate in combination with a set of one or more processing units when generating data processing output; Wherein at least one of the plurality of functional units has a throughput greater than at least one other functional unit among the plurality of functional units when performing the processing operation; The method includes: Configure a set of one or more processing units from the plurality of processing units to generate data processing output; The functional unit among the plurality of functional units, which has the throughput when performing the processing operation, is configured to operate in combination with the set of one or more processing units when generating the data processing output, the processing capacity being sufficient to match the processing capacity of the set of one or more processing units for generating the data processing output; and When the data processing output is generated, the functional unit performs the processing operation when operating in combination with the set of one or more processing units.

[0140] Another embodiment of the technology described herein includes a method for providing a data processing system, the data processing system comprising multiple processing units and multiple functional units configured to perform the same processing operations, the method comprising: The plurality of processing units are provided, wherein one or more of the processing units are operable in combination with at least one other processing unit among the plurality of processing units; A control circuit is provided, configured to divide a plurality of processing units into one or more sets of processing units according to an operating mode in a selected set of a plurality of different operating modes, such that each set of the one or more processing units is operable to generate a data processing output; and The plurality of functional units are provided, each of which can operate in combination with a set of one or more processing units when generating data processing output, and wherein at least one of the plurality of functional units has a throughput greater than at least one other of the plurality of functional units when performing the processing operation. The multiple functional units include a selection set based on multiple different operating modes to select the throughput of the functional unit when performing the processing operation.

[0141] Another embodiment of the technology described herein includes a data processing system comprising: A plurality of processing units, wherein one or more of the processing units are operable in combination with at least one other processing unit, such that a corresponding set of the one or more processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same type of processing operations, each functional unit being able to operate in combination with a set of one or more processing units when generating data processing output; The processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other functional unit for performing the processing operation.

[0142] Another embodiment of the technology described herein includes a method for operating a data processing system, the data processing system comprising: A plurality of processing units, wherein one or more of the processing units are operable in combination with at least one other processing unit, such that a corresponding set of the one or more processing units can generate a corresponding data processing output; and Multiple functional units configured to perform the same type of processing operations, each functional unit being able to operate in combination with a set of one or more processing units when generating data processing output; The processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other functional unit for performing the processing operation. The method includes: Configure a set of one or more processing units from the plurality of processing units to generate data processing output; The functional unit among the plurality of functional units, having a processing capacity for performing the processing operation, is configured to operate in combination with the set of one or more processing units when generating data processing output, the processing capacity being sufficient to match the processing capacity of the set of one or more processing units for generating the data processing output; and When the data processing output is generated, the functional unit performs the processing operation when operating in combination with the set of one or more processing units.

[0143] Another embodiment of the technology described herein includes a method for providing a data processing system, the data processing system comprising a plurality of processing units and a plurality of functional units configured to perform the same type of processing operations, the method comprising: The plurality of processing units are provided, wherein one or more of the processing units are operable in combination with at least one other processing unit among the plurality of processing units; A control circuit is provided, configured to divide a plurality of processing units into one or more sets of processing units according to an operating mode in a selected set of a plurality of different operating modes, such that each set of the one or more processing units is operable to generate a data processing output; and The plurality of functional units are provided, each of which can operate in combination with a set of one or more processing units when generating data processing output, and wherein the processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other of the plurality of functional units for performing the processing operation. The multiple functional units include a selection of the processing capacity of the functional unit for performing the processing operation based on a selection set of multiple different operating modes.

[0144] As those skilled in the art will understand, these embodiments of the technology described herein may, as appropriate, include (and in one embodiment, do include) any one or more or all optional features of the technology described herein.

[0145] Therefore, for example, each processing unit in one embodiment is a programmable processing unit, and in one embodiment includes one or more programmable circuits that can be programmed to perform desired processing operations. For example, each processing unit in one embodiment includes one or more execution units, each of which is executable program instructions to perform a processing operation indicated by the program instructions.

[0146] These processing units can be any suitable and desired form of processing unit. In one embodiment, they are processing units designed to perform a specific type of processing operation. In one embodiment, all processing units are configured to perform graphics processing operations. Accordingly, execution units in one embodiment are all configured to perform graphics processing operations, for example, and in another embodiment, they are all shader cores. Thus, in one embodiment, the processing unit is a graphics processor, and in the embodiments discussed above, it is a graphics processing unit. However, in other embodiments, the processing unit can be other forms of processing units, such as a central processing unit (CPU), a video processing unit, a neural network processing unit, etc.

[0147] A functional unit can be any suitable and desired form of functional unit appropriate to the processing unit under consideration. In one embodiment, each functional unit is a fixed functional unit or an accelerator. Thus, in one embodiment, each (fixed functional) unit is dedicated to performing processing operations to, for example, generate appropriate outputs for use by one or more processing units (execution units) in the (programmable) processing unit or consume appropriate inputs generated by one or more processing units (execution units) in the (programmable) processing unit (when executing program instructions to generate data processing outputs).

[0148] In one implementation, the processing unit (or execution unit) is configured to execute multiple processing tasks in parallel (independently and simultaneously), and in another implementation, the functional unit is not conducive to this parallelization. For example, in one implementation, each function divides the entire processing task into subtasks and assigns the subtasks to multiple execution units, which execute the subtasks in parallel (independently and simultaneously) in one implementation. Thus, a processing operation could be to divide (process) a task into subtasks and assign the subtasks to execution units for parallel execution.

[0149] As discussed above, when the processing unit is a graphics processor (GPU), the functional unit can be a tiling unit, a (task) management circuit, etc. When the processing unit is a video processing unit, the functional unit can be, for example, a (task) management circuit, a discrete cosine transform (DCT) unit, etc. In other embodiments, the functional unit can be a direct memory access (DMA) controller or a memory data compression / decompression unit (codec).

[0150] Although the functional units described above with reference to perform a single processing operation have been generally described, it should be understood that functional units may also be able to perform other processing operations. For example, multiple functional units may be configured to perform the same set of one or more processing operations. Although the system described above with reference to a single set of multiple functional units all of the same type has been generally described, the system may include other types of functional units. For example, the system may include multiple different sets of multiple functional units, each comprising multiple functional units of the same type. In this case, one or more of the multiple functional units (and in one embodiment, each functional unit) may be arranged and operated according to the techniques described herein.

[0151] The techniques described herein can be implemented in any suitable system, such as a microprocessor-based system capable of proper operation. In some implementations, the techniques described herein are implemented in computer- and / or microprocessor-based systems.

[0152] The various functions of the technology described herein can be performed in any desired and suitable manner. For example, the functions of the technology described herein can be implemented in hardware or software as needed. Thus, for example, the various functional elements, stages, units, and "devices" of the technology described herein may include one or more suitable processors, one or more controllers, functional units, circuit systems, circuits, processing logic, microprocessor arrangements, etc., capable of operating to perform various functions, such as appropriate dedicated hardware elements (processing circuits) and / or programmable hardware elements (processing circuits) that can be programmed to operate in a desired manner.

[0153] It should also be noted that the various functions of the technology described herein can be copied and / or executed in parallel on a given processor. Similarly, various processing stages can share processing circuitry / circuits, etc., if needed.

[0154] Furthermore, any one or more processing stages or units of the technology described herein may be embodied as processing stage or unit circuits, for example, in the form of one or more fixed-function units (hardware) (processing circuits), and / or in the form of programmable processing circuits that can be programmed to perform desired operations. Similarly, any one or more of the processing stages or units and processing stage or unit circuits of the technology described herein may be provided as independent circuit elements to other processing stages or units or processing stage or unit circuits, and / or any one or more or all of the processing stages or units and processing stage or unit circuits may be formed at least partially by shared processing circuitry.

[0155] Those skilled in the art should also understand that all embodiments of the technology described herein may include any one or more or all of the optional features described herein, as appropriate.

[0156] The methods described herein can be implemented at least in part using software, such as computer programs. Therefore, further embodiments of the techniques described herein include: computer software, particularly adapted to perform the methods described herein when installed on a data processor; computer program elements including computer software code portions for performing the methods described herein when the program elements are run on a data processor; and a computer program including code adapted to perform all steps of one or more methods described herein when the program is run on a data processing system. The data processing system may be a microprocessor, a programmable FPGA (Field-Programmable Gate Array), etc.

[0157] The techniques described herein also extend to computer software carriers that, when used to operate a graphics processor, renderer, or other system including a data processor, cause said processor, renderer, or system to perform the steps of the methods described herein in conjunction with said data processor. Such computer software carriers can be physical storage media, such as ROM chips, CD-ROMs, RAM, flash memory, or disks, or they can be signals, such as electronic signals transmitted through wires, optical signals, or radio signals, such as signals to satellites.

[0158] It should also be understood that not all steps of the methods described herein need to be performed by computer software; therefore, other embodiments of the techniques described herein include computer software and such software installed on a computer software carrier for performing at least one step of the methods described herein.

[0159] Therefore, the techniques described herein may suitably be embodied as a computer program product used with a computer system. Such embodiments may include a series of computer-readable instructions fixed on a tangible, non-transitory medium, such as a computer-readable medium, for example, a disk, CD-ROM, ROM, RAM, flash memory, or hard disk. It may also include a series of computer-readable instructions that can be invisibly transmitted to the computer system via a modem or other interface device, through a tangible medium (including but not limited to optical or analog communication lines), or using wireless technologies (including but not limited to microwave, infrared, or other transmission technologies). This series of computer-readable instructions embodies all or part of the functions previously described herein.

[0160] Those skilled in the art will understand that such computer-readable instructions can be written in a variety of programming languages ​​to be used with many computer architectures or operating systems. Furthermore, such instructions can be stored using any current or future memory technology (including, but not limited to, semiconductor, magnetic, or optical technologies), or transmitted using any current or future communication technology (including, but not limited to, optical, infrared, or microwave technologies). It is conceivable that such computer program products can be distributed as removable media with accompanying printed or electronic documentation (e.g., shrink-wrapping software), pre-loaded with a computer system on, for example, a system ROM or a fixed disk, or distributed via a network (e.g., the Internet or the World Wide Web) from a server or electronic bulletin board.

[0161] As discussed above, when generating data processing output (such as frames for display), data processing systems (such as graphics processing systems) typically utilize various functional units (such as tiling units). For example, in a tile-based graphics processing system, generating rendering output (e.g., frames) typically involves a set of execution units (shader cores) of a graphics processing unit (GPU) performing vertex processing operations to generate processed vertex data, a tiling unit preparing a primitive list using the processed vertex data, and then that set of execution units (shader cores) of the GPU performing fragment processing operations using the prepared primitive list. In this case, to ensure efficient rendering output generation, the throughput (processing capacity) of the tiling unit will be matched with the throughput (processing capacity) of the set of execution units (shader cores), for example, to avoid a “bottleneck.” For example, the time expected to be spent by the tiling unit preparing the primitive list for a typical frame will be roughly equal to the time expected to be spent by the set of execution units performing vertex or fragment processing operations for that frame.

[0162] The technology described herein relates to a data processing system comprising multiple connected graphics processing units, wherein different sets (i.e., different “partitions”) of one or more of these graphics processing units can operate independently of each other. For example, such a data processing system may be particularly suitable for automotive applications. For instance, a corresponding partition may be assigned to each of one or more of the following: a display screen for the main instrument console, additional navigation and / or entertainment screens, and advanced driver assistance systems (ADAS) for the vehicle, etc.

[0163] Such systems typically include multiple identical functional units (e.g., multiple tiled units), allowing each partition to use one functional unit independently of other partitions.

[0164] The applicant recognizes that in such a data processing system, the throughput (processing capacity) associated with a partition will be variable; for example, the throughput (processing capacity) will depend on the number of graphics processing units that make up the partition. Furthermore, the maximum possible system throughput (processing capacity) is typically achievable only if, for example, all graphics processing units are combined into a single partition.

[0165] The applicant has recognized that this means that in such a data processing system, it is not necessary for all the multiple functional units (e.g., tiled units) to have a (maximum supported) throughput (processing capacity) that matches the maximum possible system throughput (processing capacity). Instead, and as will be discussed in more detail below, one or more functional units (e.g., tiled units) can be provided with a reduced processing capacity (throughput). This can lead to a reduction in the overall hardware / silicon area cost associated with the multiple functional units (e.g., tiled units), and thus provide a more efficient data processing system.

[0166] Figure 1 A data processing system 9 according to one embodiment is shown, which includes a host processor 1 and a collection of multiple connected graphics processing units 3. It should be understood that... Figure 1 This is merely an illustration, and the system may include components not shown in [the diagram]. Figure 1 Other units and components shown in the diagram.

[0167] In this embodiment, the host processor 1 is a central processing unit (CPU) that directly executes the application 2 for the graphics processing unit 3 and the driver 4. However, in other embodiments, the application and driver may be executed by a virtual machine running on the host processor 1.

[0168] like Figure 1 As shown, in this embodiment, the set of graphics processing units 3 includes a pair of connected graphics processing units (GPUs) 10, 11, which can communicate with each other. The connected graphics processing units 10, 11 can operate in different modes, namely, as “independent” graphics processing units, or as a linked set of primary (master) and secondary (slave) graphics processing units.

[0169] When using this system, application 2 will request one or both of the graphics processing units 10 and 11 to perform graphics processing operations. To do this, application 2 will generate API (Application Programming Interface) calls, which are interpreted by driver 4 to generate appropriate commands to the set of graphics processing units 3 to produce the graphics output required by application 2.

[0170] Then, the driver 4 sends the relevant graphics processing tasks (e.g., commands and data for the relevant graphics processing tasks) to the set of graphics processing units 3 for one or both of the graphics processing units 10, 11 to process in order to generate the desired data processing output.

[0171] Data processing outputs can typically be output frames designed for display on a display device such as a screen or printer, but can also include, for example, intermediate rendering data (also known as "render-to-texture" output) intended for later rendering traversal. Furthermore, as discussed above, data processing outputs do not necessarily involve a display or image. For example, data processing outputs could be vehicle control data for ADAS (Advanced Driver Assistance Systems) or computational data for image recognition or neural network applications.

[0172] In this embodiment, the system is configurable, allowing each GPU 10, 11 to operate in independent mode or to link with another GPU to work collaboratively on a given task. The GPU linking mechanism is implemented in hardware and is transparent to the host processor 1 (to the software), such that the linked GPUs appear as a single (larger) GPU to the host software (e.g., driver 4).

[0173] In standalone mode, the GPUs operate independently, for example, under the direct control of host processor 1. In linked operation, one GPU operates in master mode, and the other GPU operates in slave mode. In master mode, the GPU controls the other GPU operating in slave mode and provides a software interface (host processor interface) for the linked set of GPUs. In slave mode, the GPUs operate under the control of the master GPU. The arrangement and operation of the GPUs are described in the implementation scheme as in US 2017 / 0236244.

[0174] This allows the collection of graphics processing units 3 to be used in different situations, either as two separate GPUs effectively performing different functions, or in conjunction with a single GPU linked to perform a higher-performance function. For example, one GPU can operate as a first partition and generate frames for display on a first display, for example, under the control of a first application, while the other GPU operates as a second independent partition, which generates different frames for display on different displays, for example, under the control of a second, different application. Alternatively, the two GPUs can operate in combination as a single partition to generate the same frames for display on a single display, for example, under the control of a single application.

[0175] Figure 2 illustrates this point: Figure 2A The images show both GPUs 10 and 11 operating in standalone mode, and... Figure 2B The link pattern is shown. For example... Figure 2A As shown, in standalone mode, the first GPU 10 acts as the first partition 200, and the second GPU 11 acts as the second partition 201.

[0176] like Figure 2AAs shown, each GPU 10, 11 includes (task) management circuitry in the form of an job manager 40, 41. This job manager provides a software interface to the corresponding partition and thus receives tasks (commands and data) from the driver. It then divides the tasks given by the driver into subtasks and assigns the subtasks for execution to the corresponding sets of tiling units 20, 21 and shader cores 50, 51. Job managers 40, 41 can both receive tasks from the same driver 4, or different drivers may exist for each partition. In the case of different drivers, the different drivers can execute on the same host processor 1 (or virtual machine), or they can execute on different host processors (or virtual machines).

[0177] In this configuration, each tiling unit 20, 21 operates in combination with a corresponding set 50, 51 of shader cores of the respective GPU 10, 11. In this embodiment, this involves the tiling unit assigning vertex processing tasks to the associated set of shader cores to generate processed vertex data used by the tiling unit to prepare a primitive list, the tiling unit providing the prepared primitive list to the set of shader cores, and the shader cores using the prepared primitive list when performing fragment processing operations.

[0178] Figure 2B The illustration shows a configuration where two GPUs 10 and 11 are combined as a single partition 202. In this embodiment, the first GPU 10 can operate only in standalone or master operation mode, while the second GPU 11 can operate only in standalone or slave operation mode. Therefore, in Figure 2B In this configuration, the first GPU 10 acts as the primary graphics processing unit, while the second GPU 11 acts as the secondary graphics processing unit.

[0179] In this configuration, the job manager 40 of the first main graphics processing unit 10 provides a software interface to the two GPUs 10, 11, and thus receives tasks from the drivers and assigns subtasks to the two sets 50, 51 of the shader cores. The job manager 41 of the second slave GPU 11 is correspondingly disabled. Similarly, in this operating mode, the tiling unit 20 of the first main GPU 10 will operate in combination with the two sets 50, 51 of the shader cores, while the tiling unit 21 of the second slave GPU 11 is disabled.

[0180] Therefore, the tiling unit 20 of the first GPU 10 will operate in standalone mode in combination with a single set 50 of shader cores, or in master mode in combination with two sets 50, 51 of shader cores. However, the tiling unit 21 of the second GPU 11 will operate in standalone mode in combination with a single set 51 of shader cores, or will be disabled in slave mode.

[0181] Therefore, the tiling unit 20 of the first GPU 10 will need to have sufficient processing throughput (capacity) to prepare the primitive list at a sufficiently fast rate for operation in combination with the two sets 50, 51 of the shader cores, while the tiling unit 21 of the second GPU 11 will only need to have sufficient processing throughput (capacity) to prepare the primitive list at a sufficiently fast rate for operation in combination with one set 51 of the sets of shader cores.

[0182] Therefore, the tiling unit 21 of the second GPU 11 has a smaller (maximum) processing throughput (capacity) than the tiling unit 20 of the first GPU 10. For example... Figure 2A As shown, this means that the tiled units 21 of the second GPU 11 can occupy a smaller silicon area than the tiled units 20 of the first GPU 10. Therefore, hardware / silicon area costs can be reduced.

[0183] Figure 3 An embodiment has been shown, which will now be discussed in more detail. In this embodiment, the set of graphics processing units 3 comprises eight connected tile-based graphics processing units 10-17. It should be understood here that... Figure 3 This is merely an illustration, and the system may include components not shown in [the diagram]. Figure 3 Other units and components shown in the diagram.

[0184] In tile-based rendering, instead of efficiently processing the entire render output (e.g., a frame) all at once as in immediate mode rendering, the render output (e.g., a frame to be displayed) is divided into multiple smaller sub-regions (often called "tiles"). Each tile (sub-region) is rendered separately (e.g., processed one after another), and the rendered tiles (sub-regions) are then reassembled to provide the complete render output, such as a frame for display. In this arrangement, the render output is typically divided into sub-regions (tiles) of regular size and shape (which are typically, for example, squares or rectangles), but this is not required.

[0185] The advantage of this type of tile-based rendering is that graphics processing commands (primitives) that are not applicable to a given tile do not need to be processed for that tile and can therefore be ignored when processing that tile. This allows for a reduction in the total amount of graphics processing required for a given render output. Furthermore, external memory bandwidth can be significantly reduced because, for example, temporal and spatial locality is significantly increased.

[0186] In tile-based rendering systems, it is therefore generally desirable to be able to identify and know the geometry (primitives) that are actually applied to a given rendered tile, in order to, for example, avoid unnecessarily processing geometry (primitives) that are not actually applied to that tile.

[0187] To facilitate this implementation, in this embodiment, such as Figure 3 As shown, the graphics processing unit includes corresponding tiling units 20, 22-27, each operable to prepare a list of geometry (e.g., primitives) to be processed for different regions of the rendered output. These “primitive lists” (which may also be referred to as “tile lists” or “polygon lists”) identify (e.g., by reference primitive indicators) the geometry (e.g., primitives) to be processed for the region under consideration. The region of the rendered output for which a primitive list can be prepared may correspond to, for example, a single rendered tile or a set of multiple rendered tiles.

[0188] The primitive list preparation process uses processed vertex data generated by processing the vertex data of the primitives. This vertex processing may include transforming the attributes of each vertex into the form required for the primitive list and subsequent graphics processing operations. This may include, for example, transforming vertex position attributes from the world or user space where they were originally defined to the screen space where the output of the graphics processing system will be displayed.

[0189] Once a list of primitives has been prepared for the render output area, each render tile can be processed by manipulating the geometry (e.g., rasterized primitives) listed for the area covering the render tile, for example, to generate a graphic fragment for processing. The graphic fragment thus generated can then be subjected to appropriate fragment processing operations.

[0190] This fragment processing can include any suitable and desired fragment shading (rendering) process, such as performing fragment shader procedures on the fragment, applying textures to the fragment, applying fog or other operations to the fragment, to generate appropriate fragment data.

[0191] To facilitate vertex and fragment processing, in this implementation, such as Figure 3 As shown, each graphics processing unit 10-17 includes a corresponding set of execution units, which in this embodiment takes the form of a set of shader cores (SCs) 50-57. In this embodiment, each graphics processing unit includes a set of three shader cores. However, other numbers of shader cores are also possible.

[0192] Each shader core is an execution unit that performs graphics processing operations by executing instructions from the vertex or fragment shader program on the graphics "work" items in the rendered output, where these items can be vertices or fragments. This typically enables high parallelism, where typical rendered output (e.g., frames) is characterized by a fairly large number of vertices or fragments, each of which can be processed independently.

[0193] If necessary, various further processing can be performed on the tinted fragments, such as depth testing, blending, dithering, etc.

[0194] Finally, the output fragment data (values) is written to the local L2 cache (L2C). Then, under the control of the memory management unit (MMU), the output data can be output from the L2 cache (L2C) to the frame buffer in external memory for display via memory interfaces 70-77.

[0195] Once a tile of the rendered output has been processed and its data exported to external memory, the next tile is processed, and so on, until enough tiles have been processed to generate the entire rendered output (e.g., a frame (image) to be displayed). The process is then repeated for the next rendered output (e.g., a frame), and so on.

[0196] like Figure 3 As shown, in this embodiment, eight graphics processing units 10-17 are connected together in a "daisy chain" manner. Each graphics processing unit 10-17 includes a corresponding interconnect 30-37, which is connected to the interconnect of the adjacent graphics processing unit in the daisy chain sequence.

[0197] Each graphics processing unit 10-17 can operate in one or more of the following modes: standby mode, master mode, and slave mode. To facilitate this, such as... Figure 3 As shown, the partition manager (control circuitry) 300 is connected to each GPU 10-17 via corresponding configuration connectors 60-67. The partition manager 300 uses the configuration connectors 60-67 to configure the GPU 10-17 to operate in the desired operating mode.

[0198] The partition manager 300 includes a set of control registers (not shown) that can be used to configure the operation of the partition manager 300. The general arrangement is in an embodiment described in US 2019 / 0056955.

[0199] The operating mode (standalone, master, or slave) of the GPU is set (enabled and disabled) by appropriately configuring the interconnects 30-37 of GPU 10-17. For example, when the GPU operates in standalone mode, its interconnects are configured to prevent communication with other graphics processing units. Accordingly, when the GPU acts as a master or slave device, its interconnects are configured to allow communication with one or two connected GPUs, as appropriate.

[0200] Furthermore, when the GPU operates in master or standalone mode, the GPU's job manager operates to allocate tasks appropriately, and the GPU's tiling units operate to prepare primitive lists as needed. However, when the GPU operates in slave mode, its job manager and tiling units are disabled.

[0201] like Figure 3As shown, in this embodiment, the system includes three “large” tiling units 20, 24, and 25 and four “small” tiling units 22, 23, 26, and 27. Each “large” tiling unit has sufficient processing throughput (capacity) to prepare the primitive list for operation in combination with all 24 shader cores. That is, the time expected to be spent by the “large” tiling units preparing the primitive list for a typical rendering output (e.g., a frame for display) will be approximately equal to the time expected to be spent by the set of 24 execution units performing vertex (or fragment) processing operations for that rendering output.

[0202] However, each "small" tiling unit has sufficient processing throughput (capacity) to prepare the primitive list for operation in combination with only 6 shader cores. That is, the time expected to take for a "small" tiling unit to prepare the primitive list for a typical rendering output (e.g., a frame for display) will be roughly equal to the time expected to take for a set of 6 execution units to perform vertex (or fragment) processing operations for that rendering output. Figure 3 As shown, the silicon area occupied by a "small" tile is correspondingly smaller than that occupied by a "large" tile.

[0203] Other tiled cell throughput (processing capacity) is also possible.

[0204] As will now be explained in more detail, the system is configured to minimize the total number of “large” tiled units while still allowing for a high degree of flexibility.

[0205] Figure 4 The partition manager 300 is shown in all possible modes 401-415 that the data processing system of this embodiment can be configured to operate accordingly. Other arrangements are possible.

[0206] In this implementation, communication between GPUs 10-17 allows a GPU to act solely as the master GPU to control one or more adjacent GPUs following it in the daisy-chain sequence (and allows a GPU to act solely as a slave GPU that will be controlled by the GPU preceding it in the daisy-chain sequence). (Other arrangements are, of course, possible.)

[0207] This means that, as Figure 4 As shown in mode 401, where all GPUs 10-17 act as a single partition in combination, the first GPU 10 will be configured by partition manager 300 as the master GPU, while all other subsequent GPUs 11-17 will be configured by partition manager 300 as slave GPUs. In this mode, the tiling units 20 of the first GPU 10 will be used to prepare the primitive list for use by the set 50-57 of all eight shader cores (i.e., for all 24 shader cores). Therefore, as Figure 3As can be seen, tile unit 20 is a "large" tile unit, which makes it compatible with the processing power (processing capacity) of all 24 shader cores in the combination.

[0208] However, the last GPU, 17, cannot operate as the primary GPU because there is no GPU following it in the daisy-chain sequence. Therefore, and as... Figure 3 As can be seen, tile unit 27 is a "small" tile unit because it only needs to be able to match the throughput (processing capacity) of the three shader cores 57 of GPU 17, which will prepare the primitive list when GPU 17 is operating in stand-alone mode.

[0209] Similarly, since the penultimate GPU 16 in the sequence has only one other GPU 17 following it in the daisy-chain sequence, it will only be able to act as the master GPU to control at most one other GPU 17. This means that the tiling unit 26 will only need to prepare the primitive list for combinations of up to six shader cores. Therefore, and as Figure 3 As can be seen, tile unit 26 is also a "small" tile unit.

[0210] like Figure 4 As shown in mode 408, with GPUs 10-17 evenly divided into two partitions, the first four GPUs 10-13 act as the first partition, while the other four GPUs 14-17 act as the second partition. In this "4-4" mode 408, GPU 10 acts as the master from GPUs 11-13, and GPU 14 acts as the master from GPUs 15-17. In this mode, the tiling unit 20 of GPU 10 will be used to prepare the primitive list for use by the four shader core sets 50-53 (i.e., 12 shader cores), and the tiling unit 24 of GPU 14 will be used to prepare the primitive list for use by the other four shader core sets 54-57 (i.e., 12 shader cores). As mentioned above, since the tiling unit 20 is a "large" tiling unit, it will be able to match the throughput (processing capacity) of the combined 12 shader cores. Furthermore, as... Figure 3 As can be seen, tile unit 24 is also a "large" tile unit, which makes it compatible with the throughput (processing capacity) of the other 12 shader cores.

[0211] Figure 4Mode 405 shows the first five GPUs 10-14 acting as the first partition, and the other three GPUs 15-17 acting as the second partition. In this "5-3" mode, GPU 10 acts as the master controlling GPUs 11-14, and GPU 15 acts as the master controlling GPUs 16-17. In this mode, the tiling unit 20 of GPU 10 will be used to prepare the primitive list for use by the five shader core sets 50-54 (i.e., 15 shader cores), while the tiling unit 25 of GPU 15 will be used to prepare the primitive list for use by the three shader core sets 55-57 (i.e., 9 shader cores). Since the tiling unit 20 is a "large" tiling unit, it will be able to match the throughput (processing capacity) of the combined 15 shader cores. Furthermore, as... Figure 3 As can be seen, tile unit 25 is also a "large" tile unit, which makes it compatible with the throughput (processing capacity) of the other 9 shader cores.

[0212] It should be understood here that while, for example, the first three GPUs 10-12 can act as the first partition in combination, and the other five GPUs 13-17 can act as the second partition in combination, such a "3-5" mode would involve GPU 13 acting as the master to control the GPUs 14-17. This means that the tiling unit 23 will need to be able to prepare a primitive list for use by the five shader core sets 53-57 (i.e., 15 shader cores), and therefore will need to be a "large" tiling unit. Therefore, if both the "5-3" and "3-5" modes are possible, an additional "large" tiling unit needs to be provided.

[0213] Therefore, in this embodiment, where multiple different modes exist so that GPUs 10-17 can be partitioned into partitions of a specific size, the partition manager 300 only allows and supports a single mode among these possible modes. For example, in this embodiment, the partition manager 300 allows a "5-3" mode 405 in which the first five GPUs 10-14 operate in combination and the other three GPUs 15-17 operate in combination, but does not allow a "3-5" mode in which the first three GPUs 10-12 operate in combination and the other five GPUs 13-17 operate in combination. It should be understood that limiting the possible modes in this way can reduce the number of "large" tiling units required.

[0214] Similarly, such as Figure 4 As shown, other allowed modes where the GPU is divided into two partitions are “7-1” mode 402 and “6-2” mode 403, but partition manager 300 does not allow modes such as “1-7” and “2-6”.

[0215] like Figure 4As shown, in this implementation, the allowed modes for dividing the GPU into three partitions are "6-1-1" mode 404, "5-2-1" mode 406, "4-3-1" mode 409, "4-2-2" mode 410, and "3-2-3" mode 412. The allowed modes for dividing GPUs 10-17 into four partitions are "5-1-1-1" mode 407, "4-2-1-1" mode 411, "3-1-1-3" mode 413, "3-2-2-1" mode 414, and "2-2-2-2" mode 415. While the system can be configured to support more partitions, in this implementation, the system is limited to supporting a maximum of four partitions at any given time.

[0216] Other arrangements of the allowed pattern are also possible.

[0217] It should be understood that Figure 4 All the patterns shown can be adapted using only three “large” tile units 20, 24, and 25, while all other tile units 22, 23, 26, and 27 are “small” tile units.

[0218] Furthermore, in this embodiment, the second GPU 11 only needs to operate in slave mode, and therefore does not require tiling units at all. Thus, as Figure 3 As shown, in this implementation, tiling units are omitted in GPU 11. Figure 3 As shown, the job manager and memory management unit (MMU) were also omitted from GPU 11 for the same reason.

[0219] Other distributions, such as tiled units, GPUs, and possible operating modes, are of course also possible.

[0220] Although in the above implementation, each tile unit 20, 22-27 is set up as a component of a specific GPU 10, 12-17 (i.e., on the same chip as the specific GPU), and therefore a primitive list can be prepared only for the GPU's partition of its portion, Figure 5 An alternative implementation is shown in which tiling units with different (maximum) throughput (processing capacity) 520-523 are provided in the external pool 510 such that each tiling unit 520-523 can be assigned to any desired partition.

[0221] like Figure 5As shown, in this configuration, the system includes a first configurable interconnect 531 operable to route graphics processing tasks to tiling units 520-523 in pool 510, and a second configurable interconnect 532 operable to route communication between tiling units 520-523 and GPUs 10-17. The system also includes control circuitry 530 operable to select tiling units from pool 510 for a specific partition of one or more GPUs based on the required processing throughput (capacity) for that partition, and to appropriately configure interconnects 531, 532 to route graphics processing tasks for that partition to the selected tiling units and to route communication between the selected tiling units and one or more GPUs in that partition.

[0222] For example, as mentioned above Figure 3 and Figure 4 Compared to the previous arrangement, this arrangement allows for a further reduction in the number of "large" tile units and the total number of tile units. For example, as Figure 5 As shown, in this case, pool 510 may consist of only two “large” tile units 520, 521 and two “small” tile units 522, 533. In this case, the total number of tile units in pool 510 may be the same as the maximum number of partitions supported at any given time (i.e., four in this embodiment).

[0223] Alternatively, fewer tiled units can be provided in pool 510 than the maximum number of partitions supported at any given time. In this case, tiled units can be dynamically allocated and ownership changed as needed.

[0224] Although in the above implementation, the tiling unit is limited to having one of two possible (maximum) processing throughput (capacity) (i.e., corresponding to a "large" tiling unit and a "small" tiling unit), in other implementations, a tiling unit may have more than two possible processing capacities, such as three, four, or more different possible throughputs (processing capacities). Each such tiling unit may have a minimum possible processing throughput (capacity) sufficient to prepare a primitive list for the maximum possible number of shader cores for which the tiling unit can prepare a primitive list.

[0225] Although the processing throughput (capacity) of the tiling unit is modified and minimized in the above implementation, the processing throughput (capacity) of other functional units can also, or alternatively, be modified and minimized in substantially the same manner. For example, the throughput (processing capacity) of the (task) management circuitry (job manager) and / or the memory management unit (MMU) can be modified and minimized in substantially the same manner.

[0226] Although in the above embodiments the functional unit operates in combination with the graphics processing unit, in other embodiments, the functional unit may operate in combination with other forms of processing units, such as a central processing unit (CPU), a video processing unit, a neural network processing unit, etc. For example, in one embodiment, multiple discrete cosine transform (DCT) units with different (maximum supported) throughputs (processing capacities) are provided in combination with multiple composable video processing units.

[0227] In one embodiment, multiple direct memory access (DMA) controllers with different (maximum supported) throughput (processing capacity) are provided in combination with multiple composable processing units (e.g., CPUs or GPUs). In one embodiment, multiple memory data compression / decompression units (codecs) are provided in combination with multiple composable processing units (e.g., CPUs or GPUs).

[0228] In one implementation, multiple fixed-function task management circuits with different (maximum supported) throughput (processing capacity) are provided in combination with multiple programmable processing units. Each task management circuit is operable to divide the entire processing task into subtasks and assign the subtasks to the processing units for execution in parallel (independently and simultaneously) by the processing units.

[0229] As can be understood from the foregoing, at least in its embodiments, the techniques described herein provide an arrangement in which the hardware / silicon area cost associated with functional units (e.g., tiled units) in a data processing system comprising multiple connected graphics processing units and multiple functional units is reduced. In embodiments of the techniques described herein, this is achieved at least by providing at least one functional unit having a (maximum supported) processing throughput (capacity) less than the (maximum supported) processing throughput (capacity) required by all the combined multiple graphics processing units.

[0230] The specific embodiments described above are presented for illustrative and descriptive purposes only. They are not intended to be exhaustive or to limit the technology described herein to the precise forms disclosed. Many modifications and variations are possible in accordance with the teachings above. The described embodiments were chosen to best explain the principles of the technology described herein and its practical application, thereby enabling others skilled in the art to best utilize the technology described herein in various embodiments and with various modifications suitable for the particular intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A data processing system, the data processing system comprising: Multiple processing units, wherein one or more of the multiple processing units are operable in combination with at least one other processing unit, such that a corresponding set of the multiple processing units can generate a corresponding data processing output. and Multiple functional units are configured to perform the same type of processing operations, and each functional unit can operate in combination with a set of one or more processing units when generating data processing output; The processing capacity of at least one of the plurality of functional units for performing the processing operation is greater than the processing capacity of at least one other functional unit for performing the processing operation.

2. The data processing system of claim 1, further comprising a control circuit configured to divide the plurality of processing units into one or more sets of one or more processing units, wherein each set of one or more processing units is operable to generate a data processing output independently of any other set of one or more processing units in the one or more sets of one or more processing units, and such that each set of one or more processing units operates in combination with a functional unit among the plurality of functional units having a processing capacity for performing the processing operation, the processing capacity being sufficient to match the processing capacity of the set of one or more processing units for generating the data processing output.

3. The data processing system according to claim 1 or 2, wherein the processing capacity of the at least one functional unit for performing the processing operation is sufficient to match the processing capacity of the processing units operating in combination to generate the maximum possible number of data processing outputs, and the processing capacity of the at least one other functional unit for performing the processing operation is insufficient to match the processing capacity of the processing units operating in combination to generate the maximum possible number of data processing outputs.

4. The data processing system of claim 1 or 2, wherein each processing unit comprises a corresponding set of one or more execution units, each of the one or more execution units being operable to use the output of the processing operation as input and / or generate the input of the processing operation, and wherein the processing capacity of the at least one functional unit for performing the processing operation is sufficient to match the processing capacity of the maximum possible number of execution units that operate in combination to generate the data processing output, and the processing capacity of the at least one other functional unit for performing the processing operation is sufficient to match the processing capacity of some, but not all, of the maximum possible number of execution units that operate in combination to generate the data processing output.

5. The data processing system according to claim 1 or 2, wherein the processing capacity of each of the plurality of functional units for performing the processing operation is a first processing capacity or a second lower processing capacity.

6. The data processing system according to claim 1 or 2, wherein each of the plurality of functional units is included in a corresponding processing unit among the plurality of processing units.

7. The data processing system of claim 6, wherein each processing unit, which is operable in combination with at least one other processing unit among the plurality of processing units under the control of the respective processing unit, includes a functional unit, the processing capacity of the functional unit for performing the processing operation being based on the combined processing capacity for generating data processing outputs of the respective processing unit and each of the processing units among the plurality of processing units with which the respective processing unit can operate in combination.

8. The data processing system according to claim 1 or 2, the system comprising a control circuit operable to select a functional unit among the plurality of functional units to operate in combination with the set of one or more processing units when generating a data processing output based on a processing capacity for generating the data processing output of the set of one or more processing units.

9. The data processing system of claim 2, wherein the control circuit is configured to divide the plurality of processing units according to an operating mode in a selected set of a plurality of different operating modes.

10. The data processing system of claim 9, wherein the processing capacity of each of the plurality of functional units is selected based on a selected set of a plurality of different operating modes.

11. The data processing system according to claim 1 or 2, wherein each of the plurality of processing units is configured to perform graphics processing operations, and the plurality of functional units are all tiling units, or all graphics processing unit task management circuits, or all of them are memory management units (MMUs).

12. The data processing system according to claim 1 or 2, wherein different processing units among the plurality of processing units include different numbers of execution units.

13. A method of operating the data processing system as described in claim 1, The method includes: Configure a set of one or more processing units from the plurality of processing units to generate data processing output; The functional unit among the plurality of functional units having a processing capacity for performing the processing operation is configured to operate in combination with the set of the one or more processing units when generating data processing output, the processing capacity being sufficient to match the processing capacity of the set of the one or more processing units for generating the data processing output; as well as When the data processing output is generated, the functional unit performs the processing operation in combination with the set of one or more processing units.

14. The method of claim 13, wherein the processing capacity of the at least one functional unit for performing the processing operation is sufficient to match the processing capacity of the processing units operating in combination to generate a maximum possible number of data processing outputs, and the processing capacity of the at least one other functional unit for performing the processing operation is insufficient to match the processing capacity of the processing units operating in combination to generate a maximum possible number of data processing outputs. When the maximum possible set of the processing units is generating data processing output: One of the at least one functional units is configured to operate in combination with the set of the maximum possible number of the processing units when generating the data processing output; and When the data processing output is generated, the functional unit performs the processing operation in combination with the set of the maximum possible number of the processing units.

15. The method of claim 13 or 14, wherein each processing unit comprises a corresponding set of one or more execution units, each of the one or more execution units being operable to use the output of the processing operation as input and / or generate the input of the processing operation, and wherein the processing capacity of the at least one functional unit for performing the processing operation is sufficient to match the processing capacity of the maximum possible number of execution units that operate in combination to generate the data processing output, and the processing capacity of the at least one other functional unit for performing the processing operation is sufficient to match the processing capacity of a selected number, but not all, of the execution units that operate in combination to generate the data processing output; When a collection of one or more processing units, including more than the selected number of execution units, is generating data processing output: One of the at least one functional units is configured to operate in combination with a set of one or more processing units, including more than a selected number of execution units, when generating the data processing output; as well as When the data processing output is generated, the functional unit performs the processing operation in combination with a set of one or more processing units that include more than the selected number of execution units; as well as When a set of one or more processing units, comprising fewer than or equal to the selected number of execution units, is generating data processing output: One of the at least one other functional units is configured to operate in combination with a set of one or more processing units comprising a number of execution units less than or equal to the selected number when generating the data processing output; as well as When generating the data processing output, the functional unit performs the processing operation in combination with a set of one or more processing units comprising fewer than or equal to the selected number of execution units.

16. The method of claim 13 or 14, wherein the processing capacity of each of the plurality of functional units for performing the processing operation is a first processing capacity or a second lower processing capacity.

17. The method according to claim 13 or 14, wherein each of the plurality of functional units is included in a corresponding processing unit among the plurality of processing units.

18. The method according to claim 13 or 14, wherein the method comprises: Select a functional unit from the plurality of functional units to operate in combination with the set of one or more processing units when generating data processing output based on the processing capacity for generating data processing output of the set of one or more processing units; When generating data processing output, the selected functional unit operates in combination with the set of one or more processing units.

19. The method according to claim 13 or 14, wherein each of the plurality of processing units is configured to perform graphics processing operations, and the functional units of the plurality of functional units are all tiling units, or all graphics processing unit task management circuits, or all all memory management units (MMUs).

20. A method for providing a data processing system, the method comprising: A plurality of processing units are provided, wherein one or more of the processing units are capable of operating in combination with at least one other processing unit among the plurality of processing units; A control circuit is provided, the control circuit being configured to divide the plurality of processing units into one or more sets of one or more processing units according to an operating mode in a selected set of a plurality of different operating modes, such that each set of one or more processing units is operable to generate a data processing output. as well as Provide multiple functional units configured to perform the same type of processing operation, each functional unit being able to operate in combination with a set of one or more processing units when generating data processing output, and wherein the processing capacity of at least one of the multiple functional units for performing the processing operation is greater than the processing capacity of at least one other of the multiple functional units for performing the processing operation. The provision of the plurality of functional units includes selecting the processing capacity of the functional unit for performing the processing operation based on a selection set of a plurality of different operating modes.

21. The method of claim 20, wherein each of the plurality of processing units is configured to perform graphics processing operations, and the functional units of the plurality of functional units are all tiling units, or all graphics processing unit task management circuits, or all all memory management units (MMUs).

22. A computer program product comprising computer software code, which, when run on a data processor, performs the method according to any one of claims 13 to 21.

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