A method of protecting semiconductor wafers during material analysis

Abstract

The application provides a method for protecting a semiconductor wafer during material analysis, S1: placing the semiconductor wafer on an operation platform; S2: removing layers of the semiconductor wafer to a layer required for analysis by layer removal; S3: pouring glue on the layer of the semiconductor wafer exposed after layer removal and heating; S4: stopping heating when the heating temperature reaches a specified temperature and solidifying the glue into a gel, so that the gel completely adheres to the layer of the semiconductor wafer exposed after layer removal. The gel is prepared on the surface of the semiconductor wafer after layer removal, the gel is heated to a specified temperature, the gel in a molten state completely adheres to the surface of the semiconductor wafer after layer removal, external water vapor or oxygen cannot enter the surface of the wafer to produce metal oxides with copper, and the gel solidifies at room temperature, so that the mechanical strength of the semiconductor wafer after layer removal is greatly improved, the semiconductor wafer is convenient to take and is not easy to damage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor test piece protection, and more specifically to a method for protecting semiconductor test pieces during material analysis. Background Technology

[0002] The semiconductor test wafer has a layered structure, with a silicon substrate at the bottom, followed by transistor layers and metal interconnect layers. To analyze the characteristics of the metals and dielectric materials within each metal interconnect layer, a manual polishing method is typically used. Starting from the front of the semiconductor test wafer, layers are removed one by one towards the back. After removing layers to a specific metal interconnect layer, material analysis begins. After analysis, the process continues to the next metal interconnect layer for analysis, repeating the above process until the material characteristics of each metal interconnect layer are obtained.

[0003] If the current technology is used, when delamination reaches a certain metal trace layer, due to different equipment usage conditions, it is not possible to put it into the material analysis machine for continuous analysis in time. It is necessary to wait a day or even until the weekend before it can be put into the machine for analysis. The current practice is to place the test piece on a glass slide and put it in a dehumidifying cabinet. However, the metal trace layer material of semiconductor test pieces is copper, which has high chemical reactivity. If the delamination stops at a certain metal trace layer and is not put into the machine for analysis as soon as possible, even if it is placed in a dehumidifying cabinet, the exposed metal trace layer is easy to react with the outside moisture or oxygen, producing metal surface. This will cause problems in analysis and subsequent delamination. Moreover, the semiconductor test piece after delamination is quite brittle. The air conditioning in the working environment, the engineer's sneezing, or vibration may blow the test piece away, drop or damage it. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method for protecting semiconductor test pieces during material analysis.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a method for protecting semiconductor test wafers during material analysis, the specific steps of which are as follows: S1: Place the semiconductor test piece on the operating platform; S2: Using a de-layering method, the semiconductor test piece is de-layered down to the specific layer that needs to be analyzed; S3: Apply glue to the exposed layers of the semiconductor test wafer after delamination and heat it; S4: When the heating temperature reaches the specified temperature, stop heating and allow the adhesive to cure into a colloid, so that the colloid is completely attached to the exposed layers of the semiconductor test piece after delamination.

[0006] Preferably, in step S1, the semiconductor test wafer is provided with an outer insulating layer, a metal trace layer, a transistor layer and a silicon substrate from top to bottom; the transistor layer is fixedly mounted on the silicon substrate; the metal trace layer is wound around the transistor layer; and the outer insulating layer is wrapped around the metal trace layer.

[0007] Preferably, in step S2, removing the semiconductor test wafer to the specific layer to be analyzed means removing it to the metal trace layer until the metal surface inside the metal trace layer is exposed.

[0008] Preferably, in step S3, the adhesive is a 1-minute instant adhesive formed by mixing epoxy resin and a hardener.

[0009] Preferably, the ratio of epoxy resin to hardener in the adhesive is 1.16:1.12; the application temperature of the adhesive is suitable for use between 4°C and 35°C.

[0010] Preferably, in step S4, if the semiconductor sample after colloid curing still needs to be analyzed for material properties or further delamination is required, the following steps may also be performed: S4-1: Place the semiconductor test piece after the colloid has been cured in an organic solvent, so that the colloid dissolves in the organic solution; S4-2: After the colloid is completely removed from the semiconductor test piece, it can be dried with 99.99% pure dry nitrogen gas to expose the surface of the original metal trace layer. S4-3: Finally, perform material property analysis or delamination on the sol-gel semiconductor test piece.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention prepares a colloid on the surface of the delaminated semiconductor test piece. The colloid is solid at room temperature, and becomes a viscous molten state when heated to a specified temperature. By utilizing the property that the molten colloid can completely adhere to the surface of the delaminated semiconductor test piece, it can prevent external moisture or oxygen from entering the test piece surface and forming metal oxides with copper. Furthermore, since the colloid will solidify at room temperature, it can greatly improve the mechanical strength of the delaminated semiconductor test piece, making it easy to handle and less prone to damage. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view of the semiconductor test piece; Figure 2 This is a cross-sectional view of the semiconductor test wafer in the delamination direction; Figure 3 This is a cross-sectional view of the semiconductor test wafer after delamination. Figure 4 A cross-sectional view of the adhesive casting process for semiconductor test wafers; Figure 5A cross-sectional view of the cured colloid of a semiconductor sample. Figure 6 Cross-sectional view of the semiconductor test piece with adhesive replacement; Figure 7 A cross-sectional view for semiconductor test wafer applications; In the diagram: 1-Outer insulating layer; 2-Metal trace layer; 3-Transistor layer; 4-Silicon substrate. Implementation

[0013] To provide a further understanding of the purpose, structure, features, and functions of the present invention, detailed descriptions are provided below with reference to specific embodiments.

[0014] Please refer to the reference. Figure 1 This invention provides a method for protecting semiconductor test pieces during material analysis, the specific steps of which are as follows: S1: Place the semiconductor test piece on the operating platform; S2: Using a de-layering method, the semiconductor test piece is de-layered down to the specific layer that needs to be analyzed; S3: Apply glue to the exposed layers of the semiconductor test wafer after delamination and heat it; S4: When the heating temperature reaches the specified temperature, stop heating and allow the adhesive to cure into a colloid, so that the colloid is completely attached to the exposed layers of the semiconductor test piece after delamination.

[0015] Furthermore, the operating platform in step S1 also has a heating function.

[0016] Preferably, in step S1, the semiconductor test wafer is provided with an outer insulating layer 1, a metal trace layer 2, a transistor layer 3, and a silicon substrate 4 from top to bottom; the transistor layer 3 is fixedly mounted on the silicon substrate 4; the metal trace layer 2 is wound around the transistor layer 3; and the outer insulating layer 1 is wrapped around the metal trace layer 2.

[0017] Preferably, in step S2, removing the semiconductor test wafer to the specific layer to be analyzed means removing it to the metal trace layer 2 until the metal surface inside the metal trace layer 2 is exposed.

[0018] Preferably, in step S3, the adhesive is a 1-minute instant adhesive formed by mixing epoxy resin and a hardener.

[0019] Preferably, the ratio of epoxy resin to hardener in the adhesive is 1.16:1.12; the application temperature of the adhesive is suitable for use between 4°C and 35°C.

[0020] An instant adhesive composed of epoxy resin and a hardener, when mixed in proportion, the resin and hardener react to produce a hard, high-strength bond, which begins to solidify within 1 minute and reaches treatment strength within 5 to 10 minutes.

[0021] The mixing nozzle delivers a homogeneous mixture of resin and hardener with each application. It can be used as an adhesive for various materials or as a versatile filler for gap bonding, surface repair, and lamination. Epoxy resin does not shrink during mixing and is resistant to water and most common solvents. It can be colored and matched with clay pigments, cement, or sand, and can also be sanded and drilled.

[0022] Preferably, in step S4, if the semiconductor sample after colloid curing still needs to be analyzed for material properties or further delamination is required, the following steps may also be performed: S4-1: Place the semiconductor test piece after the colloid has been cured in an organic solvent, so that the colloid dissolves in the organic solution; S4-2: After the colloid is completely removed from the semiconductor test piece, it can be dried with 99.99% pure dry nitrogen gas to expose the surface of the original metal trace layer. S4-3: Finally, perform material property analysis or delamination on the sol-gel semiconductor test piece.

[0023] Heating the adhesive to cure it increases the physical strength of the wafer; heating the air prevents moisture and oxygen from entering the surface of the wafer and prevents oxygen and moisture from chemically reacting with the metal trace layer.

[0024] Furthermore, in addition to the use of adhesive, a hydrophilic coating can be applied to the metal trace layer 2; the hydrophilic coating is aluminum oxide or a material containing polar (OH); hot melt adhesive, AB glue, organic glue, or UV-curable adhesive can be added on top of the hydrophilic coating for bonding, and finally, a glass, metal plate, or ceramic plate is bonded on top of the hot melt adhesive, AB glue, organic glue, or UV-curable adhesive for protection.

[0025] The method described in this invention can prevent external moisture or oxygen from entering the surface of the test piece and forming a metallic surface with copper. Furthermore, since the colloid will solidify at room temperature, it can greatly improve the mechanical strength of the semiconductor test piece after delamination, making it easy to handle and less prone to damage.

[0026] The present invention has been described in the above-described embodiments; however, these embodiments are merely examples for implementing the present invention. It must be noted that the disclosed embodiments do not limit the scope of the present invention. Conversely, any modifications and refinements made without departing from the spirit and scope of the present invention are within the scope of patent protection of the present invention.

Claims

1. A method for protecting semiconductor test pieces during materials analysis, characterized in that: The specific steps of the method are as follows: S1: Place the semiconductor test piece on the operating platform; S2: Using a de-layering method, the semiconductor test piece is de-layered down to the specific layer that needs to be analyzed; the de-layering of the semiconductor test piece down to the specific layer that needs to be analyzed means de-layering down to the metal trace layer, until the metal surface inside the metal trace layer is exposed; S3: Apply the adhesive to the exposed layers of the semiconductor wafer after delamination and heat it; the adhesive is a 1-minute instant adhesive formed by mixing epoxy resin and a hardener; S4: When the heating temperature reaches the specified temperature, stop heating and allow the adhesive to cure into a colloid, ensuring the colloid completely adheres to the exposed layers of the semiconductor test piece after delamination. If the semiconductor test piece still needs to be analyzed for material properties or further delamination is required after the colloid has cured, perform the following steps: S4-1: Place the semiconductor test piece after the colloid has been cured in an organic solvent, so that the colloid dissolves in the organic solution; S4-2: After the colloid is completely removed from the semiconductor test piece, it can be dried with 99.99% pure dry nitrogen gas to expose the surface of the original metal trace layer. S4-3: Finally, perform material property analysis or delamination on the sol-gel semiconductor test piece.

2. The method for protecting semiconductor test pieces during material analysis as described in claim 1, characterized in that: In step S1, the semiconductor test wafer is provided with an outer insulating layer, a metal trace layer, a transistor layer and a silicon substrate from top to bottom; the transistor layer is fixedly mounted on the silicon substrate; the metal trace layer is wound around the transistor layer; and the outer insulating layer is wrapped around the metal trace layer.

3. The method for protecting semiconductor test pieces during material analysis as described in claim 1, characterized in that: The ratio of epoxy resin to hardener in the adhesive is 1.16:1.12; the adhesive is suitable for use at temperatures between 4°C and 35°C.

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