Data processing system, method of operation thereof and storage means therefor

Abstract

The present application relates to a data processing system. The data processing system can include a storage device configured to transmit, to the outside, prediction information for each power mode indicating a predicted time of performing a background operation for managing the storage device, and to switch to a corresponding power mode by responding to a power mode control signal received in an idle state in which the background operation is performed, and a control device configured to determine a power mode of the storage device and an idle time of the idle state during which the background operation is performed, based on the prediction information, transmit the power mode control signal to the storage device, and suspend execution of a command processing request transmitted to the storage device during the idle time.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority and benefit to Korean Patent Application No. 10-2022-0008520, filed on January 20, 2022, which is incorporated herein by reference in its entirety as part of the disclosure of this patent application. Technical Field

[0003] Various embodiments generally relate to a semiconductor integrated device, and more specifically, to a data processing system, a method of operating thereof, and a storage device thereof. Background Technology

[0004] A data processing system generates a set of outputs in response to receiving a set of inputs and requests from an external device. The data processing system may include a data storage device to store input and output data in a data storage medium in response to requests from the external device.

[0005] Examples of data storage media may include non-volatile memory devices, such as flash memory devices.

[0006] Flash memory devices can manage storage space by performing housekeeping operations such as data migration, garbage collection, and wear leveling.

[0007] Scraping operations ensure the reliability of data storage and provide storage space. However, if a scraping operation is not performed in a timely manner due to another high-priority process or external request, the overall performance of the data processing system may degrade. Summary of the Invention

[0008] A data processing system based on some embodiments of the disclosed technology may include: a storage device configured to transmit prediction information for each power mode to an external source and switch to the corresponding power mode in response to a power mode control signal received in an idle state of the storage device, and to perform background operations in the idle state, the prediction information indicating a prediction time for performing background operations for managing the storage device; and a control device configured to determine the power mode of the storage device and the idle time of the idle state during which background operations are performed based on the prediction information, transmit a power mode control signal to the storage device, and suspend the execution of command processing requests transmitted to the storage device during the idle time.

[0009] Operating a data processing system based on some embodiments of the disclosed technology may include: generating prediction information indicating the predicted time to be spent performing background operations for managing a memory device for each power mode; determining the power mode of the memory device and the idle time for performing the background operations based on the prediction information, so as to transmit a power mode control signal corresponding to the power mode to the memory device; performing the background operations by switching to the power mode corresponding to the power mode control signal when the power mode control signal is received in the idle state; and suspending the execution of command processing requests transmitted to the data processing system during the idle time.

[0010] The storage device based on some embodiments of the disclosed technology may include: a memory device; and a memory controller configured to transmit prediction information for each power mode to the outside and to perform background operations on the memory device in the idle state by switching to the corresponding power mode in response to receiving a power mode control signal from the outside in the idle state, the prediction information indicating the prediction time for performing background operations to be performed for managing the memory device. Attached Figure Description

[0011] Figure 1 Examples of data processing systems based on some embodiments of the disclosed technology are shown.

[0012] Figure 2 Examples of external devices based on some embodiments of the disclosed technology are shown.

[0013] Figure 3 An example of a background operation control unit based on some embodiments of the disclosed technology is shown.

[0014] Figure 4 Examples of memory controllers based on some embodiments of the disclosed technology are shown.

[0015] Figure 5 Examples of memory controllers that communicate with external devices to perform command processing procedures, based on some embodiments of the disclosed technology, are shown.

[0016] Figure 6 Examples of operating methods of a data processing system based on some embodiments of the disclosed technology are shown.

[0017] Figure 7 Examples of data storage systems based on some embodiments of the disclosed technology are shown.

[0018] Figure 8 Examples of data processing systems based on some embodiments of the disclosed technology are shown.

[0019] Figure 9Examples of data processing systems based on some embodiments of the disclosed technology are shown.

[0020] Figure 10 This is an example illustrating a network system including a data storage device based on some embodiments of the disclosed technology.

[0021] Figure 11 This is an example illustrating a non-volatile memory device included in a data storage device based on some embodiments of the disclosed technology. Detailed Implementation

[0022] In the following description, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

[0023] Figure 1 An example of a data processing system 10 based on some embodiments of the disclosed technology is shown.

[0024] Reference Figure 1 The data processing system 10, based on some embodiments of the disclosed technology, may include a storage device 200 that exchanges data with another device. In some embodiments, the term "storage device" may refer to a data storage device used for temporary or permanent storage of data. In some embodiments, "another device" may refer to an external or control device or external device 100, such as a host device to which the storage device 200 is connected. In some embodiments, the external device 100 may include a control device in the data processing system 10.

[0025] External device 100 and storage device 200 can be interconnected via a first interface IF1 and a second interface IF2. In some embodiments, external device 100 may include a control device located in data processing system 10.

[0026] The first interface IF1 may include hardware and / or software components that allow the external device 100 to interact or communicate with the storage device 200. The first interface IF1 may include at least one interface device based on standard interface protocols such as Secure Digital, Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), PCMCIA, Parallel Advanced Technology Attachment (PATA), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial SCSI (SAS), Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), and Universal Flash Memory (UFS).

[0027] The second interface IF2 may include at least one of the following interface devices based on the System Management Bus (SMBus), Internal Integrated Circuit (I2C), and Improved Internal Integrated Circuit (I3C) protocols.

[0028] Storage device 200 may include memory controller 210 and memory device 220.

[0029] The memory controller 210 can control the memory device 220 in response to a request from the external device 100. For example, the memory controller 210 can allow data to be programmed into the memory device 220 in response to a write request from the external device 100. Furthermore, the memory controller 210 can provide data recorded in the memory device 220 to the external device 100 in response to a read request from the external device 100.

[0030] Memory device 220 can record or output recorded data under the control of memory controller 210. Memory device 220 can be configured as a volatile or non-volatile memory device. In embodiments, memory device 220 can be implemented using memory elements selected from a variety of non-volatile memory elements, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetic RAM (STT-MRAM). Memory device 220 may include multiple dies (Die 0 to Die n), multiple chips, or multiple packages. Additionally, memory device 220 may include a single-level cell (SLC) storing one bit of data in a memory cell or a multi-level cell (MLC) storing multiple bits of data in a memory cell.

[0031] Based on some embodiments of the disclosed technology, the memory controller 210 can be configured to transmit predictive information to the external device 100 obtained by predicting the time required for background operations for each power mode. Background operations may include at least one of the management operations for the memory device 220, such as garbage collection, data migration, wear leveling, read refresh, and background trim.

[0032] When the storage device 200 receives a power mode control signal from the external device 100 while the storage device 200 is in an idle state, the memory controller 210 can change the power mode and perform background operations. At this time, the external device 100 can recognize that the storage device 200 is in an idle state.

[0033] In this embodiment, prediction information and power mode control signals can be transmitted / received via the second interface IF2; however, the technology is not limited thereto.

[0034] External device 100, based on some embodiments of the disclosed technology, may include background operation (BGOP) control circuitry 120. BGOP control circuitry 120 may determine the power mode of storage device 200 and an allocable idle time, which is an intentional idle time used for processing background operations when prediction information is transmitted from storage device 200 via the second interface IF2. External device 100 may transmit a power mode control signal to storage device 200 and suspend command processing requests such that storage device 200 does not process commands from external device 100 during the intentional idle time following the transmission of the power mode control signal. In embodiments, the power mode control signal may include intentional idle time information.

[0035] In one embodiment, the external device 100 may determine the power mode by referring to the temperature of the data processing system 10 or the storage device 200. For this purpose, the storage device 200 may transmit predictive information including temperature information.

[0036] The prediction information provided by the storage device 200 may include, for example, the predicted time or required time for background operations to be performed for each power mode, as shown in [Table 1] below.

[0037] [Table 1]

[0038] PL0 30 PL1 50 PL2 100 PL3 200 PL4 500

[0039] When determining the power mode in response to prediction information, external device 100 can determine the intentional idle time based on the time required or the predicted time to perform background operations for each power mode included in the prediction information. Taking Table 1 above as an example, when external device 100 determines the power mode to be PL3, the intentional idle time can be [200ms + α]. The value "α" can be a default value set in external device 100 or a value that can be changed by the user.

[0040] When a power mode control signal is received in an idle state, the storage device 200 can perform background operations by switching to the corresponding power mode. Since the external device 100 suspends command processing requests to the storage device 200 during the intentional idle time following the transmission of the power mode control signal, the storage device 200 can complete background operations without degrading performance and keep the data processing system 10 essentially in optimal condition.

[0041] In the event that the execution of a command is paused after an intentional period of inactivity, the external device 100 can request the execution or processing of the paused command by turning the storage device 200 into an active state.

[0042] Figure 2Examples of external devices 100 based on some embodiments of the disclosed technology are shown.

[0043] Reference Figure 2 External device 100 may include processor 110, BGOP control circuit 120, submission queue (SQ) 130 and completion queue (CQ) 140.

[0044] Processor 110 may include any known CPU and / or FPGA, which is configured to execute instructions and communicate with other components and devices in external device 100.

[0045] The BGOP control circuit 120 can determine the power mode and intended idle time of the storage device 200 based on prediction information transmitted from the storage device 200. A generated power mode control signal can be transmitted to the storage device 200. When the power mode control signal is received during the idle state of the storage device 200, the storage device 200 can perform background operations by switching to the corresponding power mode. The prediction information may include the predicted time of the background operation to be performed for each power mode, and may further include temperature information of the data processing system 10 or the storage device 200. When the prediction information includes temperature information, the BGOP control circuit 120 can determine the power mode by further referencing the temperature information.

[0046] SQ 130 may be a storage space for storing commands generated by external device 100. CQ 140 may be a storage space for recording the processing results of commands stored in SQ 130 when the storage device 200 processes the commands.

[0047] The method by which external device 100 and storage device 200 communicate with each other based on queues including SQ 130 and CQ 140 is called the command queue-based interface method.

[0048] In one embodiment, the BGOP control circuit 120 can pause updating the submission queue doorbell corresponding to the commands stored in SQ130 during intentional idle periods.

[0049] The submission queue doorbell is a storage space used to store the tail pointer of SQ 130 and can be allocated as part of the storage space included in the memory controller 210 of storage device 200. When the tail pointer stored in the submission queue doorbell is updated, the memory controller 210 can recognize that the external device 100 has requested a new command.

[0050] The following will refer to Figure 5 Describe in detail the methods of the command queue base interface.

[0051] Figure 3 Examples of BGOP control circuits based on some embodiments of the disclosed technology are shown.

[0052] Reference Figure 3 The BGOP control circuit 120 may include a monitoring circuit 121, a power setting circuit 123, a time counter 125, and a command holding circuit 127.

[0053] The monitoring circuit 121 can be configured to check whether the storage device 200 is transmitting prediction information and whether the storage device 200 is in an idle state.

[0054] When storage device 200 transitions to an idle state, power setting circuit 123 can determine the power mode and intended idle time of storage device 200 based on prediction information transmitted by storage device 200. In embodiments, the prediction information may include predicted times for background operations to be performed for each power mode, and may further include temperature information of data processing system 10 or storage device 200. By taking temperature information into account when determining the power mode, damage or malfunction due to temperature rise in data processing system 10 can be substantially prevented.

[0055] The power mode control signal generated by the power setting circuit 123 can be transmitted to the storage device 200. When the power mode control signal is received in the idle state, the storage device 200 can perform background operations by switching to the corresponding power mode.

[0056] The time counter 125 can measure the intentional idle time starting from the point in time when the power setting circuit 123 transmits the power mode control signal to the storage device 200.

[0057] When a new command is stored in SQ 130 before time counter 125 expires, command hold circuit 127 can be configured to pause updating the corresponding submission queue doorbell register. When there are unprocessed commands in SQ 130 after time counter 125 expires, command hold circuit 127 can update the corresponding doorbell register.

[0058] Figure 4 Examples of memory controllers based on some embodiments of the disclosed technology are shown.

[0059] Reference Figure 4 The memory controller 210, based on some embodiments of the disclosed technology, may include a processor 211, a Submission Queue (SQ) Doorbell Register (DBR) 213, a Completion Queue (CQ) Doorbell Register (DBR) 215, a Required Time Prediction Circuit 217, a Power Management Circuit 219, and a Temperature Sensor 221.

[0060] Processor 211 can perform various operations on storage device 200 using firmware. In an embodiment, processor 211 can perform operations associated with the flash translation layer (FTL), such as defragmentation operations, which include background operations such as garbage collection, data migration, wear leveling, read refresh, and background trimming for managing storage device 220, error checking and correction (ECC) functions for detecting and correcting errors in data read from storage device 220, etc.

[0061] Although not shown in the accompanying drawings, memory controller 210 may include other components that may be needed during operation of storage device 200, such as external device interface, memory interface, RAM, ROM, buffer memory, and buffer memory manager or controller.

[0062] Each of SQ DBR 213 and CQ DBR 215 is a register that manages or controls queue pairs generated by external device 100, i.e., submission queues. Figure 1 SQ 130) and completion queue ( Figure 1 (CQ 140). SQDBR 213 and CQ DBR 215 can each correspond to a queue pair (SQ and CQ).

[0063] The Submission Queue (SQ) can sequentially store commands generated by the external device 100, and the SQ DBR 213 can store a tail pointer indicating the storage location of the last command in the Submission Queue (SQ).

[0064] When the storage device 200 processes the command and records the completion of the command processing in the completion queue (CQ), the head pointer of the submission queue (SQ) is incremented, and the CQ DBR 215 can receive the head pointer of the completion queue (CQ) from the external device 100 and store the received head pointer.

[0065] In an embodiment, the external device 100 may suspend the execution of command processing requests during an intentional idle time determined by the external device 100, which may include operations for pausing the update of SQ DBR 213.

[0066] Figure 5 This is a conceptual diagram illustrating the command processing procedure based on some embodiments of the disclosed technology.

[0067] The memory controller 210 of storage device 200 can communicate with external device 100 based on a command queue basic interface. Command queue basic interface operations can be performed based on queue pairs, which include a submission queue (SQ) 130 for inputting requested commands and a completion queue (CQ) 140 for recording the processing results of commands.

[0068] When the external device 100 includes multiple cores, each of the multiple cores can perform interface operations with the storage device 200 and the memory controller 210 based on a queue pair, which includes a submit queue (SQ) 130 and a completion queue (CQ) 140.

[0069] The memory controller 210 may include SQ DBR 213 and CQDBR 215 for performing command queue basic interface operations.

[0070] Each of SQ DBR 213 and CQ DBR 215 is a register for managing or controlling queue pairs 130 and 140 generated by external device 100. Each of SQ DBR 213 and CQ DBR 215 may correspond to a queue pair. For example, each of SQ DBR 213 and CQ DBR 215 may store a tail pointer indicating the tail of the submit queue (SQ) 130 and a head pointer indicating the head of the complete queue (CQ). Memory controller 210 can perform interface operations with external device 100 by accessing the queue pair corresponding to each of SQ DBR 213 and CQ DBR 215.

[0071] Specifically, the external device 100 can generate a submission queue 130 and a completion queue 140 in its memory.

[0072] The memory controller 210 can access the submission queue 130 and the completion queue 140 through the SQ DBR 213 and CQ DBR 215, thereby processing commands requested by the external device 100 and notifying the processing results.

[0073] For example, external device 100 can transmit a command COMMAND to submission queue 130 to request a data read or write operation from storage device 200 (S1). The tail pointer of submission queue 130 can be updated, and external device 100 can record the updated tail pointer in SQ DBR 213 of memory controller 210 for later updates (S2).

[0074] The memory controller 210 can retrieve commands from the submission queue 130 (S3) and process (or execute) the retrieved commands (S4). After processing the commands, the memory controller 210 can record the completed command processing in the completion queue 140 (S5). At this time, the head pointer of the completion queue 140 can be incremented. When the memory controller 210 generates an interrupt signal (S6), the external device 100 can process the command completion (S7). The external device 100 can record the updated head pointer of the completion queue (CQ) in the CQ DBR 215 of the memory controller 210 for updating.

[0075] During command processing based on this command queue basic interface, the BGOP control circuit 120, based on some embodiments of the disclosed technology, can transmit a power mode control signal to the storage device 200 in an idle state, and then suspend the update time of the SQ DBR 213 corresponding to the command stored in the submission queue 130 until the intentional idle time expires, thereby allowing the storage device 200 to perform background operations without processing requests from the external device 100.

[0076] Return to reference Figure 4 The required time prediction circuit 217 can generate prediction information by predicting the time required for the memory controller 210 to process the background operation of the memory device 220 for each power mode.

[0077] Taking garbage collection as an example, when the number of valid pages to be acquired is 100, the time required when the power mode is at its highest (maximum performance mode) can be calculated according to the following [Equation 1].

[0078] [Equation 1]

[0079] Required time - Maximum power mode = (100 × (page read time + page programming time)) + (block erase time)

[0080] There may be multiple power modes, such as 1 / 2 performance and 1 / 4 performance of the maximum performance mode, and the required time increases as the amount of the performance mode decreases. For example, in 1 / 2 performance mode, it may take about twice as long as the maximum performance mode, while in 1 / 4 performance mode, it may take about four times as long as the maximum performance mode.

[0081] In some implementations, in addition to the equations described above, environmental variables (e.g., command transfer time or response time in storage device 200), the operating method of storage device 220 (such as plane interleaving), the bus bandwidth (not shown) between storage device 220 and buffer memory, and the overhead of processor 211 may be used or considered to more accurately calculate the time required for background operation for each power mode.

[0082] When <Condition 1> is satisfied while ignoring environmental variables, the time required for background operation for each power mode can be calculated according to the following [Equation 2].

[0083] [Condition 1]

[0084] Number of valid pages to be retrieved = 100

[0085] Bus bandwidth = 400MB / s

[0086] 1 page size = 16KB

[0087] Block erase time = 5ms

[0088] One page transfer time = (400 × 1024 KB) / 16 KB = 40 µs

[0089] [Equation 2]

[0090] Required time - Maximum power mode = (100 × (40us + 40us) + 5ms = 13ms)

[0091] Required time - 1 / 2 power mode = 26ms

[0092] Required time - 1 / 4 power mode = 52ms

[0093] When the storage device 200 is in an idle state, the power management circuit 219 changes the power mode of the storage device 200 based on the power mode control signal transmitted from the external device 100. When the power mode switches from the idle state, the processor 211 can perform background operations.

[0094] In some implementations, background operations may have a priority order, such as garbage collection, data migration, wear leveling, read refresh, and background trimming.

[0095] When switching power modes during the idle state of storage device 200, processor 211 can execute background operations in order of priority. When the power mode control signal includes information about the intended idle time, processor 211 can allocate the intended idle time according to the priority of the background operations and execute multiple background operations sequentially.

[0096] Temperature sensor 221 can sense or detect the temperature of data processing system 10 or storage device 200. In this case, time-determining circuit 217 can transmit prediction information, including temperature information, to external device 100.

[0097] Figure 6 This is a flowchart explaining the operation method of a data processing system based on some embodiments of the disclosed technology.

[0098] Reference Figure 6 While the external device 100 is operating or waiting (S101), the storage device 200 can generate prediction information by predicting the time required for background operations of the storage device 220 for each power mode (S103), and transmit the prediction information to the external device 100 (S105). In embodiments, the prediction information may include the predicted time or required time of the background operations to be performed for each power mode, and in addition to the predicted time or required time, the prediction information may further include temperature information of the data processing system 10 or the storage device 200.

[0099] Background operations may include management operations for the memory device 220, such as garbage collection, data migration, wear leveling, read refresh, and background trimming.

[0100] When transmitting prediction information from storage device 200, external device 100 can check whether storage device 200 is in an idle state (S107).

[0101] When the storage device 200 is in an idle state (S107: Yes), the external device 100 can determine the power mode and intentional idle time of the storage device 200 based on the prediction information transmitted by the storage device 200, and generate a power mode control signal including the determined power mode and intentional idle time (S109). When the prediction information further includes temperature information, the external device 100 can additionally consider the temperature information to determine the power mode.

[0102] When the storage device 200 is not in an idle state (S107: No), the external device 100 may request the storage device 200 to process a command (S200). The command processing procedure (S200) may be based on, for example,... Figure 5 The command queue basic interface shown is used for execution. However, the disclosed techniques are not limited to this.

[0103] In S109, the power mode control signal generated by the external device 100 can be transmitted to the storage device 200 (S111). When the power mode control signal is received in the idle state, the storage device 200 can change the power mode according to the power mode included in the power mode control signal (S113) and perform background operation (S115).

[0104] In some implementations, after the power mode control signal is transmitted to the storage device 200, the external device 100 may set a timer and count whether the intended idle time has expired (S117).

[0105] External device 100 can check whether a new command has been generated (S119). When a command has been generated (S119: Yes), external device 100 can store the generated command in the submission queue (S121). After storing the command in the submission queue, when no command has been generated (S119: No), external device 100 can check whether the timer has expired (S123).

[0106] When the timer expires (S123: Yes), the external device 100 checks whether there are any unprocessed commands in the submission queue (S125).

[0107] When there are unprocessed commands (S125: Yes), the external device 100 can update the submission queue doorbell register (SQ DBR) (S127) and request the storage device 200 to process the command. Therefore, the storage device 200 can, for example, based on... Figure 5 The command queue basic interface shown is used to process commands (S200).

[0108] When there are no unprocessed commands (S125: No), the external device 100 may process another operation or may switch to a waiting state (S131).

[0109] In some implementations, when the timer has not expired (S123: No), i.e., when there is still intentional idle time remaining, the external device 100 may check whether the submission queue doorbell register (SQ DBR) needs to be updated (S129). The situation requiring an update to the submission queue doorbell register (SQ DBR) may be when the submission queue is full; however, the disclosed technology is not limited to this.

[0110] When updating the Submission Queue Doorbell Register (SQ DBR) is not required (S129: No), the external device 100 can suspend the execution of command processing requests to the storage device 200 by not updating the Submission Queue Doorbell Register (SQ DBR). Then, the external device 100 proceeds to S119 to check if a new command has been generated.

[0111] When the submission queue doorbell register (SQ DBR) needs to be updated because the submission queue is full of suspended commands (S129: Yes), the external device 100 can update the submission queue doorbell register (SQ DBR) (S127) and the storage device 200 can process the commands input to the submission queue (S200).

[0112] As described above, the storage device 200 generates prediction information, including the predicted time required for background operation for each power mode, and transmits the generated prediction information to the external device 100. Furthermore, when a power mode control signal is transmitted from the external device 100, the storage device 200, which is in an idle state, switches to the corresponding power mode and performs background operation.

[0113] When storage device 200 enters an idle state, external device 100 determines the power mode and intentional idle time of storage device 200 based on predictive information, allowing storage device 200 to switch to the corresponding power mode and suspend command processing requests during the determined intentional idle time. Therefore, storage device 200 can respond to external device 100's requests with optimal performance by stably executing background operations during the intentional idle time determined by external device 100.

[0114] Figure 7 A diagram illustrating an example of a data storage system 1000 based on some embodiments of the disclosed technology.

[0115] Reference Figure 7 The data storage system 1000 may include a host device 1100 and a data storage device 1200. In an embodiment, the data storage device 1200 may be configured as a solid-state drive (SSD).

[0116] The host device 1100 is configured to include Figures 1 to 3 The external device 100 shown. The data storage device 1200 is configured to include Figures 1 to 4 The storage device 200 shown.

[0117] The data storage device 1200 may include a controller 1210, a plurality of non-volatile memory devices 1220-0 to 1220-n, a buffer memory device 1230, a power supply 1240, a signal connector 1101, and a power connector 1103.

[0118] The controller 1210 can control the general operation of the data storage device 1200. The controller 1210 may include a host interface unit, a control unit, random access memory used as working memory, an error correction code (ECC) unit, and a memory interface unit. In embodiments, the controller 1210 may be configured to... Figure 1 and Figure 2 The controller 110 shown.

[0119] The host device 1100 can exchange signals with the data storage device 1200 through the signal connector 1101. These signals may include commands, addresses, data, etc.

[0120] The controller 1210 can analyze and process signals received from the host device 1100. The controller 1210 can control the operation of internal function blocks according to the firmware or software used to drive the data storage device 1200.

[0121] The buffer memory device 1230 can temporarily store data to be stored in at least one of the non-volatile memory devices 1220-0 to 1220-n. Furthermore, the buffer memory device 1230 can temporarily store data read from at least one of the non-volatile memory devices 1220-0 to 1220-n. Data temporarily stored in the buffer memory device 1230 can be transferred to the host device 1100 or at least one of the non-volatile memory devices 1220-0 to 1220-n under the control of the controller 1210.

[0122] Non-volatile memory devices 1220-0 to 1220-n can be used as storage media for data storage device 1200. Non-volatile memory devices 1220-0 to 1220-n can be connected to controller 1210 via multiple channels CH0 to CHn respectively. One or more non-volatile memory devices can be connected to one channel. Non-volatile memory devices connected to each channel can be connected to the same signal bus and data bus.

[0123] Power supply 1240 can provide power input via power connector 1103 to the controller 1210 of data storage device 1200, non-volatile memory devices 1220-0 to 1220-n, and buffer memory device 1230. Power supply 1240 may include an auxiliary power supply. The auxiliary power supply can supply power to allow normal termination of data storage device 1200 in the event of a sudden power outage. The auxiliary power supply may include a large-capacity capacitor sufficient to store the required charge.

[0124] Depending on the interface scheme between the host device 1100 and the data storage device 1200, the signal connector 1101 can be configured as one or more of various types of connectors.

[0125] Depending on the power supply scheme of the host device 1100, the power connector 1103 can be configured as one or more of various types of connectors.

[0126] Figure 8A diagram illustrating an example of a data processing system 3000 based on some embodiments of the disclosed technology. (Refer to...) Figure 8 The data processing system 3000 may include a host device 3100 and a memory system 3200.

[0127] The host device 3100 is configured to include Figures 1 to 3 The external device 100 shown. The data storage system 3200 is configured to include Figure 1 or Figure 4 The storage device 200 shown.

[0128] The host device 3100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 3100 may include internal function blocks for performing the functions of the host device.

[0129] The host device 3100 may include connection terminals 3110, such as sockets, slots, or connectors. The memory system 3200 may mate with the connection terminals 3110.

[0130] The memory system 3200 can be configured in the form of a board, such as a printed circuit board. The memory system 3200 can be referred to as a memory module or a memory card. The memory system 3200 may include a controller 3210, a buffer memory device 3220, non-volatile memory devices 3231 and 3232, a power management integrated circuit (PMIC) 3240, and a connection terminal 3250.

[0131] The controller 3210 can control the general operation of the memory system 3200. The controller 3210 can be connected to... Figure 1 or Figure 4 The memory controller 210 shown is configured in the same way.

[0132] The buffer memory device 3220 can temporarily store data to be stored in the non-volatile memory devices 3231 and 3232. Furthermore, the buffer memory device 3220 can temporarily store data read from the non-volatile memory devices 3231 and 3232. Under the control of the controller 3210, the data temporarily stored in the buffer memory device 3220 can be transferred to the host device 3100 or the non-volatile memory devices 3231 and 3232.

[0133] Non-volatile memory devices 3231 and 3232 can be used as storage media in memory system 3200.

[0134] The PMIC 3240 can supply power to the memory system 3200 via the connection terminal 3250. The PMIC 3240 can manage the power of the memory system 3200 under the control of the controller 3210.

[0135] Connection terminal 3250 can be connected to connection terminal 3110 of host device 3100. Through connection terminal 3250, signals such as commands, addresses, and data, as well as power, can be transmitted between host device 3100 and memory system 3200. Depending on the interface scheme between host device 3100 and memory system 3200, connection terminal 3250 can be configured as one or more of various types. As shown, connection terminal 3250 can be located on one side of memory system 3200.

[0136] Figure 9 A diagram illustrating an example of a data processing system 4000 based on some embodiments of the disclosed technology. (Refer to...) Figure 9 The data processing system 4000 may include a host device 4100 and a memory system 4200.

[0137] The host device 4100 may be configured as a board, such as a printed circuit board. Although not shown, the host device 4100 may include internal function blocks for performing the functions of the host device.

[0138] The host device 4100 is configured to include Figures 1 to 3 The external device 100 shown. The memory system 4200 is configured to include Figure 1 or Figure 4 The storage device 200 shown.

[0139] The memory system 4200 can be configured in a surface-mount package. The memory system 4200 can be mounted to the host device 4100 using solder balls 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a non-volatile memory device 4230.

[0140] The controller 4210 can control the general operation of the memory system 4200. The controller 4210 can be connected to... Figure 1 and Figure 2 The controller 110 shown is configured in the same way.

[0141] The buffer memory device 4220 can temporarily store data to be stored in the non-volatile memory device 4230. Furthermore, the buffer memory device 4220 can temporarily store data read from the non-volatile memory device 4230. Under the control of the controller 4210, the data temporarily stored in the buffer memory device 4220 can be transferred to the host device 4100 or the non-volatile memory device 4230.

[0142] The non-volatile memory device 4230 can be used as the storage medium of the memory system 4200.

[0143] Figure 10 This is a diagram illustrating an example of a network system 5000 including a data storage device based on some embodiments of the disclosed technology. (Refer to...) Figure 10 The network system 5000 may include a server system 5300 connected via network 5500 and multiple client systems 5410, 5420 and 5430.

[0144] Server system 5300 can serve data in response to requests from multiple client systems 5410 to 5430. For example, server system 5300 can store data provided by multiple client systems 5410 to 5430. Furthermore, server system 5300 can provide data to multiple client systems 5410 to 5430.

[0145] Server system 5300 may include host device 5100 and storage system 5200. Host device 5100 is configured to include Figures 1 to 3 The external device 100 shown. The memory system 5200 is configured to include Figure 1 or Figure 4 The storage device 200 shown.

[0146] Figure 11 This is a block diagram illustrating an example of a non-volatile memory device 300 included in a data storage device such as data storage device 10, based on some embodiments of the disclosed technology. (Refer to...) Figure 11 The non-volatile memory device 300 may include a memory cell array 310, a row decoder 320, a data read / write block 330, a column decoder 340, a voltage generator 350, and control logic 360.

[0147] The memory cell array 310 may include memory cells MC, which are located in the region where word lines WL1 to WLm and bit lines BL1 to BLn intersect.

[0148] The memory cell array 310 may include a three-dimensional memory array. For example, the three-dimensional memory array has a stacked structure with its orientation perpendicular to a plane of the semiconductor substrate. Furthermore, a three-dimensional memory array refers to a structure comprising NAND strings, wherein the memory cells included in the NAND strings are stacked perpendicular to a plane of the semiconductor substrate.

[0149] The structure of a three-dimensional memory array is not limited to the embodiments described above. Memory array structures with both horizontal and vertical orientations can be formed in a highly integrated manner. In embodiments, within the NAND strings of a three-dimensional memory array, memory cells are arranged in both horizontal and vertical directions relative to the surface of the semiconductor substrate. The memory cells can be spaced apart in various ways to provide different levels of integration.

[0150] The row decoder 320 can be connected to the memory cell array 310 via word lines WL1 to WLm. The row decoder 320 can operate under the control of control logic 360. The row decoder 320 can decode addresses provided by external devices (not shown). The row decoder 320 can select and drive word lines WL1 to WLm based on the decoding result. For example, the row decoder 320 can provide word line voltages provided by voltage generator 350 to word lines WL1 to WLm.

[0151] The data read / write block 330 can be connected to the memory cell array 310 via bit lines BL1 to BLn. The data read / write block 330 may each include read / write circuits RW1 to RWn corresponding to bit lines BL1 to BLn. The data read / write block 330 can be operated under the control of control logic 360. Depending on the operating mode, the data read / write block 330 can operate as a write driver or a sense amplifier. For example, the data read / write block 330 can operate as a write driver, in which it stores data provided by an external device into the memory cell array 310 during a write operation. Alternatively, the data read / write block 330 can operate as a sense amplifier, in which it reads data from the memory cell array 310 during a read operation.

[0152] The column decoder 340 can operate under the control of the control logic 360. The column decoder 340 can decode addresses provided by external devices. Based on the decoding result, the column decoder 340 can connect the read / write circuits RW1 to RWn of the data read / write blocks 330 corresponding to bit lines BL1 to BLn to the data input / output lines or data input / output buffers.

[0153] Voltage generator 350 can generate voltages to be used in the internal operation of non-volatile memory device 300. The voltage generated by voltage generator 350 can be applied to the memory cells of memory cell array 310. For example, a programming voltage generated during a programming operation can be applied to the word line of the memory cell to which the programming operation is to be performed. Similarly, an erase voltage generated during an erase operation can be applied to the well region of the memory cell to which the erase operation is to be performed. And yet another example is that a read voltage generated during a read operation can be applied to the word line of the memory cell to which the read operation is to be performed.

[0154] Based on control signals provided by an external device, control logic 360 can control the general operation of non-volatile memory device 300. For example, control logic 360 can control the operation of non-volatile memory device 300, such as read operations, write operations and erase operations of non-volatile memory device 300.

[0155] Although this patent application includes numerous details in the disclosed examples, these details should not be construed as limiting the scope of any subject matter or potentially claimed content, but rather as descriptions of features that may be specific to particular embodiments. Certain features described in the context of different embodiments in this patent application may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although the foregoing features may be described as functioning in certain combinations, or even initially claimed in this manner, one or more features of a claimed combination may be removed from the claimed combination in certain circumstances, thus the claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0156] Only some implementation schemes and examples are described, and other implementation schemes, enhancements and variations may be derived based on the content described and shown in this patent application.

Claims

1. A data processing system, comprising: The storage device transmits prediction information for each power mode to the outside and switches to the corresponding power mode in response to a power mode control signal received in the idle state of the storage device, and performs background operations to manage the storage device in the idle state, wherein the prediction information indicates the prediction time for performing the background operations; as well as The control device determines the power mode of the storage device and the idle time of the idle state during which the background operation is performed, based on the prediction information, transmits the power mode control signal to the storage device, and suspends the execution of command processing requests transmitted to the storage device during the idle time.

2. The data processing system according to claim 1, wherein the control device includes a submission queue corresponding to the newly generated command. The storage device includes a commit queue register that stores a tail pointer indicating the storage location of the last command in the commit queue. The control device suspends updating the tail pointer in order to suspend the execution of the command processing request.

3. The data processing system according to claim 2, wherein the control device updates the tail pointer when the submission queue becomes full during the idle time.

4. The data processing system of claim 1, wherein the storage device further includes a temperature sensor, and the prediction information further includes temperature information.

5. The data processing system of claim 4, wherein the control device determines the power mode and the idle time of the storage device by further referring to the temperature information.

6. The data processing system of claim 1, wherein the storage device remains substantially idle during the idle time.

7. The data processing system of claim 1, wherein the prediction information and the power mode control signal are transmitted or received via an interface device based on one of the system management bus protocol (SMBus), the internal integrated circuit protocol (I2C), and the improved internal integrated circuit protocol (I3C).

8. The data processing system according to claim 1, wherein the background operation includes at least one of garbage collection, data migration, wear leveling, read refresh, and background trimming.

9. A method for operating a data processing system, the method comprising: Generate prediction information indicating the predicted time spent performing background operations on the management memory device for each power mode; Based on the predicted information, the power mode of the storage device and the idle time for performing the background operation are determined, so as to transmit the power mode control signal corresponding to the power mode to the storage device. When the power mode control signal is received in the idle state, the background operation is executed by switching to the power mode corresponding to the power mode control signal; and During the idle time, the execution of command processing requests transmitted to the data processing system is suspended.

10. The method of operation according to claim 9, wherein the data processing system includes an external device and the storage device, wherein the external device includes a submission queue corresponding to newly generated commands. The storage device includes a commit queue register that stores a tail pointer indicating the storage location of the last command in the commit queue. The request to suspend the execution of the command processing includes suspending the update of the tail pointer.

11. The operating method according to claim 10, further comprising: During the idle time, the tail pointer is updated when the submission queue becomes full.

12. The method of operation according to claim 9, wherein the data processing system further includes a temperature sensor, and generates the prediction information, further including temperature information.

13. The method of operation according to claim 12, further comprising referencing the temperature information when generating the power mode control signal.

14. The method of operation according to claim 9, further comprising maintaining an idle state during the idle time.

15. The method of operation according to claim 9, wherein the prediction information and the power mode control signal are transmitted or received via an interface device based on one of the System Management Bus protocol (SMBus), the Internal Integrated Circuit protocol (I2C), and the modified Internal Integrated Circuit protocol (I3C).

16. The operation method according to claim 9, wherein the background operation includes at least one of garbage collection, data migration, wear leveling, read refresh, and background trimming.

17. A storage device, comprising: Memory devices; as well as The memory controller transmits prediction information for each power mode to the outside and switches to the corresponding power mode in response to receiving a power mode control signal from the outside in the idle state, and performs background operations to be performed on the memory device in the idle state, wherein the prediction information indicates the predicted time for performing the background operations.

18. The storage device of claim 17, wherein the memory controller includes a commit queue register that stores a tail pointer updated by the external source and performs the background operation before the tail pointer is updated.

19. The storage device of claim 17, wherein the storage device further comprises a temperature sensor, and the prediction information further comprises temperature information.

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