A performance analysis method and system based on an NPI interface and a storage medium

Abstract

The application discloses a performance analysis method based on an NPI interface, which comprises the following steps: acquiring an fsdb waveform file of an interface bus in an SoC chip in real time through the NPI interface; performing interface classification statistical processing on the fsdb waveform file to obtain signal values and corresponding time information of signals transmitted in each channel of the interface bus; performing merging processing on the signal values and the corresponding time information of the signals transmitted in each channel of the interface bus to obtain corresponding occurrence start time, end time and corresponding data content of each read transmission or write transmission in a preset time period; and calculating and analyzing performance data of the interface bus according to the result obtained through the merging processing, wherein the performance data at least comprises maximum time delay, minimum time delay and average time delay. The application further discloses a corresponding system and a storage medium. By implementing the application, the read-write performance of the interface bus can be conveniently and effectively counted, and the application has the advantages of high efficiency and low cost.

Description

Technical Field

[0001] This invention relates to the field of bus performance analysis technology for system-on-chip (SoC), and in particular, to a performance analysis method, system, and storage medium based on a native programming interface (NPI). Background Technology

[0002] In the design of large-scale SoC (System-on-a-Chip) chips, the bus structure is extremely complex. These buses are the main channels connecting the Central Processing Unit (CPU), computing subsystems, and memory (e.g., DDR memory) within the SoC chip. Their performance directly impacts the efficiency of each computing subsystem and the CPU; therefore, bus performance analysis is a crucial aspect of the success of a chip product. For example... Figure 1 This diagram illustrates the connection relationship between the bus and various components in a typical SoC chip system in the prior art.

[0003] In SoC chip systems, the main evaluation metric for bus read / write performance is the bus's transmission efficiency (i.e., bandwidth) over a period of time. This bandwidth is primarily determined by factors such as bus congestion, bus width, bus operating frequency, and bus transmission behavior.

[0004] In existing technologies, the read / write performance of a bus is generally analyzed using the following methods:

[0005] Firstly, one can indirectly analyze whether the bus meets the requirements by calculating the CPU read / write bandwidth; however, this method can only show the performance results and cannot analyze the ways to improve performance further, so it can only be used as a supplementary method.

[0006] Secondly, the bus demand can be indirectly analyzed by counting the number of key signal triggers of each node within the bus through the power management unit (PMU) embedded in the bus. This method can collect most of the bus information as required. However, the information that a PMU can collect at one time is generally limited. In order to analyze a certain scenario, it may be necessary to set different sampling signals multiple times to collect different information. This method is inefficient and can only be used as a supplementary means.

[0007] Thirdly, an external bus monitoring component can be used to determine whether the performance of a certain interface meets the requirements. This bus monitoring component can be designed to collect any bus information according to the requirements. However, the drawback of this method is that as the requirements become more complex, the design complexity of the monitoring component and the amount of logic units consumed also increase. Moreover, each interface requires an independent monitoring component, which consumes huge logical resources and also brings additional system integration costs.

[0008] Fourth, by analyzing the simulation waveform graphically to view the behavior of the bus, one can roughly determine whether the bus performance meets the requirements; however, this method cannot obtain quantitative judgments, and it is easy to overlook some key information in a large waveform file.

[0009] Therefore, in the existing technology, there is no simple and effective method to statistically analyze the read and write performance of the bus. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a performance analysis method, system and storage medium based on the NPI interface, which can easily and effectively count the read and write performance of the interface bus, and has the advantages of high efficiency and low cost.

[0011] To address the aforementioned technical problems, as one aspect of the present invention, a performance analysis method based on the NPI interface is provided, which includes at least the following steps:

[0012] The waveform files of the Fast Signal Database (fsdb) of the interface bus in the SoC chip are obtained in real time through the Raw Programming Interface (NPI).

[0013] Perform interface classification and statistical processing on the fsdb waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus.

[0014] The signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus are merged to obtain the start time, end time and corresponding data content of each read or write transmission within a preset time period.

[0015] Based on the results obtained through merging processing, the performance data of the interface bus is calculated and analyzed, and the performance data includes at least: maximum latency, minimum latency, and average latency.

[0016] The step of performing interface classification and statistical processing on the fsdb waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus further includes:

[0017] The interface classification and statistics script is executed to perform statistical processing on the contents of each channel in the interface bus described in the fsdb waveform file. At each clock rise, the value of the handshake signal is judged. When the value of all handshake signals is high, the value and time information of each transmission signal in the channel are extracted.

[0018] Wherein, when the interface bus in the SoC chip is an AXI bus, the execution of the interface classification and statistics script performs statistical processing on the contents of each channel in the interface bus in the fsdb waveform file, judges the value of the handshake signal at each clock rise, and extracts the value and time information of each transmission signal in the channel when all handshake signal values ​​are high. This further includes:

[0019] For reading the contents of the address and control channels in the AXI bus, when the values ​​of arvalid and readyy are both 1 at each rising edge of the clock, the values ​​of the corresponding aradr, arid, and arlen signals and the corresponding time information of this channel are extracted.

[0020] For reading data from the AXI bus, at each rising edge of the clock, when the values ​​of rvalid and rready are both 1, the values ​​of the corresponding rid, rdata, and rlast signals and the corresponding time information of this channel are extracted.

[0021] For writing address and control channel content in AXI bus, when the values ​​of awvalid and awready are both 1 at each rising edge of clock, extract the values ​​of awaddr, awid, and awlen signals corresponding to this channel and the corresponding time information.

[0022] For writing data channel content in AXI bus, when the values ​​of wvalid and wready are both 1 at each rising edge of clock, extract the values ​​of wdata, wstrb, and wlast signals corresponding to this channel and the corresponding time information.

[0023] For the write response channel content in the AXI bus, at each rising edge of the clock, if the values ​​of bvalid and bready are both 1, the value of bid and the corresponding time information of this channel are extracted.

[0024] Specifically, the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus are merged to obtain the start time, end time, and corresponding data of each read / write transmission within a fixed time period.

[0025] Execute the channel merging script, obtain the ID information of write transmission or read transmission based on the value and time information of each transmission signal extracted from the channel, and use the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission.

[0026] The execution channel merging script, based on the extracted values ​​and time information of each transmission signal in the channel, obtains the ID information of write or read transmissions, and uses the ID information to match and merge the information of each channel to obtain the content of each write or read transmission, further includes:

[0027] The execution channel merging script, based on the extracted values ​​and time information of each transmission signal in the channel, obtains the ID information of write or read transmissions, and uses the ID information to match and merge the information of each channel to obtain the content of each write or read transmission, further includes:

[0028] For read transfers, based on the AID information of each transfer obtained through the read address and control channel statistics, and the time information of the transfer, the nearest "awlen+1" transfer with a RID value equal to the AID is searched in the read data channel in chronological order from front to back. The last transfer of data ends with rlast being valid. After matching, they are merged to form a read transfer. This process is repeated to merge each transfer of the read address and control channel. Each merged read transfer includes the start time of each read transfer, the issued read address, the issued read control command, the time of each received data, and the time of the last received data.

[0029] For write transfers, based on the awid information of each transfer obtained through the write address and control channel statistics, and the time information of the transfer, the write response channel is searched in chronological order from beginning to end for the transfer with a bid value equal to the awid value and the transfer closest to the time when the write address and control signal were issued. After matching, the start time and end time of the transfer are obtained. At the same time, the corresponding data of the write data channel is extracted in sequence based on the awlen information. Each merged write transfer includes the start time of each write transfer, the issued write address and write control command information, the time when the "awlen+1" write data occurred, and the final completion time of the transfer.

[0030] Specifically, the step of calculating and analyzing the performance data of the interface bus based on the data obtained from the merging process includes:

[0031] Execute the read / write performance analysis script to obtain the amount of read and write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

[0032] The step of comparing the latency of each transmission to obtain the maximum and minimum latency and corresponding transmission information, and calculating the average latency, further includes:

[0033] Based on the start and end times of each read or write transfer, calculate the latency of each transfer using the following formula:

[0034] delay = end_time - start_time

[0035] Where start_time is the start time of the transmission and end_time is the end time of the transmission;

[0036] Sort all delay values ​​and determine the maximum and minimum delay values ​​and their corresponding transmission information;

[0037] The average delay is obtained by calculating the delay of all transmissions using the following formula:

[0038] average_delay=sum_of_delays / number_of_transfers

[0039] Where sum_of_delays is the total delay of all transmissions, and number_of_transfers is the total number of transmission operations.

[0040] Accordingly, another aspect of the present invention also provides a performance analysis system based on an NP interface, which includes at least:

[0041] The waveform file acquisition unit is used to acquire waveform files of the Fast Signal Database (FSDB) of the interface bus in the SoC chip in real time through the Raw Programming Interface (NPI);

[0042] The classification and statistics unit is used to perform interface classification and statistics processing on the FSDB waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus.

[0043] The merging processing unit is used to merge the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus to obtain the start time, end time and corresponding data content of each read or write transmission within a preset time period.

[0044] The performance analysis unit is used to calculate and analyze the performance data of the interface bus based on the results obtained through merging processing. The performance data includes at least: maximum latency, minimum latency, and average latency.

[0045] The classification and statistics unit includes a first script execution unit, which is used to execute an interface classification and statistics script to perform statistical processing on the contents of each channel in the interface bus in the fsdb waveform file. At each clock rise, the value of the handshake signal is judged. When the value of all handshake signals is high, the value and time information of each transmission signal in the channel are extracted.

[0046] The merging processing unit includes a second script execution unit, which is used to execute a channel merging script, obtain the ID information of write transmission or read transmission based on the extracted values ​​and time information of each transmission signal in the channel, and use the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission.

[0047] The performance analysis unit includes a third script execution unit, which is used to execute a read / write performance analysis script, statistically obtain the amount of read / write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

[0048] In another aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0049] In another aspect, the present invention provides a computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method as described above.

[0050] Implementing the embodiments of the present invention has the following beneficial effects:

[0051] This invention provides a performance analysis method, system, and storage medium based on the NPI interface. It directly analyzes the performance of the internal interface bus based on the NPI interface through the fsdb waveform file, thereby effectively calculating the overall performance of the entire SoC chip and conveniently locating and analyzing the performance analysis caused by potential design and structural issues in the bus.

[0052] Meanwhile, the solution is versatile, reusable, and easy to use, and is not affected by any testing environment. It effectively improves the efficiency of bus evaluation and analysis in SoC chip system design and reduces costs. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, obtaining other drawings based on these drawings without creative effort still falls within the scope of the present invention.

[0054] Figure 1 This is a schematic diagram illustrating the connection relationship between the bus and various components in a typical SoC chip system in the prior art.

[0055] Figure 2 This is a schematic diagram of the main flow of an embodiment of a performance analysis method based on the NPI interface provided by the present invention;

[0056] Figure 3 This is a schematic diagram of the write data related channels of the AXI bus involved in the present invention;

[0057] Figure 4 This is a schematic diagram of the channels related to reading data on the AXI bus involved in the present invention;

[0058] Figure 5 This is a schematic diagram of an embodiment of a performance analysis system based on the NPI interface provided by the present invention. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0060] like Figure 2 The diagram shows the main flow of an embodiment of a performance analysis method based on the NPI interface provided by the present invention; combined with... Figure 2 and Figure 3 As shown.

[0061] Before describing the steps of the method of the present invention, a brief introduction will be given to the AXI bus involved in one embodiment of the method of the present invention.

[0062] like Figure 2 and Figure 3As shown, the AXI bus is a bus protocol provided by ARM, short for Advanced eXtensible Interface. The AXI bus consists of five channels for read and write operations. Write operations involve the Write Address and Control channel, the Write Data channel, and the Write Response channel; read operations involve the Read Address and Control channel and the Read Data channel. Each channel has its own independent handshake signal to indicate a valid transmission.

[0063] The main signals for writing the address and control channel include: channel handshake signals awvalid and awready; channel address signal awaddr; transmission ID identifier awid; transmission length awlen; transmission width awsize; and other control signals.

[0064] The main signals for writing data channels include: channel handshake signals wvalid and wready; channel data signals wdata and wlast, etc.

[0065] The main signals for writing a reply channel include: channel handshake signals bvalid and bready; and the transmission ID identifier bid.

[0066] The main signals for reading the address and control channel include: channel handshake signals arvalid and prepared; channel address signal araddr; transmission ID identifier arid; transmission length arlen; transmission width arsize; and other control signals.

[0067] The main signals for the read data channel include: channel handshake signals rvalid and rready; and channel data signals rdata and rlast.

[0068] The meanings of each signal are based on existing technology and will not be elaborated upon here.

[0069] In simple terms, a complete write operation in the AXI bus includes at least the following:

[0070] The sender sends the address (awaddr) and control signals to the write address and control channel when the channel handshake signal is valid;

[0071] Then, when the write data channel handshake signal is valid, it is sent to the write data channel;

[0072] Finally, wait for the receiver to return a confirmation of the write transmission on the write reply channel (when the channel handshake signal is valid and bid = awid).

[0073] A single read operation on the AXI bus includes at least the following steps: the sender sends the address and control signals to the read address and control channel, and then waits for the receiver on the read data channel to return the read data corresponding to the read transmission.

[0074] Please continue to refer to this. Figure 1 As shown, in this embodiment, the performance analysis method based on the NPI interface provided by the present invention includes at least the following steps:

[0075] Step S10: Obtain the waveform file of the Fast Signal Database (fsdb) of the interface bus in the SoC chip in real time through the Raw Programming Interface (NPI);

[0076] Understandably, the NPI interface specification defines a universal interface method, enabling different chip models to be compatible with various processors and achieve efficient data exchange and communication. The FSDB waveform file, supported by Spring Soft (Novas)'s Debussy / Verdi, is similar to a VCD waveform file, but it only extracts the useful information from the simulation process, removing some redundant information; therefore, FSDB waveform files are usually smaller. The FSDB waveform file for the interface bus can be used to record interface bus waveform information, such as timing information including data transmission, control signals, and clock signals. Furthermore, FSDB waveform files can also record system status, data, and signal logic information, facilitating simulation and debugging for developers.

[0077] Step S11: Perform interface classification and statistical processing on the fsdb waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus.

[0078] In a specific example, step S11 further includes:

[0079] The interface classification and statistics script is executed to perform statistical processing on the contents of each channel in the interface bus described in the fsdb waveform file. At each clock rise, the value of the handshake signal is judged. When the value of all handshake signals is high, the value and time information of each transmission signal in the channel are extracted.

[0080] As can be understood, based on the foregoing description, the AXI bus includes a total of five channels. Each channel has independent valid and ready signals for handshaking. When the corresponding channel's clock rises and the condition "valid & ready == 1" is met, the data corresponding to that rising edge is valid and can be used for data extraction.

[0081] The above steps can be implemented in the following ways:

[0082] Step S110: For reading the contents of the address and control channels in the AXI bus, at each rising edge of the clock, when it is determined that the values ​​of arvalid and already are both 1, extract the values ​​of the corresponding aradr, arid, and arlen signals and the corresponding time information for this channel; where each extraction represents the occurrence of a transmission.

[0083] The following is a specific script program to illustrate the implementation process. This script program is used to extract signals from a channel of an AXI interface:

[0084] fileHandle=waveform.open("CPU.fsdb")

[0085] tb=waveform.TimeBasedHandle()

[0086] sigName="tb_CPUsystem.NewBus.Arvalid"

[0087] signal=fileHandle.sig_by_name(sigName)

[0088] tb.add(signal)

[0089] sigName="tb_CPUsystem.NewBus.Arready"

[0090] signal=fileHandle.sig_by_name(sigName)

[0091] tb.add(signal)

[0092] tb.iter_start(0,500)

[0093] currTime=0

[0094] while True:

[0095] idx = 0

[0096] idx,currTime = tb.iter_next()

[0097] if idx == 0:

[0098] break;

[0099] print("idx",idx,"time:",currTime,"value:",tb.get_value(waveform.VctFormat_e.BinStrVal))

[0100] tb.iter_stop()

[0101] Result

[0102] idx 1time:0value:0

[0103] idx 2time:0value:0

[0104] idx 2time:350value:1

[0105] idx 1time:350value:1

[0106] idx 1time:450value:0

[0107] idx 2time:450value:0

[0108] The signal values ​​are extracted separately for each channel, and the extraction condition is that the handshake signal of the corresponding channel is 1 at the rising edge of the clock.

[0109] Understandably, this code is used to read the value of a specified signal from an FSDB waveform file and output it. Specifically, the main function of this code is:

[0110] Open the FSDB file, named "CPU.fsdb".

[0111] Create a Time Based Handle object tb, which is used to process time-based signal values.

[0112] Get the signal object with the specified signal sigName and add it to the tb object.

[0113] Configure the start and end times of iteration for the tb object.

[0114] The program reads the signal value of the tb object at each time point in a loop and outputs it to the console.

[0115] The signals in this code are extracted from the "NewBus" interface of a CPU system, including the Arvalid and Arready signals. Here, the start of the handshake channel is defined by detecting that both signals are 1 simultaneously at the rising edge of the clock. Therefore, in each loop, the signal values ​​of the handshake channel are read and output to the console, including time information, signal values, etc., to determine the correctness of the data path.

[0116] It is understandable that data content and time information for other channels in AXI can be obtained through the same or similar interface-based statistical scripts. Specifically:

[0117] Step S111: For the content of the read data channel in the AXI bus, at each rising edge of the clock, when it is determined that the values ​​of rvalid and rready are both 1, extract the values ​​of the corresponding rid, rdata, and rlast signals and the corresponding time information of this channel; wherein, each extraction represents that a piece of data has been received on the read data channel.

[0118] Step S112: For the content of the write address and control channel in the AXI bus, at each rising edge of the clock, when it is determined that the values ​​of awvalid and awready are both 1, extract the values ​​of the corresponding awaddr, awid, and awlen signals and the corresponding time information of this channel; where each piece of data represents a write transmission.

[0119] Step S113: For the write data channel content in the AXI bus, at each rising edge of the clock, when it is determined that the values ​​of wvalid and wready are both 1, extract the values ​​of wdata, wstrb, and wlast signals corresponding to this channel and the corresponding time information.

[0120] Step S114: For the write reply channel content in the AXI bus, at each rising edge of the clock, if the values ​​of bvalid and bready are both 1, extract the value of bid and the corresponding time information of this channel.

[0121] Step S12: Merge the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus to obtain the start time, end time and corresponding data content of each read or write transmission within a preset time period.

[0122] In a specific example, step S12 further includes:

[0123] The channel merging script is executed to obtain the ID information of write or read transmissions based on the extracted values ​​and time information of each transmitted signal in the channel. This ID information is then used to match and merge the information from each channel to obtain the content of each write or read transmission. For example, based on the results of the interface classification and statistics script, write transmissions have completed the collection of data information from three independent channels. For a complete transmission, because it involves cooperation between the sender and receiver, according to the AXI protocol, AXI read and write operations use transmission ID information to match and merge the information from each channel.

[0124] The execution channel merging script, based on the extracted values ​​and time information of each transmission signal in the channel, obtains the ID information of write or read transmissions, and uses the ID information to match and merge the information of each channel to obtain the content of each write or read transmission, further includes:

[0125] 5. The method as described in claim 4, characterized in that, the execution of the channel merging script, based on the extracted values ​​and time information of each transmission signal in the channel, obtains the ID information of the write transmission or read transmission, and uses the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission, further includes:

[0126] For read transfers, based on the AID information of each transfer obtained through the read address and control channel statistics, and the time information of the transfer, the nearest "awlen+1" transfer with a RID value equal to the AID is searched in the read data channel in chronological order from front to back. The last transfer of data ends with rlast being valid. After matching, they are merged to form a read transfer. This process is repeated to merge each transfer of the read address and control channel. Each merged read transfer includes the start time of each read transfer, the issued read address, the issued read control command, the time of each received data, and the time of the last received data (i.e., the time of the completion of the transfer).

[0127] For write transfers, based on the awid information of each transfer obtained through the write address and control channel statistics, and the time information of the transfer, the write response channel is searched in chronological order from beginning to end for the transfer with a bid value equal to the awid value and the transfer closest to the time when the write address and control signal were issued. After matching, the start time and end time of the transfer are obtained. At the same time, the corresponding data of the write data channel is extracted in sequence based on the awlen information. Each merged write transfer includes the start time of each write transfer, the issued write address and write control command information, the time when the "awlen+1" write data occurred, and the final completion time of the transfer.

[0128] Step S13: Based on the results obtained through merging processing, calculate and analyze the performance data of the interface bus. The performance data includes at least: maximum latency, minimum latency, and average latency.

[0129] Specifically, in one example, step S13 further includes:

[0130] Execute the read / write performance analysis script to obtain the amount of read and write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

[0131] The step of comparing the latency of each transmission to obtain the maximum and minimum latency and corresponding transmission information, and calculating the average latency, can be achieved using the following steps:

[0132] Based on the start and end times of each read or write transfer, calculate the latency of each transfer using the following formula:

[0133] delay = end_time - start_time

[0134] Where start_time is the start time of the transmission and end_time is the end time of the transmission;

[0135] Sort all delay values ​​and determine the maximum and minimum delay values ​​and their corresponding transmission information;

[0136] The average delay is obtained by calculating the delay of all transmissions using the following formula:

[0137] average_delay=sum_of_delays / number_of_transfers

[0138] Where sum_of_delays is the total delay of all transmissions, and number_of_transfers is the total number of transmission operations.

[0139] Clearly, using the method provided by this invention, the bandwidth performance of the AXI bus can be evaluated by analyzing the read or write operations completed within a certain period of time, while the transmission latency can be evaluated using the completion time of each transmission within that period. Implementing this invention offers the advantages of high efficiency and low cost.

[0140] Furthermore, it is understood that the method of this invention can also be applied to analyze the performance of other interface buses. For example, it can be applied to buses such as ACE (ARM Cache Coherent Extensions) and CHI (Cache Coherent Interconnect for Accelerators), as the principles are the same.

[0141] like Figure 5 The diagram illustrates a structural schematic of an embodiment of a performance analysis system based on an NPI interface provided by the present invention. In this embodiment, the performance analysis system 1 based on the NPI interface includes at least:

[0142] The waveform file acquisition unit 10 is used to acquire the fast signal database (fsdb) waveform file of the interface bus in the SoC chip in real time through the raw programming interface (NPI);

[0143] The classification and statistics unit 11 is used to perform interface classification and statistics processing on the fsdb waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus.

[0144] Specifically, the classification and statistics unit 11 includes a first script execution unit, which is used to execute an interface classification and statistics script to perform statistical processing on the contents of each channel in the interface bus in the fsdb waveform file, to judge the value of the handshake signal at each clock rise, and to extract the value and time information of each transmission signal in the channel when all handshake signal values ​​are high.

[0145] The merging processing unit 12 is used to merge the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus to obtain the start time, end time and corresponding data content of each read transmission or write transmission within a preset time period.

[0146] Specifically, the merging processing unit 13 includes a second script execution unit, which is used to execute a channel merging script, obtain the ID information of write transmission or read transmission based on the extracted values ​​and time information of each transmission signal in the channel, and use the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission.

[0147] The performance analysis unit 13 is used to calculate and analyze the performance data of the interface bus based on the results obtained through merging processing. The performance data includes at least: maximum latency, minimum latency, and average latency.

[0148] Specifically, the performance analysis unit 13 includes a third script execution unit, which is used to execute a read / write performance analysis script, statistically obtain the amount of read / write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

[0149] It is understood that the specific processes of executing the interface classification and statistics script, the channel merging script, and the read / write performance analysis script can be referred to and combined with the aforementioned... Figure 1 Explanation.

[0150] For more details, please refer to and combine with the above. Figures 1 to 3 The description of that will not be repeated here.

[0151] In another aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned... Figures 1 to 3 The steps of the described method. For more details, please refer to the aforementioned section. Figure 1 and Figure 3 The description of that will not be repeated here.

[0152] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the aforementioned... Figures 1 to 3 The steps of the described method. For more details, please refer to the aforementioned section. Figure 1 and Figure 3 The description of that will not be repeated here.

[0153] Implementing the embodiments of the present invention has the following beneficial effects:

[0154] This invention provides a performance analysis method, system, and storage medium based on the NPI interface. It directly analyzes the performance of the internal interface bus based on the NPI interface through the fsdb waveform file, thereby effectively calculating the overall performance of the entire SoC chip and conveniently locating and analyzing the performance analysis caused by potential design and structural issues in the bus.

[0155] This solution is versatile, reusable, and easy to use, and is unaffected by any testing environment, effectively improving the efficiency of bus evaluation and analysis in SoC chip system design and reducing costs. Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0156] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0157] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A performance analysis method based on the NPI interface, characterized in that, It should include at least the following steps: The waveform files of the Fast Signal Database (fsdb) of the interface bus in the SoC chip are obtained in real time through the Raw Programming Interface (NPI). Perform interface classification and statistical processing on the fsdb waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus. The signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus are merged to obtain the start time, end time and corresponding data content of each read or write transmission within a preset time period. Based on the results obtained from the merging process, the performance data of the interface bus is calculated and analyzed. The performance data includes at least the maximum latency, minimum latency, and average latency.

2. The method as described in claim 1, characterized in that, The step of performing interface classification and statistical processing on the FSDB waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus further includes: The interface classification and statistics script is executed to perform statistical processing on the contents of each channel in the interface bus described in the fsdb waveform file. At each rising edge of the clock, the value of the handshake signal is judged. When the value of all handshake signals is high, the value and time information of each transmission signal in the channel are extracted.

3. The method as described in claim 2, characterized in that, When the interface bus in the SoC chip is an AXI bus, the execution of the interface classification and statistics script performs statistical processing on the contents of each channel in the interface bus in the fsdb waveform file. At each clock rise, the value of the handshake signal is judged. When all handshake signal values ​​are high, the value and time information of each transmission signal in the channel are extracted, further including: For reading the contents of the address and control channels in the AXI bus, when the values ​​of arvalid and readyy are both 1 at each rising edge of the clock, the values ​​of the corresponding aradr, arid, and arlen signals and the corresponding time information of this channel are extracted. For reading data from the AXI bus, at each rising edge of the clock, when the values ​​of rvalid and rready are both 1, the values ​​of the corresponding rid, rdata, and rlast signals and the corresponding time information of this channel are extracted. For writing address and control channel content in AXI bus, when the values ​​of awvalid and awready are both 1 at each rising edge of clock, extract the values ​​of awaddr, awid, and awlen signals corresponding to this channel and the corresponding time information. For writing data channel content in AXI bus, when the values ​​of wvalid and wready are both 1 at each rising edge of clock, extract the values ​​of wdata, wstrb, and wlast signals corresponding to this channel and the corresponding time information. For the write response channel content in the AXI bus, at each rising edge of the clock, if the values ​​of bvalid and bready are both 1, the value of bid and the corresponding time information of this channel are extracted.

4. The method as described in claim 3, characterized in that, The signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus are merged to obtain the start time, end time, and corresponding data of each read / write transmission within a fixed time period, specifically: Execute the channel merging script, obtain the ID information of write transmission or read transmission based on the value and time information of each transmission signal extracted from the channel, and use the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission.

5. The method as described in claim 4, characterized in that, The execution channel merging script, based on the extracted values ​​and time information of each transmission signal in the channel, obtains the ID information of write or read transmissions, and uses the ID information to match and merge the information of each channel to obtain the content of each write or read transmission, further including: For read transfers, based on the AID information of each transfer obtained through the read address and control channel statistics, and the time information of the transfer, the nearest "awlen+1" transfer with a RID value equal to the AID is searched in the read data channel in chronological order from front to back. The last transfer of data ends with rlast being valid. After matching, they are merged to form a read transfer. This process is repeated to merge each transfer of the read address and control channel. Each merged read transfer includes the start time of each read transfer, the issued read address, the issued read control command, the time of each received data, and the time of the last received data. For write transfers, based on the awid information of each transfer obtained through the write address and control channel statistics, and the time information of the transfer, the write response channel is searched in chronological order from beginning to end for the transfer with a bid value equal to the awid value and the transfer closest to the time when the write address and control signal were issued. After matching, the start time and end time of the transfer are obtained. At the same time, the corresponding data of the write data channel is extracted in sequence based on the awlen information. Each merged write transfer includes the start time of each write transfer, the issued write address and write control command information, the time when the "awlen+1" write data occurred, and the final completion time of the transfer.

6. The method according to any one of claims 1 to 5, characterized in that, The step of calculating and analyzing the performance data of the interface bus based on the data obtained from the merging process specifically involves: Execute the read / write performance analysis script to obtain the amount of read and write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

7. The method as described in claim 6, characterized in that, The step of comparing the latency of each transmission to obtain the maximum and minimum latency and corresponding transmission information, and calculating the average latency, further includes: Based on the start and end times of each read or write transfer, calculate the latency of each transfer using the following formula: delay = end_time - start_time Where start_time is the start time of the transmission and end_time is the end time of the transmission; Sort all delay values ​​and determine the maximum and minimum delay values ​​and their corresponding transmission information; The average delay is obtained by calculating the delay of all transmissions using the following formula: average_delay=sum_of_delays / number_of_transfers Where sum_of_delays is the total delay of all transmissions, and number_of_transfers is the total number of transmission operations.

8. A performance analysis system based on an NP interface, characterized in that, At least including: The waveform file acquisition unit is used to acquire waveform files of the Fast Signal Database (FSDB) of the interface bus in the SoC chip in real time through the Raw Programming Interface (NPI); The classification and statistics unit is used to perform interface classification and statistics processing on the FSDB waveform file to obtain the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus. The merging processing unit is used to merge the signal values ​​and corresponding time information of the signals transmitted in each channel of the interface bus to obtain the start time, end time and corresponding data content of each read or write transmission within a preset time period. The performance analysis unit is used to calculate and analyze the performance data of the interface bus based on the results obtained through merging processing. The performance data includes at least: maximum latency, minimum latency, and average latency.

9. The system as described in claim 8, characterized in that, in: The waveform file acquisition unit includes a first script execution unit, which is used to execute an interface classification and statistics script to perform statistical processing on the contents of each channel in the interface bus in the fsdb waveform file. At each clock rise, the value of the handshake signal is judged. When the value of all handshake signals is high, the value and time information of each transmission signal in the channel are extracted. The merging processing unit includes a second script execution unit, which is used to execute a channel merging script, obtain the ID information of write transmission or read transmission based on the extracted values ​​and time information of each transmission signal in the channel, and use the ID information to match and merge the information of each channel to obtain the content of each write transmission or read transmission. The performance analysis unit includes a third script execution unit, which is used to execute a read / write performance analysis script, statistically obtain the amount of read / write data on the interface bus within a predetermined time period, compare the latency of each transmission, obtain the maximum and minimum latency and corresponding transmission information, and calculate the average latency.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 7.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 7.

Images