A data transmission method, device and storage medium

Abstract

Embodiments of the present application provide a data transmission method, device and storage medium, the method applied to FPGA comprises: receiving the descriptor trigger information sent by the central processing unit (CPU), the descriptor trigger information comprising descriptor storage address information; analyzing the descriptor trigger information, and reading a plurality of descriptors stored in the CPU according to the descriptor storage address information obtained by analysis, and storing a plurality of descriptors, the descriptor comprising data moving time, data source address information and data destination address information; analyzing the i th descriptor, and moving the data stored in the i th first target address in the CPU to the i th second target address in the FPGA according to the data moving time included in the i th descriptor obtained by analysis; i is an integer from 1 to n, and n represents the number of a plurality of descriptors. Therefore, embodiments of the present application can improve the accuracy of the DMA transmission mode between the CPU and the FPGA in time.

Description

Technical Field

[0001] This invention relates to the field of mobile communication technology, and in particular to a data transmission method, apparatus, and storage medium. Background Technology

[0002] In the communications industry, the Building Baseband Unit (BBU) is an important part of communication equipment, responsible for processing the baseband signals of mobile communications.

[0003] Within the BBU, there is extensive data interaction between the central processing unit (CPU) and the field-programmable gate array (FPGA). This data is transmitted via the high-speed serial computer component interconnect express (PCIe) interface, including uplink data reporting, downlink channel parameter transmission, and CPU parameter configuration. In downlink channel parameter transmission, because data transmission in the BBU is frame-based, and data scheduling and synchronization are in time slots, data transmission timing control is at the microsecond level. Therefore, in the FPGA, downlink channel parameter transmission has high requirements for time and transmission efficiency.

[0004] Currently, the primary method for PCIe data transfer between the CPU and FPGA is Direct Memory Access (DMA). Compared to the traditional CPU-directed data transfer method, DMA controller-based transfer does not require CPU involvement, significantly improving data transfer efficiency. However, DMA transfer time is controlled by CPU interrupts, resulting in insufficient timing precision.

[0005] As can be seen from the above, in the existing technology, the DMA transfer method between the CPU and FPGA has low accuracy in terms of time. Summary of the Invention

[0006] This invention provides a data transmission method, apparatus, and storage medium to solve the problem of low time accuracy in the DMA transmission method between CPU and FPGA in the prior art.

[0007] In a first aspect, embodiments of the present invention provide a data transmission method applied to a Field Programmable Gate Array (FPGA), the method comprising:

[0008] Receive descriptor trigger information sent by the central processing unit (CPU), wherein the descriptor trigger information includes descriptor storage address information;

[0009] The descriptor trigger information is parsed, and multiple descriptors stored in the CPU are read according to the descriptor storage address information obtained from the parsing, and the multiple descriptors are stored. The descriptor includes data migration time, data source address information and data destination address information.

[0010] Parse the i-th descriptor, and based on the data migration time included in the parsed i-th descriptor, move the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA;

[0011] Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

[0012] Optionally, after moving the data stored in the nth first target address in the CPU to the nth second target address in the FPGA based on the data migration time included in the parsed nth descriptor, the method further includes:

[0013] Delete the first to the nth descriptors.

[0014] Optionally, after parsing the descriptor trigger information, the method further includes:

[0015] Determine whether the remaining space in the storage space used to store the descriptor is less than a first preset threshold.

[0016] Specifically, if the remaining space is greater than or equal to the first preset threshold, the steps of reading multiple descriptors stored in the CPU and storing the multiple descriptors are performed based on the descriptor storage address information obtained by parsing.

[0017] Optionally, the method further includes:

[0018] If the remaining space is less than the first preset threshold, discard the currently parsed descriptor storage address information, start a preset timer, and discard the parsed descriptor storage address information within the timer's timeout period until the timer's timeout period reaches the preset time, then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

[0019] Optionally, the descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering information is valid;

[0020] Specifically, if the parsed first indication information indicates that the descriptor trigger information is valid, the step of reading multiple descriptors stored in the CPU based on the parsed descriptor storage address information is executed.

[0021] Optionally, the descriptor further includes a descriptor validity signal, which is used to indicate whether the descriptor is valid;

[0022] Specifically, if the parsed i-th descriptor includes a descriptor validity signal indicating that the i-th descriptor is valid, the step of moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data migration time included in the parsed i-th descriptor is executed.

[0023] Optionally, after moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA based on the data migration time included in the parsed i-th descriptor, the method further includes:

[0024] Convert the moved data into the first preset format.

[0025] Optionally, the method further includes at least one of the following steps:

[0026] Report data to the CPU;

[0027] Receive a Double Data Rate (DMR) synchronous dynamic random access memory (DDR) request sent by the CPU, and send data associated with the DDR access request to the CPU according to the DDR access request;

[0028] Receive configuration parameters sent by the CPU.

[0029] Secondly, embodiments of the present invention also provide a data transmission method applied to a central processing unit (CPU), the method comprising:

[0030] Send descriptor trigger information to the FPGA;

[0031] The descriptor triggering information includes descriptor storage address information, and the descriptor triggering information is used to instruct the FPGA to read multiple descriptors stored in the CPU according to the descriptor storage address information.

[0032] Optionally, sending descriptor triggering information to the FPAG includes:

[0033] The descriptor trigger information is sent to the FPAG at preset time intervals.

[0034] Thirdly, embodiments of the present invention provide a data transmission device applied to a field-programmable gate array (FPGA), the device comprising:

[0035] An interface conversion module is used to receive descriptor trigger information sent by a central processing unit (CPU), wherein the descriptor trigger information includes descriptor storage address information;

[0036] The descriptor trigger information configuration module is used to parse the descriptor trigger information to obtain the descriptor storage address information;

[0037] The descriptor reading module is used to read multiple descriptors stored in the CPU based on the descriptor storage address information obtained by the descriptor trigger information configuration module.

[0038] A descriptor caching module is used to store the plurality of descriptors read by the read descriptor module, wherein the descriptor includes data migration time, data source address information and data destination address information;

[0039] The system includes a Direct Memory Access (DMA) control module and a data transfer module. The DMA control module receives the i-th descriptor sent by the descriptor cache module, parses the i-th descriptor, and controls the data transfer module to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA based on the data transfer time included in the parsed i-th descriptor.

[0040] Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

[0041] Optionally, the DMA control module, based on the data transfer time included in the parsed nth descriptor, controls the data transfer module to transfer the data stored in the nth first target address in the CPU to the nth second target address in the FPGA. The descriptor caching module is further configured to:

[0042] Delete the first to the nth descriptors.

[0043] Optionally, after receiving the descriptor storage address information parsed by the descriptor trigger information configuration module, the descriptor reading module is further configured to: determine whether the remaining space of the storage space used to store the descriptor is less than a first preset threshold.

[0044] Specifically, when the remaining space is greater than or equal to the first preset threshold, the descriptor reading module executes the step of reading multiple descriptors stored in the CPU by parsing the descriptor storage address information obtained by the descriptor trigger information configuration module.

[0045] Optionally, the descriptor reading module is further configured to: discard the descriptor storage address information currently received by the descriptor trigger information configuration module when the remaining space is less than the first preset threshold, start a pre-set timer, and discard the descriptor storage address information received by the descriptor trigger information configuration module within the timer's timing period, until the timer's timing period reaches the preset time, and then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

[0046] Optionally, the descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering signal is valid;

[0047] Wherein, when the first indication information obtained by parsing indicates that the descriptor trigger information is valid, the descriptor trigger information configuration module sends the parsed descriptor storage address information to the read descriptor module.

[0048] Optionally, the descriptor further includes a descriptor validity signal, which is used to indicate whether the descriptor is valid;

[0049] Wherein, when the parsed descriptor valid signal of the i-th descriptor indicates that the i-th descriptor is valid, the DMA control module executes the step of controlling the data transfer module to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data transfer time included in the parsed i-th descriptor.

[0050] Optionally, the device further includes:

[0051] The format conversion module is used to convert the moved data into a first preset format.

[0052] Optionally, the device further includes at least one of the following modules:

[0053] The reporting module is used to report data to the CPU;

[0054] The DDR module is used to receive a Double Data Rate (DMR) synchronous dynamic random access memory (DDR) request sent by the CPU, and to send data associated with the DDR access request to the CPU according to the DDR access request;

[0055] The memory mapping module is used to receive configuration parameters sent by the CPU.

[0056] Fourthly, embodiments of the present invention provide a data transmission device applied to a central processing unit (CPU), the device comprising:

[0057] The descriptor trigger information sending module is used to send descriptor trigger information to the field programmable gate array (FPGA).

[0058] The descriptor triggering information includes descriptor storage address information, and the descriptor triggering information is used to instruct the FPGA to read multiple descriptors stored in the CPU according to the descriptor storage address information.

[0059] Optionally, the descriptor trigger information sending module is specifically used for:

[0060] The descriptor trigger information is sent to the FPAG at preset time intervals.

[0061] Fifthly, embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing the processor to perform the method described in the first aspect or the method described in the second aspect.

[0062] In this embodiment of the invention, after the FPGA receives the descriptor trigger information sent by the CPU, it can parse the descriptor trigger information to obtain the descriptor storage address information included in the descriptor trigger information. Then, based on the descriptor storage address information, it reads the corresponding descriptor from the CPU, parses the read descriptor, obtains the data migration time, data source address information and data destination address information included in the descriptor, and migrates the data in the CPU to the FPGA based on the data migration time, data source address information and data destination address information.

[0063] Therefore, in the embodiments of the present invention, the CPU actively sends descriptor trigger information, triggering the FPGA to actively read the descriptor and parse its contents. Data is then moved according to the descriptor requirements. Furthermore, time information is added to the descriptor to control the start and end times of the data movement, making the data movement operation time-controllable. Thus, in the embodiments of the present invention, the CPU notifies the FPGA to read the descriptor, and the FPGA controls the time for data movement based on the descriptor. Since the FPGA has high time accuracy, the embodiments of the present invention can improve the time accuracy of the DMA transfer method between the CPU and the FPGA. Attached Figure Description

[0064] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0065] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present invention;

[0066] Figure 2 A flowchart of another data transmission method provided in an embodiment of the present invention;

[0067] Figure 3 A structural block diagram of a data transmission device provided in an embodiment of the present invention;

[0068] Figure 4 A structural block diagram of another data transmission device provided in an embodiment of the present invention;

[0069] Figure 5 This is a structural block diagram of a specific implementation of the data transmission system in this invention.

[0070] Figure 6 This is a structural block diagram of the DMA module in an embodiment of the present invention;

[0071] Figure 7 A schematic diagram of the data migration process in an embodiment of the present invention;

[0072] Figure 8 A schematic diagram of the state machine of the DMA control module in this embodiment of the invention. Detailed Implementation

[0073] In this embodiment of the invention, the term "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0074] In this embodiment of the invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0075] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0076] This invention provides a data transmission method, apparatus, and storage medium to solve the problem of low time accuracy in the DMA transmission method between CPU and FPGA in the prior art.

[0077] In this embodiment of the invention, the CPU and FPGA can be located in the terminal device or in the network device.

[0078] Furthermore, the method and apparatus are based on the same concept of the application. Since the methods and apparatus solve problems in similar ways, the implementation of the apparatus and methods can refer to each other, and the repeated parts will not be described again.

[0079] Furthermore, the technical solutions provided in this invention can be applied to various systems, especially 5G systems. For example, applicable systems include Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS), Long Term Evolution (LTE), LTE Frequency Division Duplex (FDD), LTE Time Division Duplex (TDD), Long Term Evolution Advanced (LTE-A), Universal Mobile Telecommunications System (UMTS), Worldwide Interoperability for Microwave Access (WiMAX), and 5G New Radio (NR). All of these systems include terminal equipment and network equipment. The systems may also include a core network component, such as Evolved Packet System (EPS) and 5G systems (5GS).

[0080] The terminal devices involved in these embodiments of the invention can be devices that provide voice and / or data connectivity to users, handheld devices with wireless connectivity, or other processing devices connected to a wireless modem. The names of the terminal devices may differ in different systems; for example, in a 5G system, a terminal device can be called User Equipment (UE). Wireless terminal devices can communicate with one or more core networks (CNs) via a Radio Access Network (RAN). Wireless terminal devices can be mobile terminal devices, such as mobile phones (or "cellular" phones) and computers with mobile terminal devices, for example, portable, pocket-sized, handheld, computer-embedded, or vehicle-mounted mobile devices that exchange voice and / or data with the RAN. Examples include Personal Communication Service (PCS) phones, cordless phones, Session Initiated Protocol (SIP) phones, Wireless Local Loop (WLL) stations, and Personal Digital Assistants (PDAs). Wireless terminal equipment can also be referred to as a system, subscriber unit, subscriber station, mobile station, mobile station, remote station, access point, remote terminal, access terminal, user terminal, user agent, or user device, but is not limited to these terms in this embodiment of the invention.

[0081] The network device involved in this embodiment of the invention can be a base station, which may include multiple cells providing services to terminals. Depending on the specific application, the base station may also be called an access point, or a device in the access network that communicates with wireless terminal devices through one or more sectors on the air interface, or other names. The network device can be used to exchange received air frames with Internet Protocol (IP) packets, acting as a router between the wireless terminal device and the rest of the access network, where the rest of the access network may include an Internet Protocol (IP) communication network. The network device can also coordinate the attribute management of the air interface. For example, the network equipment involved in the embodiments of this invention can be a base transceiver station (BTS) in a Global System for Mobile communications (GSM) or Code Division Multiple Access (CDMA) system, a NodeB in a wide-band Code Division Multiple Access (WCDMA) system, an evolved Node B (eNB or e-NodeB) in a long term evolution (LTE) system, a 5G base station (gNB) in a next generation system, a Home evolved Node B (HeNB), a relay node, a femto, a pico, etc., and is not limited in the embodiments of this invention. In some network structures, the network equipment may include centralized unit (CU) nodes and distributed unit (DU) nodes, and the centralized unit and distributed unit may also be geographically separated.

[0082] Network devices and terminal devices can each use one or more antennas for multiple-input multiple-output (MIMO) transmission. MIMO transmission can be single-user MIMO (SU-MIMO) or multiple-user MIMO (MU-MIMO). Depending on the configuration and number of antenna combinations, MIMO transmission can be 2D-MIMO, 3D-MIMO, FD-MIMO, or massive-MIMO, and can also be diversity transmission, precoding transmission, or beamforming transmission, etc.

[0083] Figure 1 The diagram shows a flowchart of a data transmission method according to an embodiment of the present invention. This method can be applied to an FPGA and includes the following steps 101 to 103:

[0084] Step 101: Receive descriptor trigger information sent by the central processing unit (CPU).

[0085] The descriptor trigger information (also known as descriptor trigger) includes descriptor storage address information.

[0086] Furthermore, in the embodiments of the present invention, data transfer between the CPU and the FPGA adopts DMA (Distributed Mapping) migration. Due to the characteristics of DMA migration, the storage addresses of all descriptors migrated by each descriptor trigger information are contiguous. Therefore, the aforementioned descriptor storage address information may include a first starting address (also referred to as a first base address) and the number of descriptors. That is, by indicating the first starting address and the number of descriptors in the descriptor trigger information, the storage addresses of all descriptors associated with the descriptor trigger information can be obtained.

[0087] Furthermore, in embodiments of the present invention, the CPU can send descriptor trigger information to the FPGA at preset time intervals.

[0088] Step 102: Parse the descriptor trigger information, and according to the descriptor storage address information obtained from the parsing, read the multiple descriptors stored in the CPU and store the multiple descriptors.

[0089] In an embodiment of the present invention, one descriptor triggering information is associated with multiple descriptors, that is, one descriptor triggering information is used to instruct the FPGA to move multiple descriptors to the CPU.

[0090] Optionally, the descriptor relocation is 512-bit aligned, and the amount of data relocated is an integer multiple of 512 bits. Since each descriptor is 128 bits, the amount of descriptors relocated is 4 or an integer multiple of 4.

[0091] Optionally, a descriptor trigger message must be at least one length, and a descriptor trigger message of one length is used to move 4 descriptors. Therefore, a descriptor trigger message is used to move k*4 descriptors, where k is a positive integer.

[0092] Step 103: Parse the i-th descriptor, and according to the data migration time included in the parsed i-th descriptor, move the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA.

[0093] Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

[0094] In addition, the descriptor includes data migration time, data source address information, and data destination address information, and the data migration time includes the start time and end time of data migration.

[0095] Furthermore, in the embodiments of the present invention, data transfer between the CPU and the FPGA adopts DMA (Distributed Mapping) migration. Due to the characteristics of DMA migration, the storage addresses of all data migrated by each descriptor are contiguous. Therefore, the aforementioned data source address information may include a second starting address (also known as a second base address) and data length. That is, by indicating the second starting address and data length of the data in the descriptor, the storage addresses of all data associated with the descriptor can be obtained.

[0096] As can be seen from steps 102 to 103, the FPGA can store the descriptors to be moved one by one in sequence, and wait for the data start time indicated by each descriptor. Within the required time, the data is moved from the source address to the destination address until the data of all descriptors is moved.

[0097] In summary, according to steps 101 to 103 above, in this embodiment of the invention, after the FPGA receives the descriptor trigger information sent by the CPU, it can parse the descriptor trigger information to obtain the descriptor storage address information included in the descriptor trigger information. Then, based on the descriptor storage address information, it reads the corresponding descriptor from the CPU, parses the read descriptor, obtains the data migration time, data source address information, and data destination address information included in the descriptor, and migrates the data in the CPU to the FPGA based on the data migration time, data source address information, and data destination address information.

[0098] Therefore, in the embodiments of the present invention, the CPU actively sends descriptor trigger information to trigger the FPGA to actively read the descriptor and parse the descriptor content, thereby performing data transfer according to the descriptor requirements. Furthermore, time information is added to the descriptor to control the start and end times of data transfer, making the data transfer operation controllable in time.

[0099] In existing technologies, there is no strict control over the data transfer time. Generally, the CPU actively sends descriptors based on the time of interrupts, etc., and the FPGA immediately performs DMA operation after receiving the descriptor without controlling the data transfer time. However, since the data of each channel on the BBU has strict time requirements, generally at the microsecond level, this method is generally not accurate enough.

[0100] In the embodiments of the present invention, the CPU notifies the FPGA to read the descriptor, and the FPGA controls the time for data transfer based on the descriptor. Since the FPGA has high time accuracy, the embodiments of the present invention can improve the time accuracy of the DMA transfer method between the CPU and the FPGA.

[0101] In addition, since the content of the descriptor in each time slot remains basically unchanged in practical applications, these descriptors are fixedly stored in a memory space of the CPU, and there are a large number of descriptors. If the CPU actively sends descriptors, it will occupy more CPU resources and affect the data transmission rate. However, the embodiments of the present invention use the descriptor triggering information to reduce the CPU utilization rate, thereby improving the data transmission rate.

[0102] Optionally, after moving the data stored in the nth first target address in the CPU to the nth second target address in the FPGA based on the data migration time included in the parsed nth descriptor, the method further includes:

[0103] Delete the first to the nth descriptors.

[0104] Therefore, in the embodiments of the present invention, when the data migration is completed for the last descriptor among all descriptors associated with a descriptor trigger information, all descriptors associated with that descriptor trigger information are uniformly deleted.

[0105] Specifically, when the CPU sends a descriptor trigger message to the FPGA at preset time intervals, the FPGA parses the descriptor trigger message, reads the descriptor from the CPU according to the descriptor storage address information obtained from the parsing, and stores the read descriptor. At the same time, it also parses the stored descriptor, performs data migration according to the data migration time and data source address information obtained from the parsing, and deletes all descriptors associated with a descriptor trigger after all data associated with a descriptor trigger is migrated. In this way, the number of descriptors stored in the FPGA is dynamically changing.

[0106] Optionally, after parsing the descriptor trigger information, the method further includes:

[0107] Determine whether the remaining space in the storage space used to store the descriptor is less than a first preset threshold;

[0108] Specifically, if the remaining space is greater than or equal to the first preset threshold, the steps of reading multiple descriptors stored in the CPU based on the parsed descriptor storage address information and storing the multiple descriptors are performed. Optionally, the method further includes:

[0109] If the remaining space is less than the first preset threshold, discard the currently parsed descriptor storage address information, start a preset timer, and discard the parsed descriptor storage address information within the timer's timeout period until the timer's timeout period reaches the preset time, then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

[0110] In one embodiment of the present invention, time information is added to the descriptor, which imposes strict requirements on the data transmission time. If the descriptor trigger information is sent at an abnormal time (such as incorrect data migration time in the descriptor), it may cause the descriptor to remain in a waiting state for a long time due to the failure to reach the start migration time, resulting in a large accumulation of descriptors. Alternatively, if a descriptor needs to migrate a large amount of data, resulting in a long data migration time, it may also lead to a large accumulation of descriptors.

[0111] The descriptors are processed one by one in the order they are moved back. Therefore, when processing subsequent normal descriptors, the accumulation of previous descriptors will cause a time delay, thus keeping the entire data migration in an abnormal state.

[0112] Therefore, embodiments of the present invention can also add a timeout protection mechanism. That is, after parsing a descriptor trigger information, it is determined whether the remaining space of the storage space currently used to store the descriptor is less than a first preset threshold. If the current remaining space is greater than or equal to the first preset threshold, it means that the number of currently stored descriptors has not yet reached the preset maximum value, and the descriptor trigger information can be received normally. The received descriptor trigger information is parsed, and the descriptor is moved according to the descriptor storage address information obtained by parsing. If the current remaining space is less than the first preset threshold, it means that the number of currently stored descriptors has reached the preset maximum value, thereby triggering the protection mechanism.

[0113] The protection mechanism is as follows: directly discard the descriptor storage address information obtained by parsing the descriptor trigger information received this time, start a pre-set timer, and discard the descriptor storage address information obtained after parsing the descriptor trigger information within the timer's time period, until the protection time ends (i.e. until the timer reaches the preset time), and then re-determine whether the protection mechanism conditions are met.

[0114] The number of descriptors (or the remaining space in the storage space used to store descriptors) and the timing period of the timer can be set according to actual needs. For example, the timing period of the timer is in units of 10 microseconds.

[0115] Optionally, the descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering information is valid;

[0116] Specifically, if the parsed first indication information indicates that the descriptor trigger information is valid, the step of reading multiple descriptors stored in the CPU based on the parsed descriptor storage address information is executed.

[0117] If the first indication information obtained through parsing indicates that the descriptor trigger information is invalid, the currently parsed descriptor storage address information is discarded.

[0118] Specifically, each descriptor trigger information can be defined as 64 bits. For example, in the case of a 24-core CPU, 24 sets of register addresses can be opened to store the descriptor trigger information. The definitions of each bit are shown in Table 1.

[0119] Table 1 Descriptor Trigger Information Definition

[0120]

[0121] In Table 1, the “offset address” is used to indicate that the information is descriptor trigger information; Bit[8:0] in the high 32 bits and the low 32 bits together represent the first starting address of the descriptor (i.e., the first base address), Bit[19:9] represents the number of descriptors, and Bit

[31] represents the above first indication information, that is, whether the descriptor trigger information is valid. A value of 1 indicates that the descriptor trigger information is valid; a value of 0 indicates that the descriptor trigger information is invalid.

[0122] Optionally, the descriptor further includes a descriptor validity signal, which is used to indicate whether the descriptor is valid;

[0123] Specifically, if the parsed i-th descriptor includes a descriptor validity signal indicating that the i-th descriptor is valid, the step of moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data migration time included in the parsed i-th descriptor is executed.

[0124] If the parsed i-th descriptor contains a valid descriptor signal indicating that the i-th descriptor is invalid, the data migration time data source address information and data destination address information contained in the parsed i-th descriptor shall be discarded.

[0125] In an embodiment of the present invention, the FPGA moves data to the CPU according to the descriptor. In addition to the source address, destination address and data length, the data move start time and end time are also included. In this way, the DMA operation can only realize data move within the start time and end time. In addition, the descriptor can also include a descriptor validity signal, which indicates whether the descriptor is valid, so that the DMA only processes valid descriptors and discards invalid descriptors.

[0126] Specifically, the descriptor can be defined as 128 bits of data, and the specific definitions of each field are shown in Table 2:

[0127] Table 2. Definitions of each field in the descriptor

[0128]

[0129] The specific explanations of each field in Table 2 are as follows:

[0130] SRC_ADDR_LSB: Indicates the lower 32 bits of the source address, in 64-byte units, and data must be moved in 64-byte alignment; SRC_ADDR_MSB: Indicates the upper 9 bits of the source address;

[0131] DEST_ADDR_LSB: Indicates the lower 32 bits of the destination address, in 64-byte units, and data must be moved in 64-byte alignment; DEST_ADDR_MSB: Indicates the upper 9 bits of the destination address;

[0132] HFE: Indicates the odd or even half-frame number where the data transfer ended, 0 represents an even half-frame and 1 represents an odd half-frame;

[0133] HFS: Indicates the odd or even half-frame number where the data migration begins, 0 represents an even half-frame and 1 represents an odd half-frame;

[0134] TST: Indicates the start time of data transfer, in units of 10US, and in range of one and a half frames. 511 means immediate transmission.

[0135] TET: The end time of data migration, in units of 10US, with a range of one and a half frames. It is used for data migration timeout verification. 511 means no verification.

[0136] INFO: Indicates data-as-you-go information, that is, the attribute information of the data;

[0137] VLD: A valid descriptor identifier; 0 indicates invalid, and 1 indicates valid.

[0138] END: The descriptor list end marker, used to indicate whether the descriptor is at the end of the list;

[0139] LEN: Length of data to be moved, in units of 64 bytes.

[0140] Optionally, after moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA based on the data migration time included in the parsed i-th descriptor, the method further includes:

[0141] Convert the moved data into the first preset format.

[0142] The first preset format is, for example, a random access memory (RAM) interface format.

[0143] Therefore, in the embodiments of the present invention, after the FPGA moves data from the CPU, the moved data can be converted into a first preset format.

[0144] Existing DMA designs are relatively simple in function, generally lacking interface conversion capabilities. Furthermore, the data format directly output by DMA may be inconvenient for subsequent module data processing. In the embodiments of this invention, to facilitate data storage and use by other modules, the output data format is converted during DMA data transfer. For example, the output data is converted from AXI4 format to RAM interface format, facilitating further data processing. Here, AXI stands for Advanced Scalable Interface.

[0145] Optionally, the method further includes at least one of the following steps:

[0146] Report data to the CPU;

[0147] Receive a Double Data Rate (DDR) access request sent by the CPU, and send data associated with the DDR access request to the CPU according to the DDR access request;

[0148] Receive configuration parameters sent by the CPU.

[0149] There may be other requirements for data interaction between the FPGA and the CPU on the BBU, such as FPGA data reporting, CPU access to the FPGA-side DDR, and CPU actively configuring a small number of parameters to the FPGA. Therefore, in the embodiments of the present invention, these functions can be added as needed by adding an AXI interface to the FPGA.

[0150] Figure 2 The diagram illustrates a data transmission method according to an embodiment of the present invention. This method can be applied to a CPU and includes the following step 201:

[0151] Step 201: Send descriptor trigger information to the Field Programmable Gate Array (FPGA).

[0152] The descriptor triggering information includes descriptor storage address information, and the descriptor triggering information is used to instruct the FPGA to read multiple descriptors stored in the CPU according to the descriptor storage address information.

[0153] The descriptor includes data migration time, data source address information, and data destination address information. The data migration time includes the start and end times of the data migration.

[0154] Furthermore, in the embodiments of the present invention, the data transfer between the CPU and the FPGA adopts the DMA transfer method, and due to the characteristics of DMA transfer, the storage addresses of all descriptors that trigger information transfer for each descriptor are contiguous, and the storage addresses of all data transferred by each descriptor are contiguous.

[0155] Therefore, the aforementioned descriptor storage address information may include a first starting address (also known as a first base address) and the number of descriptors. That is, by indicating the first starting address and the number of descriptors in the descriptor trigger information, the storage addresses of all descriptors associated with the descriptor trigger information can be obtained. The aforementioned data source address information may include a second starting address (also known as a second base address) and the data length. That is, by indicating the second starting address and the data length in the descriptor, the storage addresses of all data associated with the descriptor can be obtained.

[0156] In addition, after the FPGA receives the descriptor trigger information sent by the CPU, it parses the descriptor trigger information, reads multiple descriptors stored in the CPU according to the descriptor storage address information obtained from the parsing, stores the read descriptors, thereby parsing each descriptor, and moves the data in the CPU to the FPGA according to the data migration time, data source address information and data destination address information included in each descriptor obtained from the parsing.

[0157] Therefore, in the embodiments of the present invention, the CPU actively sends descriptor trigger information to trigger the FPGA to actively read the descriptor and parse the descriptor content, thereby performing data transfer according to the descriptor requirements. Furthermore, time information is added to the descriptor to control the start and end times of data transfer, making the data transfer operation controllable in time.

[0158] In existing technologies, there is no strict control over the data transfer time. Generally, the CPU actively sends descriptors based on the time of interrupts, etc., and the FPGA immediately performs DMA operation after receiving the descriptor without controlling the data transfer time. However, since the data of each channel on the BBU has strict time requirements, generally at the microsecond level, this method is generally not accurate enough.

[0159] In the embodiments of the present invention, the CPU notifies the FPGA to read the descriptor, and the time for the FPGA to perform data transfer based on the descriptor is controlled by the FPGA. The FPGA has high time accuracy. Therefore, the embodiments of the present invention can improve the time accuracy of the DMA transfer method between the CPU and the FPGA.

[0160] In addition, since the content of the descriptor in each time slot remains basically unchanged in practical applications, these descriptors are fixedly stored in a memory space of the CPU, and there are a large number of descriptors. If the CPU actively sends descriptors, it will occupy more CPU resources and affect the data transmission rate. However, the embodiments of the present invention use the descriptor triggering information to reduce the CPU utilization rate, thereby improving the data transmission rate.

[0161] Optionally, sending descriptor triggering information to the FPAG includes:

[0162] The descriptor trigger information is sent to the FPAG at preset time intervals.

[0163] The preset time interval can be configured according to the actual application scenario.

[0164] The data transmission method provided by the embodiments of the present invention has been described above. The data transmission device provided by the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0165] like Figure 3 As shown, an embodiment of the present invention provides a data processing apparatus applied to an FPGA, the apparatus comprising:

[0166] The interface conversion module 301 is used to receive descriptor trigger information sent by the central processing unit (CPU), wherein the descriptor trigger information includes descriptor storage address information;

[0167] The descriptor trigger information configuration module 302 is used to parse the descriptor trigger information and obtain the descriptor storage address information;

[0168] The descriptor reading module 303 is used to read multiple descriptors stored in the CPU based on the descriptor storage address information obtained by the descriptor triggering information configuration module 302.

[0169] The descriptor cache module 304 is used to store the plurality of descriptors read by the read descriptor module 303, wherein the descriptor includes data migration time, data source address information and data destination address information;

[0170] The system includes a Direct Memory Access (DMA) control module 305 and a data transfer module 306. The DMA control module 305 receives the i-th descriptor sent by the descriptor cache module 304, parses the i-th descriptor, and controls the data transfer module 306 to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA based on the data transfer time included in the parsed i-th descriptor.

[0171] Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

[0172] Optionally, the DMA control module, based on the data transfer time included in the parsed nth descriptor, controls the data transfer module to transfer the data stored in the nth first target address in the CPU to the nth second target address in the FPGA. The descriptor caching module is further configured to:

[0173] Delete the first to the nth descriptors.

[0174] Optionally, after receiving the descriptor storage address information parsed by the descriptor trigger information configuration module, the descriptor reading module is further configured to: determine whether the remaining space of the storage space used to store the descriptor is less than a first preset threshold.

[0175] Among them, the read descriptor module

[0176] If the remaining space is greater than or equal to the first preset threshold, the step of reading multiple descriptors stored in the CPU is executed, based on the descriptor storage address information parsed by the descriptor trigger information configuration module.

[0177] Optionally, the descriptor reading module is further configured to: discard the descriptor storage address information currently received by the descriptor trigger information configuration module when the remaining space is less than the first preset threshold, start a pre-set timer, and discard the descriptor storage address information received by the descriptor trigger information configuration module within the timer's timing period, until the timer's timing period reaches the preset time, and then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

[0178] Optionally, the descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering signal is valid;

[0179] Among them, the descriptor trigger information configuration module

[0180] If the parsed first indication information indicates that the descriptor trigger information is valid, the parsed descriptor storage address information is sent to the read descriptor module.

[0181] Optionally, the descriptor further includes a descriptor validity signal, which is used to indicate whether the descriptor is valid;

[0182] Wherein, when the parsed descriptor valid signal of the i-th descriptor indicates that the i-th descriptor is valid, the DMA control module executes the step of controlling the data transfer module to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data transfer time included in the parsed i-th descriptor.

[0183] Optionally, the device further includes:

[0184] The format conversion module is used to convert the moved data into a first preset format.

[0185] Optionally, the device further includes at least one of the following modules:

[0186] The reporting module is used to report data to the CPU;

[0187] The DDR module is used to receive a Double Data Rate (DMR) synchronous dynamic random access memory (DDR) request sent by the CPU, and to send data associated with the DDR access request to the CPU according to the DDR access request;

[0188] The memory mapping module is used to receive configuration parameters sent by the CPU.

[0189] like Figure 4 As shown, an embodiment of the present invention provides a data transmission device applied to a central processing unit (CPU), the device comprising:

[0190] The descriptor trigger information sending module 401 is used to send descriptor trigger information to the field programmable gate array (FPGA).

[0191] The descriptor triggering information includes descriptor storage address information, and the descriptor triggering information is used to instruct the FPGA to read multiple descriptors stored in the CPU according to the descriptor storage address information.

[0192] Optionally, the descriptor trigger information sending module 401 is specifically used for:

[0193] The descriptor trigger information is sent to the FPAG at preset time intervals.

[0194] It should be noted that the division of units in the embodiments of this invention is illustrative and only represents one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0195] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0196] It should be noted that the apparatus provided in this embodiment of the invention can implement all the method steps implemented in the above method embodiment and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.

[0197] Embodiments of the present invention also provide a data transmission system, including the data transmission device applied to an FPGA and the data transmission device applied to a CPU as described above.

[0198] Optionally, the specific implementation of the data transmission system of this embodiment of the invention may be as follows:

[0199] like Figure 5 As shown, the data transmission system includes an FPGA and a CPU. The FPGA includes a BBU, and the BBU includes a PCIe IP core, a first data interconnect module, a second data interconnect module, a DMA module, a channel processing unit, a clock module, at least one reporting module, a format conversion module, and a DDR module.

[0200] The CPU and PCIe IP core are connected via an X16, X8, or X4 interface. The PCIe IP core is connected to a master interface (AXI_M) and a slave interface (AXI_S) of the first data interconnect module, respectively.

[0201] In addition, the DMA module is connected to the read descriptor interface (AXI_SG_R) and read data interface (AXI_DATA) of the first data interconnect module, respectively. The AXI interface of the first data interconnect module is connected to the format conversion module, which in turn is connected to the DMA write data interface (MEM_W) of the channel processing unit. The second data interconnect module is connected to the AXI interface of the first data interconnect module, and its AXI_Lite interface is connected to the AXI_Lite interface of the DMA module. The AXI_Lite interface transmits the descriptor trigger and configuration parameters sent by the CPU. The DMA distinguishes between descriptor triggers and configuration parameters based on the address. Therefore, through the DMA module, PCIe IP core, first data interconnect module, second data interconnect module, format conversion module, and channel processing unit, a DMA transfer path is formed between the CPU and the FPGA (the specific DMA transfer process will be described in detail later).

[0202] The reporting module is connected to the write data interface (AXI_W) of the first data interconnect module. In this way, a channel for FPGA to report data to CPU is formed through the reporting module, the first data interconnect module, and the PCIE IP core.

[0203] The DDR module is connected to the AXI interface of the first data interconnect module. In this way, a channel for the CPU to access the FPGA's DDR is formed through the DDR module, the first data interconnect module, and the PCIE IP core.

[0204] The AXI_Lite interface of the memory mapping module is connected to the AXI_Lite interface of the second interconnect module. The second data interconnect module is also connected to the AXI of the first data interconnect module, thus forming a channel for the CPU to configure parameters to the FPGA.

[0205] In addition, the aforementioned clock module is connected to the DMA module to perform clock control on the DMA module.

[0206] As can be seen from the above, in the embodiments of the present invention, the FPGA's BBU mainly includes a PCIE part, a DMA part, and a data format conversion part.

[0207] Firstly, the PCIe section consists of PCIe IP cores and interconnect modules (i.e., interconnect IP cores), primarily responsible for PCIe communication with the CPU and arbitration of data before it enters the PCIe interface. Specifically, for simplicity and stability, the PCIe section employs an IP core design, with the PCIe IP core using an AXI bridge mode, and the interconnect module arbitrating data input to the master and slave interfaces of the PCIe IP core.

[0208] Secondly, the DMA section is used to implement functions such as descriptor trigger parsing, descriptor reading, descriptor parsing, and controlling PCIe to perform data transfer. The timing information for descriptor timing is provided by the clock module in 10µs increments for counting and frame header signals.

[0209] Specifically, such as Figure 6 As shown, the above DMA module includes an interface conversion module, a descriptor trigger information configuration module, a descriptor moving module, a DMA control module, a data moving module, and a time control module. The descriptor moving module includes a logic judgment module, a descriptor read module, and a descriptor cache module.

[0210] The CPU-sent trigger descriptor is transmitted to the DMA module via the PCIe IP core, the first data interconnect module, and the second data interconnect module. It is then received by the interface conversion module and its format is converted. Since the CPU-sent trigger descriptor outputs data in the AXI4_Lite interface format, to facilitate parsing, it is first converted to RAM interface format data in the interface conversion module before being input to the trigger information configuration module.

[0211] The descriptor trigger information configuration module parses the descriptor trigger and sends the parsing result (including descriptor storage address information) to the logic judgment module. The logic judgment module determines whether the descriptor trigger has errors such as length errors (e.g., zeros) and whether it is currently in a protected state (this protected state will be explained in detail below), thus determining whether the descriptor needs to be read. Furthermore, when multiple descriptor triggers are received consecutively, this module has a certain caching capability to prevent descriptor trigger loss due to insufficient time to move the descriptors.

[0212] The descriptor moving module, based on the instructions of the logic judgment module and the parsing results, reads the descriptor from the CPU through the first data interconnect module, the path between the PCIe IP core and the CPU, and sends the read descriptor to the descriptor cache module for storage.

[0213] While caching the received descriptors, the descriptor caching module also synchronously sends the descriptors to the DMA control module. The DMA control module parses the received descriptors to obtain the data transfer time, data source address information, and data destination address information. Then, under the control of the time control module, the data transfer module moves the data from the CPU to the FPGA according to the data transfer time and the data source address information and the data destination address information, through the first data interconnect module, the path between the PCIe IP core and the CPU.

[0214] It should be noted that 24 sets of register addresses can be opened in the descriptor trigger information configuration module mentioned above to store descriptor triggers, for example... Figure 6 In this context, DDPi(LSB) represents the lower 32-bit memory address of a descriptor trigger, and DDPi(HSB) represents the higher 32-bit memory address of a descriptor trigger. In other words, DDPi(LSB) and DDPi(HSB) represent the memory address of a descriptor trigger, and i takes an integer from 0 to 23.

[0215] Therefore, the data migration process involved in the embodiments of the present invention is as follows: Figure 7 As shown, it is mainly divided into the following four stages:

[0216] The first stage: The CPU generates a descriptor and its corresponding data at a specific address. Due to the DMA transfer characteristics, all descriptor addresses moved by each descriptor trigger are consecutive, and the data addresses moved by the same descriptor are also consecutive.

[0217] Second phase: The CPU sends the descriptor trigger within the required time.

[0218] The third stage: DMA control in the FPGA resolves the descriptor trigger, moves the descriptor, and caches it;

[0219] The fourth stage: The DMA module in the FPGA will move the data of the descriptors one by one in sequence, wait for the data start time of each descriptor, and move the data from the source address to the destination address within the required time until the data of all descriptors is moved.

[0220] The aforementioned DMA control module implements the DMA control function, completing the entire data transfer control process. Its state machine transition diagram is as follows: Figure 8 As shown, it includes the following:

[0221] 1. Start reading the descriptor list, that is, the DMA control module starts receiving descriptors sent by the descriptor buffer module;

[0222] 2. Generate a data transfer command based on the descriptor, wherein the data transfer command is sent by the DMA control module to the data transfer module;

[0223] 3. Control the timing of sending data migration commands based on the data migration time included in the descriptor;

[0224] 4. Verify that the linked list relocation operation is complete. That is, the DMA control module determines whether the received descriptor is the last descriptor in the descriptor associated with the current descriptor trigger (i.e., the descriptor whose address is represented by the descriptor address information included in the descriptor trigger).

[0225] In addition, the aforementioned data migration module utilizes existing IP cores to achieve data migration, completes high-throughput data transmission between AXI4 memory maps, supports 4KB address boundary protection, and automatic burst partitioning.

[0226] Thirdly, the data format conversion part is implemented by the format conversion module. That is, through the first data interconnection module, the data moved by the data transfer module is sent to the format conversion module, which converts the transferred data from the AXI4 format to the RAM interface format, and then sends the converted data to the channel processing unit for storage.

[0227] In addition to supporting DMA functionality, the PCIe IP cores in the BBU can also be supplemented with other AXI interfaces as needed:

[0228] For example, data reported by the reporting module is reported to the CPU via the PCIe IP core;

[0229] A DDR module is added to facilitate CPU reading and writing to the FPGA's DDR, enabling functions such as stub placement and location. Stub placement refers to sending stub files from the CPU to the FPGA's DDR via the PCIe IP core for verifying DDR functionality. Location function refers to writing data and status information retrieved by the DMA module, or other node data that can be used for location, to the DDR via data capture. By reading the data in the DDR, it is possible to locate whether there is any abnormal information.

[0230] Add a "memory mapping module" to support the direct configuration of a small number of CPU parameters into the FPGA's memory mapping module for parsing;

[0231] Therefore, in the embodiments of the present invention, the interface has high flexibility, that is, the number of AXI interfaces can be flexibly increased or decreased as needed to achieve various different functions.

[0232] Furthermore, embodiments of the present invention may also include a DMA anomaly recovery and protection mechanism, as described below:

[0233] The aforementioned descriptor cache module, while synchronously receiving descriptors read from the CPU by the read descriptor module and storing the received descriptors, also synchronously sends the descriptors one by one to the DMA control module for parsing according to the descriptor transfer order (that is, when the DMA control module controls the data transfer module to complete the data transfer associated with a descriptor, the descriptor cache module sends the next descriptor to the DMA control module). When the data associated with the last descriptor among all the descriptors associated with a descriptor trigger is transferred, all descriptors associated with that descriptor trigger sent to the DMA control module are deleted. In this way, the number of descriptors stored in the descriptor cache module is dynamically changing.

[0234] In one embodiment of the present invention, time information is added to the descriptor, which imposes strict requirements on the data transmission time. If the descriptor trigger issuance time is abnormal (such as incorrect data migration time within the descriptor), it may cause the descriptor to remain in a waiting state for a long time due to the failure to reach the start migration time. This will result in a large number of descriptors accumulating in the descriptor cache module. Alternatively, if a certain descriptor needs to migrate a large amount of data, resulting in a long data migration time, it will also lead to a large number of descriptors accumulating in the descriptor cache module.

[0235] The descriptors are processed one by one in the order they are moved back. Therefore, when processing subsequent normal descriptors, the accumulation of previous descriptors will cause a time delay, thus keeping the entire data migration in an abnormal state.

[0236] Therefore, embodiments of the present invention can also add a timeout protection mechanism. That is, after the read descriptor module receives the descriptor trigger after being parsed by the descriptor trigger information configuration module, it will determine whether the remaining space of the cache space used to cache descriptors in the descriptor cache module is less than a preset threshold. If so, it will enter a protection state, that is, the read descriptor module will discard the parsed descriptor trigger received this time and start a timer. During the timer period, the received parsed descriptor trigger will be discarded until the timer period reaches the preset time (e.g., 10 microseconds). Then, it will determine again whether the remaining space is less than the preset threshold.

[0237] In summary, the embodiments of the present invention have the following advantages:

[0238] 1. The number of interfaces is flexible and controllable; AXI interfaces can be added as needed to interact with PCIe IP cores.

[0239] 2. By triggering FPAG to actively read the descriptor through a descriptor trigger, CPU utilization can be reduced;

[0240] 3. It can move multiple descriptors at once and has a 2k descriptor cache, which can improve data migration efficiency;

[0241] 4. Add time information to the descriptor to make data migration time controllable;

[0242] 5. The data output interface is converted to a RAM interface for convenient subsequent data storage and use.

[0243] Embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing the processor to perform the data processing method described above.

[0244] The processor-readable storage medium can be any available medium or data storage device that the processor can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).

[0245] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0246] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0247] These processor-executable instructions may also be stored in a processor-readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the processor-readable memory produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0248] These processors can execute instructions that can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0249] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data transmission method, characterized in that, The method, applied to a field-programmable gate array (FPGA), includes: Receive descriptor trigger information sent by the central processing unit (CPU), wherein the descriptor trigger information includes descriptor storage address information; The descriptor trigger information is parsed, and multiple descriptors stored in the CPU are read according to the descriptor storage address information obtained from the parsing, and the multiple descriptors are stored. The descriptor includes data migration time, data source address information and data destination address information. Parse the i-th descriptor, and based on the data migration time included in the parsed i-th descriptor, move the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA; Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

2. The data transmission method according to claim 1, characterized in that, Based on the data migration time included in the nth descriptor obtained through parsing, after moving the data stored in the nth first target address in the CPU to the nth second target address in the FPGA, the method further includes: Delete the first to the nth descriptors.

3. The data transmission method according to claim 2, characterized in that, After parsing the descriptor trigger information, the method further includes: Determine whether the remaining space in the storage space used to store the descriptor is less than a first preset threshold; Specifically, if the remaining space is greater than or equal to the first preset threshold, the steps of reading multiple descriptors stored in the CPU and storing the multiple descriptors are performed based on the descriptor storage address information obtained by parsing.

4. The data transmission method according to claim 3, characterized in that, The method further includes: If the remaining space is less than the first preset threshold, discard the currently parsed descriptor storage address information, start a preset timer, and discard the parsed descriptor storage address information within the timer's timeout period until the timer's timeout period reaches the preset time, then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

5. The data transmission method according to claim 1, characterized in that, The descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering information is valid; Specifically, if the parsed first indication information indicates that the descriptor trigger information is valid, the step of reading multiple descriptors stored in the CPU based on the parsed descriptor storage address information is executed.

6. The data transmission method according to claim 1, characterized in that, The descriptor also includes a descriptor validity signal, which indicates whether the descriptor is valid. Specifically, if the parsed i-th descriptor includes a descriptor validity signal indicating that the i-th descriptor is valid, the step of moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data migration time included in the parsed i-th descriptor is executed.

7. The data transmission method according to claim 1, characterized in that, Based on the data migration time included in the parsed i-th descriptor, after moving the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA, the method further includes: Convert the moved data into the first preset format.

8. The data transmission method according to claim 1, characterized in that, The method further includes at least one of the following steps: Report data to the CPU; Receive a Double Data Rate (DMR) synchronous dynamic random access memory (DDR) request sent by the CPU, and send data associated with the DDR access request to the CPU according to the DDR access request; Receive configuration parameters sent by the CPU.

9. A data transmission method, characterized in that, Applied to a central processing unit (CPU), the method includes: A descriptor trigger message is sent to the Field Programmable Gate Array (FPGA) so that the FPGA can parse the descriptor trigger message and read multiple descriptors stored in the CPU according to the descriptor storage address information obtained from the parsing, and store the multiple descriptors, wherein the descriptor includes data migration time, data source address information and data destination address information; the i-th descriptor is parsed, and according to the data migration time included in the i-th descriptor, the data stored in the i-th first target address in the CPU is moved to the i-th second target address in the FPGA; wherein the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of multiple descriptors.

10. The data transmission method according to claim 9, characterized in that, Sending descriptor trigger information to the FPAG includes: The descriptor trigger information is sent to the FPAG at preset time intervals.

11. A data transmission device, characterized in that, The device, applied to a field-programmable gate array (FPGA), includes: An interface conversion module is used to receive descriptor trigger information sent by a central processing unit (CPU), wherein the descriptor trigger information includes descriptor storage address information; The descriptor trigger information configuration module is used to parse the descriptor trigger information to obtain the descriptor storage address information; The descriptor reading module is used to read multiple descriptors stored in the CPU based on the descriptor storage address information obtained by the descriptor trigger information configuration module. A descriptor caching module is used to store the plurality of descriptors read by the read descriptor module, wherein the descriptor includes data migration time, data source address information and data destination address information; The system includes a Direct Memory Access (DMA) control module and a data transfer module. The DMA control module receives the i-th descriptor sent by the descriptor cache module, parses the i-th descriptor, and controls the data transfer module to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA based on the data transfer time included in the parsed i-th descriptor. Wherein, the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of the plurality of descriptors.

12. The data transmission apparatus according to claim 11, characterized in that, The DMA control module, based on the data transfer time included in the parsed nth descriptor, controls the data transfer module to transfer the data stored in the nth first target address in the CPU to the nth second target address in the FPGA. The descriptor caching module is further configured to: Delete the first to the nth descriptors.

13. The data transmission apparatus according to claim 12, characterized in that, After receiving the descriptor storage address information parsed by the descriptor trigger information configuration module, the descriptor reading module is further configured to: determine whether the remaining space of the storage space used to store the descriptor is less than a first preset threshold. Among them, the read descriptor module If the remaining space is greater than or equal to the first preset threshold, the step of reading multiple descriptors stored in the CPU is executed, based on the descriptor storage address information parsed by the descriptor trigger information configuration module.

14. The data transmission apparatus according to claim 13, characterized in that, The descriptor reading module is further configured to: discard the descriptor storage address information currently received by the descriptor trigger information configuration module when the remaining space is less than the first preset threshold, start a pre-set timer, and discard the descriptor storage address information received by the descriptor trigger information configuration module within the timer's timing period, until the timer's timing period reaches the preset time, and then return to the step of determining whether the remaining space of the storage space used to store the descriptor is less than the first preset threshold.

15. The data transmission apparatus according to claim 11, characterized in that, The descriptor triggering information further includes: first indication information, which is used to indicate whether the descriptor triggering signal is valid; Wherein, when the first indication information obtained by parsing indicates that the descriptor trigger information is valid, the descriptor trigger information configuration module sends the parsed descriptor storage address information to the read descriptor module.

16. The data transmission apparatus according to claim 11, characterized in that, The descriptor also includes a descriptor validity signal, which indicates whether the descriptor is valid. Wherein, when the parsed descriptor valid signal of the i-th descriptor indicates that the i-th descriptor is valid, the DMA control module executes the step of controlling the data transfer module to transfer the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA according to the data transfer time included in the parsed i-th descriptor.

17. The data transmission apparatus according to claim 11, characterized in that, The device further includes: The format conversion module is used to convert the moved data into a first preset format.

18. The data transmission apparatus according to claim 11, characterized in that, The device further includes at least one of the following modules: The reporting module is used to report data to the CPU; The DDR module is used to receive a Double Data Rate (DMR) synchronous dynamic random access memory (DDR) request sent by the CPU, and to send data associated with the DDR access request to the CPU according to the DDR access request; The memory mapping module is used to receive configuration parameters sent by the CPU.

19. A data transmission device, characterized in that, The device, applied to a central processing unit (CPU), includes: The descriptor trigger information sending module is used to send descriptor trigger information to the Field Programmable Gate Array (FPGA) so that the FPGA can parse the descriptor trigger information, and read multiple descriptors stored in the CPU according to the descriptor storage address information obtained from the parsing, and store the multiple descriptors, wherein the descriptor includes data migration time, data source address information and data destination address information; parse the i-th descriptor, and according to the data migration time included in the i-th descriptor, move the data stored in the i-th first target address in the CPU to the i-th second target address in the FPGA; wherein the i-th first target address is the address represented by the data source address information included in the i-th descriptor, the i-th second target address is the address represented by the data destination address information included in the i-th descriptor, i is an integer from 1 to n, and n represents the number of multiple descriptors.

20. The data transmission apparatus according to claim 19, characterized in that, The descriptor trigger information sending module is specifically used for: The descriptor trigger information is sent to the FPAG at preset time intervals.

21. A processor-readable storage medium, characterized in that, The processor-readable storage medium stores a computer program that causes the processor to perform the method according to any one of claims 1 to 8, or to perform the method according to any one of claims 9 to 10.

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