Access verification method and apparatus, electronic device, and storage medium

Abstract

The embodiment of the present application discloses an access verification method and device, electronic equipment and computer storage medium, the method comprises: obtaining the number of physical memory protection table items of a to-be-tested chip; determining the physical memory protection table items corresponding to each memory region pre-allocated according to the number of physical memory protection table items of the to-be-tested chip; wherein each physical memory protection table item of the to-be-tested chip comprises access permission and address information of the corresponding memory region; based on the content in each physical memory protection table item, generate a verification item corresponding to each physical memory protection table item of the to-be-tested chip, the verification item corresponding to each physical memory protection table item is used to verify whether the to-be-tested chip performs access control according to the corresponding physical memory protection table item; execute the verification item corresponding to each physical memory protection table item.

Description

Technical Field

[0001] Embodiments of this application relate to an access verification method, apparatus, electronic device, and storage medium. Background Technology

[0002] Physical Memory Protection (PMP) technology is used to isolate physical memory regions. The number of PMP entries in a chip under test (DUT) depends on the specific application scenario and chip design requirements. That is, the number of PMP entries is uncertain. The verification entries corresponding to each PMP entry are used to verify whether the DUT performs access control according to the corresponding PMP entry. In related technologies, for each DUT, verification entries for each PMP entry need to be manually written based on the number of PMP entries for that specific chip, which is quite complex. Summary of the Invention

[0003] This application provides at least one access verification method, apparatus, electronic device, and storage medium.

[0004] An access verification method provided in this application includes:

[0005] Obtain the number of PMP entries for the chip under test;

[0006] Based on the number of PMP entries in the chip under test, determine the PMP entries corresponding to each pre-allocated memory region; wherein, each PMP entry of the chip under test includes the access permissions and address information of the corresponding memory region;

[0007] Based on the content of each PMP entry, a verification item corresponding to each PMP entry of the chip under test is generated. The verification item corresponding to each PMP entry is used to verify whether the chip under test performs access control according to the corresponding PMP entry.

[0008] Execute the verification item corresponding to each PMP table entry.

[0009] In some embodiments, before obtaining the number of PMP entries of the chip under test, the method further includes: obtaining the number of security domains in the execution environment of the chip under test; and allocating a memory region for each security domain of the chip under test according to the number of security domains of the chip under test.

[0010] In some embodiments, allocating a memory region for each security domain of the chip under test based on the number of security domains of the chip under test includes: allocating a segmented memory region for each security domain of the chip under test based on the number of security domains of the chip under test and a preset segmentation method for the memory region.

[0011] In some embodiments, before obtaining the number of PMP entries of the chip under test, the method further includes: obtaining the number of execution environment security domains of the chip under test; and if the number of security domains of the chip under test is greater than 1, allocating a shared memory region for each security domain of the chip under test, wherein the shared memory region includes at least one of a shared code segment and a shared data segment.

[0012] In some embodiments, obtaining the number of security domains of the chip under test includes: during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test, determining whether a target interrupt signal is generated, wherein the target interrupt signal represents an interrupt signal generated when the switching between security domains is successful; if a target interrupt signal is generated, incrementing the value of i by 1, and repeating the step of determining whether a target interrupt signal is generated during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test; if no target interrupt signal is generated, determining the number of security domains of the chip under test based on the value of i.

[0013] In some embodiments, obtaining the number of PMP entries of the chip under test includes: reading a key value from the configuration register of the j-th PMP entry of the chip under test, the key value being used to indicate whether there is a next PMP entry; if the key value indicates that there is a next PMP entry, incrementing the value of j by 1, and repeating the step of reading the key value from the configuration register of the j-th PMP entry of the chip under test; if the key value indicates that there is no next PMP entry, determining the number of PMP entries of the chip under test based on the value of j.

[0014] In some embodiments, determining the PMP entries corresponding to each pre-allocated memory region based on the number of PMP entries of the chip under test includes: determining the PMP entries corresponding to each type of pre-allocated memory region based on the number of PMP entries of the chip under test and the type of each pre-allocated memory region.

[0015] In some embodiments, determining the PMP entry corresponding to each type of pre-allocated memory region based on the number of PMP entries in the chip under test and the type of each pre-allocated memory region includes:

[0016] Based on the type of each pre-allocated memory region, determine the access permissions for each type of memory region in the first mode and the access permissions for each type of memory region in the second mode. The first mode is machine mode, and the second mode is user mode or supervisor mode.

[0017] Based on the number of PMP entries in the chip under test, the access permissions of each type of memory region in the first mode, and the access permissions of each type of memory region in the second mode, a PMP entry corresponding to each pre-allocated type of memory region is generated.

[0018] An access verification device provided in this application includes:

[0019] The information acquisition module is used to acquire the number of PMP entries of the chip under test;

[0020] The information processing module is used to determine the PMP entries corresponding to each pre-allocated memory region based on the number of PMP entries of the chip under test; wherein, each PMP entry of the chip under test includes the access permissions and address information of the corresponding memory region;

[0021] The verification item generation module is used to generate a verification item corresponding to each PMP entry of the chip under test based on the content of each PMP entry. The verification item corresponding to each PMP entry is used to verify whether the chip under test performs access control according to the corresponding PMP entry.

[0022] The verification item execution module is used to execute the verification item corresponding to each PMP table entry.

[0023] This application also provides an electronic device, which includes a processor and a memory for storing a computer program that can run on the processor; wherein the processor is used to run the computer program to perform any of the above-described access verification methods.

[0024] This application also provides a computer storage medium storing a computer program that, when executed by a processor, implements any of the above-described access verification methods.

[0025] As can be seen, the embodiments of this application can adaptively determine the PMP entries corresponding to the pre-allocated memory area based on the number of PMP entries of the chip under test, thereby adaptively generating the verification items corresponding to each PMP entry. Since there is no need to manually rewrite the verification program for each chip under test, the implementation is relatively simple, reducing the manpower and time costs of generating the verification items corresponding to the PMP entries.

[0026] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0028] Figure 1 This is a flowchart of an access verification method according to an embodiment of this application;

[0029] Figure 2 This is a flowchart illustrating the process of obtaining the number of PMP entries in an embodiment of this application.

[0030] Figure 3 This is a flowchart illustrating the process of obtaining the number of security domains in the execution environment of the chip under test, as described in this application.

[0031] Figure 4 This is a schematic diagram of the memory region partitioning result and PMP entries of the chip under test in this embodiment of the application;

[0032] Figure 5 This is a flowchart of another access verification method according to an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the structure of an access verification device according to an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of a hardware entity of an electronic device in an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to be limiting of this application.

[0039] RISC-V is an open-source instruction set architecture (ISA) based on the Reduced Instruction Set Computing (RISC) principle. Simply put, it can be described as a type of "open-source hardware" corresponding to the open-source software movement. PMP is the memory isolation mechanism provided by RISC-V. However, the PMP solution does not consider scenarios where it coexists with other master nodes at the System-on-Chips (SoC) level, and cannot provide finer-grained hardware-level memory protection, nor can it solve the cache isolation problem between multiple regions. For example, the cache can be a cache or a Translation Lookaside Buffer (TLB).

[0040] For example, the PMP scheme can be a Physical Memory Protection Enhancements for memory access and execution prevention on Machine mode (SMEPMP) scheme that adopts Machine Mode (M mode) memory access and execution protection. The SMEPMP scheme is a scheme that combines the concepts of Security Monitor Extension (SME) and Domain Identification Extension. Here, SME is used to establish multiple security domains and uses Secure Monitor Firmware that works in machine mode to isolate and switch between different security domains.

[0041] In the chip under test (DUT), the number of PMP entries depends on the actual application scenario and chip design requirements; that is, the number of PMP entries is uncertain. For example, the number of PMP entries for a multi-core DUT can be 16, 32, or greater than 32. Each PMP entry includes access permissions for memory regions, and the corresponding verification items are used to verify whether the DUT performs access control according to the corresponding access permissions. In this case, for each DUT, a verification program needs to be manually written based on the number of PMP entries, which is quite complex. When there are many verification sub-items within the verification items corresponding to a PMP entry, the program code becomes even more complex. Here, the verification program refers to the program that performs verification according to the verification items corresponding to each PMP entry.

[0042] Furthermore, in chips employing a RISC-V multi-security-domain architecture, the comprehensiveness of the verification items corresponding to SMEPMP entries is particularly important. In chips under test (DUTs) using a RISC-V multi-security-domain architecture, the number of security domains depends on the actual application scenario and chip design requirements; that is, the number of security domains is uncertain. For example, the number of security domains can be four or more. When there are many verification sub-items in the verification items corresponding to SMEPMP entries, the uncertainty in the number of PMP entries and security domains increases the workload of writing the verification items corresponding to SMEPMP entries. At the same time, the verification items corresponding to SMEPMP entries for a specific chip cannot be adapted to the verification of other multi-core chips. Therefore, for each DUT, a verification program needs to be manually written, making implementation quite complex.

[0043] To address the aforementioned technical problems, this application proposes an access verification method. This access verification method can be applied to an electronic device with a processor. The electronic device can be a terminal or a server. The terminal can be a thin client, a thick client, a handheld or laptop device, a microprocessor-based system, a set-top box, a programmable consumer electronics product, a network personal computer, a minicomputer system, etc. The server can be a server computer system, a minicomputer system, a mainframe computer system, or a distributed cloud computing environment including any of the above systems, etc.

[0044] Electronic devices such as terminals and servers may include program modules for executing instructions. Typically, program modules may include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0045] The aforementioned processor may be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor.

[0046] The embodiments of this application are described in detail below with reference to the accompanying drawings.

[0047] Figure 1 This is a flowchart of an access verification method according to an embodiment of this application, such as... Figure 1 As shown, the process may include:

[0048] Step 101: Obtain the number of PMP entries for the chip under test.

[0049] For example, a PMP entry can be a SMEPMP entry.

[0050] Step 102: Based on the number of PMP entries in the chip under test, determine the PMP entries corresponding to each pre-allocated memory region; wherein, each PMP entry of the chip under test includes the access permissions and address information of the corresponding memory region.

[0051] Here, each pre-allocated memory region can be a memory region allocated for each security domain of the chip under test. For example, the PMP entries corresponding to different memory regions can be different PMP entries or the same PMP entry.

[0052] In this embodiment of the application, each PMP entry of the chip under test includes a configuration register and an address register. The configuration register is used to store the access permissions of the corresponding memory region, and the address register is used to store the address information of the corresponding memory region.

[0053] For example, based on the number of PMP entries in the chip under test (DUT), and with the goal of configuring access permissions to memory regions for each PMP entry, the PMP entries corresponding to each pre-allocated memory region can be determined. In one example, the more PMP entries the DUT has, the fewer memory regions corresponding to at least one PMP entry; conversely, the fewer PMP entries the DUT has, the more memory regions corresponding to at least one PMP entry.

[0054] Step 103: Based on the content of each PMP entry, generate a verification item corresponding to each PMP entry of the chip under test. The verification item corresponding to each PMP entry is used to verify whether the chip under test performs access control according to the corresponding PMP entry.

[0055] In this embodiment of the application, when determining each PMP entry of the chip under test, since each PMP entry of the chip under test includes the access permissions and address information of the corresponding memory region, a verification item corresponding to each PMP entry can be generated based on the access permissions and address information in each PMP entry.

[0056] Step 104: Execute the verification items corresponding to each PMP table entry.

[0057] Here, by executing the verification items corresponding to each PMP entry, it is possible to verify whether the chip under test (DUT) performs access control according to the corresponding PMP entry. For example, it is possible to verify whether the DUT performs access control according to the read, write, or execute permissions configured in the corresponding PMP entry.

[0058] As can be seen, the embodiments of this application can adaptively determine the PMP entries corresponding to the pre-allocated memory area based on the number of PMP entries of the chip under test, thereby adaptively generating the verification items corresponding to each PMP entry. Since there is no need to manually rewrite the verification program for each chip under test, the implementation is relatively simple, reducing the manpower and time costs of generating the verification items corresponding to the PMP entries.

[0059] In some embodiments, the process of obtaining the number of PMP entries for the chip under test may include:

[0060] Read the key value from the configuration register of the j-th PMP entry of the chip under test. The key value is used to indicate whether there is a next PMP entry.

[0061] If the key value indicates that there is a next PMP entry, increment the value of j by 1 and repeat the step of reading the key value from the configuration register of the j-th PMP entry of the chip under test; if the key value indicates that there is no next PMP entry, determine the number of PMP entries of the chip under test based on the value of j.

[0062] In some embodiments, a key value is used to indicate the existence of the (j+1)th PMP entry. For example, a key value of 0 indicates that the (j+1)th PMP entry does not exist; a key value that is not 0 indicates that the (j+1)th PMP entry exists.

[0063] For example, the initial value of j is 1. Starting from the configuration register of the first PMP entry of the chip under test, the existence of the next PMP entry is determined by reading the key value. If the key value indicates that the next PMP entry exists, the value of j is incremented by 1. If the key value indicates that the next PMP entry does not exist, the number of PMP entries of the chip under test can be determined as j.

[0064] Reference Figure 2 The process for determining the number of PMP entries in this application embodiment may include:

[0065] Step 201: Read the key value from the pmp.cfgj register.

[0066] Here, the pmp.cfgj register represents the configuration register for the j-th PMP entry of the chip under test.

[0067] Step 202: Determine if the key value is 0. If it is, proceed to step 203; otherwise, proceed to step 204.

[0068] Step 203: Determine the number of PMP entries based on the value of j, and then end the process.

[0069] Here, the number of PMP entries for the chip under test can be determined as j.

[0070] Step 204: Increment the value of j by 1, and return to step 201.

[0071] As can be seen, since the key value indicates whether there is a next PMP entry, this embodiment of the application can accurately determine the number of PMP entries of the chip under test by reading the key value in the configuration register of the j-th PMP entry.

[0072] In some embodiments, before obtaining the number of PMP entries of the chip under test, the number of security domains in the execution environment of the chip under test can also be obtained; based on the number of security domains of the chip under test, a memory region is allocated for each security domain of the chip under test.

[0073] Here, after determining the number of security domains of the chip under test, a corresponding memory region can be allocated to each security domain. For example, when the number of security domains of the chip under test is 32, memory regions can be allocated to each of the 32 security domains. In this embodiment, the memory regions allocated to different security domains are different.

[0074] As can be seen, the embodiments of this application can reasonably allocate the memory area of ​​each security domain according to the number of security domains of the chip under test, which is beneficial to reasonably determine the corresponding PMP table entry according to each pre-allocated memory area; that is, the PMP table entry can be adaptively determined according to the number of security domains of the chip under test.

[0075] In some embodiments, the process of allocating a memory region for each security domain of the chip under test based on the number of security domains of the chip under test may include: allocating a segmented memory region for each security domain of the chip under test based on the number of security domains of the chip under test and a preset segmentation method for the memory region.

[0076] Here, for each security domain, at least two segmented memory regions can be defined. For example, exemplarily, the preset memory region segmentation method can be to divide the memory region into at least two segments, which may include at least two of the following: a code segment, an execution permission verification memory segment, a data segment, a stack segment, and a read / write permission verification memory segment. Specifically, the code segment represents a memory region used to store the program's executable code; the execution permission verification memory segment represents a memory region used to verify execution permissions; the data segment represents a memory region used to store initialized global variables in the program; the stack segment represents a memory region that operates using a stack; and the read / write permission verification memory segment represents a memory region used to verify read / write permissions.

[0077] As can be seen, the embodiments of this application can accurately and reasonably divide the segmented memory region for each security domain according to the number of security domains of the chip under test and the preset segmentation method of the memory region, thereby facilitating the reasonable determination of the corresponding PMP table entry based on the pre-allocated segmented memory region for each security domain.

[0078] In some embodiments, before obtaining the number of PMP entries of the chip under test, the number of security domains of the chip under test may also be obtained; if the number of security domains of the chip under test is greater than 1, while allocating a separate memory region for each security domain of the chip under test, a shared memory region may be allocated for each security domain of the chip under test, the shared memory region including at least one of a shared code segment and a shared data segment.

[0079] Here, the shared code segment refers to the memory area used to implement code sharing between different security domains, and the shared data segment refers to the memory area used to implement non-code data sharing between different security domains.

[0080] In some embodiments, a shared memory region for each security domain of the chip under test can be allocated without allocating a separate memory region for each security domain of the chip under test.

[0081] As can be seen, the embodiments of this application can reasonably determine the shared memory region allocated to each security domain based on the number of security domains of the chip under test, thereby facilitating the reasonable determination of the corresponding PMP entries based on the pre-allocated shared memory region.

[0082] In some embodiments, the process of obtaining the number of security domains of the chip under test may include:

[0083] During the process of controlling the switching from the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test, it is determined whether a target interrupt signal is generated. The target interrupt signal represents the interrupt signal generated when the switching between security domains is successful.

[0084] If a target interrupt signal is generated, the value of i is incremented by 1, and the step of determining whether a target interrupt signal is generated is repeated during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test; if no target interrupt signal is generated, the number of security domains of the chip under test is determined according to the value of i.

[0085] For example, the target interrupt signal can be a machine exchange (MEXG) interrupt signal. If no target interrupt signal is generated, it means that the i-th security domain of the chip under test could not be successfully switched to the (i+1)-th security domain of the chip under test, that is, it means that the (i+1)-th security domain of the chip under test does not exist. In this case, the number of security domains of the chip under test can be i.

[0086] For example, Domain_i can be used to represent the (i+1)th security domain of the chip under test. The first security domain of the chip under test is Domain_0. For Domain_1, a timer interrupt can be triggered to attempt to switch Domain_1 to Domain_2. If Domain_1 is successfully switched to Domain_2, a target interrupt signal will be generated. If the switch to Domain_2 is not successful, no target interrupt signal will be generated.

[0087] For example, if i is an integer greater than or equal to 2 and the switch to Domain_i is successful, the value of i can be increased by 1. Then, the control will attempt to switch the Domain_i-1 of the chip under test to Domain_i and determine whether a target interrupt signal is generated.

[0088] For example, when i is an integer greater than or equal to 2, the switching process from Domain_i-1 to Domain_i of the chip under test can be: first switch Domain_i-1 of the chip under test to Domain_0, and then switch Domain_0 to Domain_i.

[0089] Reference Figure 3 The process for obtaining the number of security domains of the chip under test in this application embodiment may include:

[0090] Step 301: Trigger a timer interrupt to attempt to switch Domain_1 to Domain_2.

[0091] Step 302: Determine whether a mexg interrupt occurs during the process of attempting to switch from Domain_i-1 to Domain_i; if yes, proceed to step 303; otherwise, proceed to step 304.

[0092] Step 303: Increment the value of i by 1, and return to step 302.

[0093] Here, if a mexg interrupt occurs during the process of attempting to switch from Domain_i-1 to Domain_i, it can be determined that Domain_i exists, and thus the existence of the (i+1)th security domain can be confirmed.

[0094] Step 304: Determine the number of security domains of the chip under test based on the value of i, and then end the process.

[0095] Here, if no mexg interrupt is generated during the process of attempting to switch from Domain_i-1 to Domain_i, it can be determined that Domain_i does not exist, and thus the (i+1)th security domain does not exist. At this point, the number of security domains of the chip under test can be determined as i.

[0096] As can be seen, since the target interrupt signal represents the interrupt signal generated when the switch between security domains is successful, the embodiments of this application can determine the number of security domains of the chip under test more accurately by judging whether the target interrupt signal is generated during the switching of security domains.

[0097] In some embodiments, the process of determining the PMP entries corresponding to each pre-allocated memory region based on the number of PMP entries of the chip under test may include: determining the PMP entries corresponding to each type of pre-allocated memory region based on the number of PMP entries of the chip under test and the type of each pre-allocated memory region.

[0098] For example, the same PMP entry can be set for the same type of memory region. That is, when each PMP entry corresponds to multiple memory regions, the multiple memory regions corresponding to each PMP entry can be of the same type of memory region.

[0099] For example, the number of PMP entries for the chip under test can be set differently for the same type of memory region.

[0100] For example, each pre-allocated memory region can be a memory region segmented into different types. These segmented memory regions can include multiple memory regions segmented according to the aforementioned preset memory region segmentation method. For instance, different segmented memory regions can include at least two of the following: code segment, execution permission verification memory segment, data segment, stack segment, and read / write permission verification memory segment. For example, different segmented memory regions can also include at least one of the following: the aforementioned shared memory region, a memory region for serial port initialization, and a memory region for storing firmware data.

[0101] As can be seen, the embodiments of this application can allocate corresponding PMP entries for each type of memory region more accurately according to the number of PMP entries of the chip under test and the type of each pre-allocated memory region, which is beneficial for reasonably determining the access permissions for each type of memory region.

[0102] In some embodiments, the process of determining the PMP entries corresponding to each type of pre-allocated memory region based on the number of PMP entries in the chip under test and the type of each pre-allocated memory region may include:

[0103] Based on the type of each pre-allocated memory region, determine the access permissions for each type of memory region in the first mode and the access permissions for each type of memory region in the second mode. The first mode is machine mode, and the second mode is user mode or supervisor mode.

[0104] Based on the number of PMP entries in the chip under test, the access permissions of each type of memory region in the first mode, and the access permissions of each type of memory region in the second mode, a PMP entry corresponding to each pre-allocated type of memory region is generated.

[0105] As can be seen, the embodiments of this application can set access permissions for each type of memory region that are different from those in machine mode for user mode or supervisor mode, thereby generating PMP entries corresponding to each type of memory region. In this way, the access permissions of the chip under test in different modes can be verified.

[0106] In one application scenario, the chip under test (DUT) has 16 security domains, which can be denoted as Domain_0 to Domain_15. The DUT also has 16 PMP entries. (Refer to...) Figure 4 The 16 PMP entries of the chip under test can be denoted as entry0 to entry15.

[0107] Reference Figure 4 The access permissions for each PMP entry can be represented by the LRWX field and the result field. In the LRWX field, L indicates whether the PMP entry is locked. When the value of the L field is 1, it means that the PMP entry is locked, and writing to the configuration register and the corresponding address register of the PMP entry will be ignored. When the value of the L field is 0, it means that the PMP entry is not locked. The R field, W field, and X field represent read permission, write permission, and execute permission, respectively. When the corresponding field is 1, it means that the permission is possessed, and when the corresponding field is 0, it means that the permission is not possessed. Figure 4 In this context, E test indicates execution test, and R / W test indicates read / write test.

[0108] Reference Figure 4 M represents machine mode, U represents user mode (U mode), and S represents supervisor mode (S mode).

[0109] R_start represents the memory area used for serial port initialization. In this embodiment, when outputting the execution result of the verification item, it is necessary to rely on serial port printing. Therefore, a memory area is allocated for serial port initialization. For example, the permissions of the memory area are set through entry0 to have write permissions in M ​​mode, supervisor mode and user mode.

[0110] text.domain0 through text.domain15 represent the code segments corresponding to Domain_0 through Domain_15, respectively; x.test.text.domain0 represents the execution permission verification memory segment corresponding to Domain_0. When X takes values ​​from 1 to 15, x.test.text.domainX represents the execution permission verification memory segment corresponding to Domain_X. share.code is the shared code segment from Domain_0 to Domain_15.

[0111] data.domain0 to data.domain15 represent the data segments corresponding to Domain_0 to Domain_15, respectively; share.data is the shared data segment of Domain_0 to Domain_15; sp.domain0 to sp.domain15 represent the stack segments corresponding to Domain_0 to Domain_15, respectively.

[0112] rw.test.domain0 to rw.test.domain15 represent the read / write permission verification memory segments corresponding to Domain_0 to Domain_15, respectively; rw.test.domain0 represents the read / write permission verification memory segment corresponding to Domain_0; when X takes values ​​from 1 to 15, rw.test.domainX represents the read / write permission verification memory segment corresponding to Domain_X.

[0113] For rw.test.domain1 to rw.test.domain15, the following three PMP entries are used: entry12, entry13, and entry14. Among them, entry13 is used to configure the access permissions of the read and write test areas. For example, different security domains can be used as read and write test areas by modifying the address register (pmpaddr) in entry13. entry12 is used to configure the access permissions of non-read and write test areas in the read and write permission verification memory segment, and entry14 is used to configure the access permissions of non-read and write test areas in the read and write permission verification memory segment.

[0114] R_end represents the memory area used to store firmware data. For example, R_end can be implemented using a memory such as Static Random-Access Memory (SRAM).

[0115] pass Figure 4It can be seen that the permissions of Domain_0 are related to the execution mode and the segmentation type of the memory region. The execution mode can be M mode, U mode, or S mode. For the data segments corresponding to Domain_1 to Domain_15, read and write permissions are only available in U mode or S mode; for the code segments corresponding to Domain_1 to Domain_15, execute permissions are only available in U mode or S mode; for the stack segments corresponding to Domain_1 to Domain_15, read and write permissions are only available in U mode or S mode; based on Figure 4 The configuration method of the PMP entries shown can achieve isolation of different memory regions while the code is running normally.

[0116] Figure 5 Here is a flowchart of another access verification method according to an embodiment of this application, referred to... Figure 5 The process may include:

[0117] Step 501: Obtain the number of security domains of the chip under test.

[0118] Step 502: Allocate a memory region for each security domain of the chip under test according to the number of security domains of the chip under test.

[0119] Step 503: Obtain the number of PMP entries for the chip under test.

[0120] Step 504: Based on the number of PMP entries in the chip under test and the memory area allocated to each security domain of the chip under test, generate a verification item corresponding to each PMP entry in the chip under test.

[0121] Step 505: Execute the validation items corresponding to each PMP entry.

[0122] In summary, the embodiments of this application can adaptively configure the verification items corresponding to SMEPMP entries for chips under test (DUTs) employing a RISC-V multi-security-domain architecture. These embodiments can dynamically reallocate memory regions based on the number of security domains in the DUT, and can also adaptively configure the verification items corresponding to SMEPMP entries (achieved through hierarchical code) by combining the dynamically acquired number of SMEPMP entries and the reallocated memory regions, thereby enabling functional verification of each verification sub-item within the verification item. In an exemplary scenario, the hardware environment of the DUT can first be downloaded to the FPGA platform via programming or other methods, allowing for simulation-based verification of the DUT's PMP verification items on the FPGA platform.

[0123] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0124] Based on the foregoing embodiments, this disclosure provides an access verification device. Figure 6 This is a schematic diagram of the structure of an access verification device according to an embodiment of this application, such as... Figure 6 As shown, the device may include an information acquisition module 601, an information processing module 602, a verification item generation module 603, and a verification item execution module 604; wherein,

[0125] The information acquisition module 601 is used to acquire the number of PMP entries of the chip under test;

[0126] The information processing module 602 is used to determine the PMP entries corresponding to each pre-allocated memory region based on the number of PMP entries of the chip under test; wherein each PMP entry of the chip under test includes access permissions and address information of the corresponding memory region;

[0127] The verification item generation module 603 is used to generate a verification item corresponding to each PMP entry of the chip under test based on the content of each PMP entry. The verification item corresponding to each PMP entry is used to verify whether the chip under test performs access control according to the corresponding PMP entry.

[0128] The verification item execution module 604 is used to execute the verification item corresponding to each PMP table entry.

[0129] In some embodiments, the information acquisition module 601 is further configured to acquire the number of security domains of the chip under test before acquiring the number of PMP entries of the chip under test; and allocate a memory region for each security domain of the chip under test according to the number of security domains of the chip under test.

[0130] In some embodiments, the information acquisition module 601 is configured to allocate a memory region for each security domain of the chip under test according to the number of security domains of the chip under test, including: allocating a segmented memory region for each security domain of the chip under test according to the number of security domains of the chip under test and a preset segmentation method for the memory region.

[0131] In some embodiments, the information acquisition module 601 is further configured to acquire the number of security domains of the chip under test before acquiring the number of PMP entries of the chip under test; and if the number of security domains of the chip under test is greater than 1, allocate a shared memory region for each security domain of the chip under test, wherein the shared memory region includes at least one of a shared code segment and a shared data segment.

[0132] In some embodiments, the information acquisition module 601 is used to acquire the number of security domains of the chip under test, including: during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test, determining whether a target interrupt signal is generated, wherein the target interrupt signal represents an interrupt signal generated when the switching between security domains is successful; if a target interrupt signal is generated, incrementing the value of i by 1, and repeating the step of determining whether a target interrupt signal is generated during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test; if no target interrupt signal is generated, determining the number of security domains of the chip under test based on the value of i.

[0133] In some embodiments, the information acquisition module 601 is used to acquire the number of PMP entries of the chip under test, including: reading a key value from the configuration register of the j-th PMP entry of the chip under test, the key value being used to indicate whether there is a next PMP entry; if the key value indicates that there is a next PMP entry, incrementing the value of j by 1, and repeating the step of reading the key value from the configuration register of the j-th PMP entry of the chip under test; if the key value indicates that there is no next PMP entry, determining the number of PMP entries of the chip under test based on the value of j.

[0134] In some embodiments, the information processing module 602 is configured to determine a PMP entry corresponding to each pre-allocated memory region based on the number of PMP entries of the chip under test, including: determining a PMP entry corresponding to each type of pre-allocated memory region based on the number of PMP entries of the chip under test and the type of each pre-allocated memory region.

[0135] In some embodiments, the information processing module 602 is configured to determine, based on the number of PMP entries in the chip under test and the type of each pre-allocated memory region, a PMP entry corresponding to each type of pre-allocated memory region, including:

[0136] The number of PMP entries in the chip and the type of each pre-allocated memory region are used to determine the PMP entries corresponding to each type of pre-allocated memory region, including:

[0137] Based on the type of each pre-allocated memory region, determine the access permissions for each type of memory region in the first mode and the access permissions for each type of memory region in the second mode. The first mode is machine mode, and the second mode is user mode or supervisor mode.

[0138] Based on the number of PMP entries in the chip under test, the access permissions of each type of memory region in the first mode, and the access permissions of each type of memory region in the second mode, a PMP entry corresponding to each pre-allocated type of memory region is generated.

[0139] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this application can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0140] It should be noted that, in the embodiments of this application, if the above-described access verification method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0141] This application provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements some or all of the steps in any of the above-described access verification methods. The computer-readable storage medium can be transient or non-transient.

[0142] This application provides a computer program including computer-readable code. When the computer-readable code is executed in a computer device, the processor in the computer device performs some or all of the steps for implementing any of the above-described access verification methods.

[0143] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described display compensation method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0144] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referenced interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product, please refer to the descriptions of the method embodiments of this application for understanding.

[0145] Figure 7 This is a schematic diagram of a hardware entity of an electronic device in an embodiment of this application, such as... Figure 7 As shown, the electronic device 70 may include: a memory 701, a processor 702, and a computer program stored in the memory 701 and executable on the processor 702; wherein,

[0146] The processor 702 is used to run the computer program to perform any of the above-described access verification methods.

[0147] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0148] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0149] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0150] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0151] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0152] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0153] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0154] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An access verification method, characterized in that, The method includes: Obtain the number of physical memory protection entries in the chip under test; Based on the number of physical memory protection entries in the chip under test, determine the physical memory protection entries corresponding to each pre-allocated memory region; wherein, each physical memory protection entry of the chip under test includes the access permissions and address information of the corresponding memory region; Based on the contents of each physical memory protection table entry, a verification item corresponding to each physical memory protection table entry is generated. The verification item corresponding to each physical memory protection table entry is used to verify whether the chip under test performs access control according to the corresponding physical memory protection table entry. Execute the verification item corresponding to each physical memory protection table entry; The step of determining the physical memory protection entries corresponding to each pre-allocated memory region based on the number of physical memory protection entries in the chip under test includes: Based on the type of each pre-allocated memory region, determine the access permissions for each type of memory region in the first mode and the access permissions for each type of memory region in the second mode. The first mode is machine mode, and the second mode is user mode or supervisor mode. Based on the number of physical memory protection entries in the chip under test, the access permissions of each type of memory region in the first mode, and the access permissions of each type of memory region in the second mode, physical memory protection entries corresponding to each pre-allocated type of memory region are generated.

2. The method according to claim 1, characterized in that, Before obtaining the number of physical memory protection entries in the chip under test, the method further includes: Obtain the number of security domains in the execution environment of the chip under test; Based on the number of security domains of the chip under test, a memory region is allocated for each security domain of the chip under test.

3. The method according to claim 2, characterized in that, The step of allocating a memory region for each security domain of the chip under test based on the number of security domains of the chip under test includes: Based on the number of security domains of the chip under test and the preset segmentation method of the memory region, a segmented memory region is allocated to each security domain of the chip under test.

4. The method according to claim 2, characterized in that, Before obtaining the number of physical memory protection entries in the chip under test, the method further includes: When the number of security domains of the chip under test is greater than 1, a shared memory region is allocated to each security domain of the chip under test. The shared memory region includes at least one of a shared code segment and a shared data segment.

5. The method according to any one of claims 2 to 4, characterized in that, Obtain the number of security domains of the chip under test, including: During the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test, it is determined whether a target interrupt signal is generated. The target interrupt signal represents the interrupt signal generated when the switching between security domains is successful. If a target interrupt signal is generated, the value of i is increased by 1, and the step of determining whether a target interrupt signal is generated is repeated during the process of controlling the switching of the i-th security domain of the chip under test to the (i+1)-th security domain of the chip under test. In the absence of a target interrupt signal, the number of security domains of the chip under test is determined based on the value of i.

6. The method according to any one of claims 1 to 4, characterized in that, The number of physical memory protection entries obtained for the chip under test includes: A key value is read from the configuration register of the j-th physical memory protection table entry of the chip under test. The key value is used to indicate whether there is a next physical memory protection table entry. If the critical value indicates the existence of the next physical memory protection entry, increment the value of j by 1 and repeat the step of reading the critical value from the configuration register of the j-th physical memory protection entry of the chip under test. When the key value indicates that there is no next physical memory protection entry, the number of physical memory protection entries of the chip under test is determined according to the value of j.

7. The method according to any one of claims 1 to 4, characterized in that, The step of determining the physical memory protection entries corresponding to each pre-allocated memory region based on the number of physical memory protection entries in the chip under test includes: Based on the number of physical memory protection entries in the chip under test and the type of each pre-allocated memory region, determine the physical memory protection entries corresponding to each type of pre-allocated memory region.

8. An access verification device, characterized in that, The device includes: The information acquisition module is used to acquire the number of physical memory protection entries of the chip under test; The information processing module is used to determine the physical memory protection entries corresponding to each pre-allocated memory region based on the number of physical memory protection entries in the chip under test; each physical memory protection entry of the chip under test includes the access permissions and address information of the corresponding memory region; The verification item generation module is used to generate a verification item corresponding to each physical memory protection table entry based on the content of each physical memory protection table entry. The verification item corresponding to each physical memory protection table entry is used to verify whether the chip under test performs access control according to the corresponding physical memory protection table entry. The verification execution module is used to execute the verification items corresponding to each physical memory protection table entry; The information processing module is used to determine the physical memory protection entries corresponding to each pre-allocated memory region based on the number of physical memory protection entries in the chip under test, including: Based on the type of each pre-allocated memory region, determine the access permissions for each type of memory region in the first mode and the access permissions for each type of memory region in the second mode. The first mode is machine mode, and the second mode is user mode or supervisor mode. Based on the number of physical memory protection entries in the chip under test, the access permissions of each type of memory region in the first mode, and the access permissions of each type of memory region in the second mode, physical memory protection entries corresponding to each pre-allocated type of memory region are generated.

9. An electronic device, characterized in that, It includes a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is used to run the computer program to perform the access verification method according to any one of claims 1 to 7.

10. A computer storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the access verification method according to any one of claims 1 to 7.

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