A local layout routing method for reducing crosstalk at chip module interfaces

Abstract

The application discloses a local layout wiring method for reducing crosstalk at a chip module interface, and belongs to the technical field of integrated circuits, and comprises the following steps: reading chip layout wiring data of the last time; using a tcl script language to arrange at least one buffer unit in a pin extension line layout of the chip module interface and generating an EDA tool executable command script; using the tcl script language to preset buffer unit positions and wiring distances according to buffer types and generating an EDA tool executable command script; extracting clock signal lines between buffer units arranged in module pins and using different metal layers to create a main part of an interconnection line and generating an EDA tool executable command script; after generating an integrated script file to complete local layout wiring at the chip module interface, subsequent chip design is completed; through the local layout wiring at the chip interface in advance, crosstalk between parallel signal lines is reduced, the integrity of signal transmission is improved, and the overall performance of the chip during work is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a local layout and routing method for reducing crosstalk at chip module interfaces. Background Technology

[0002] Crosstalk, according to electromagnetic theory, is electromagnetic coupling between two signal lines, caused by mutual capacitance and inductance between the lines, resulting in line noise. Crosstalk leads to data loss and transmission errors, preventing chips from functioning properly. In the field of integrated circuits, especially at deep submicron process nodes, with faster chip speeds, richer on-chip functions, and lower power consumption, crosstalk-induced noise becomes a significant challenge in deep submicron chip design. Typically, during chip design, engineers use primetime tools to read chip placement and routing data. To address crosstalk issues in this data, ECO (Engineer Changing Order) iterations are needed to continuously correct design problems. This lengthens the entire design cycle and reduces chip competitiveness.

[0003] Current EDA software such as ICC2 (IC Compiler 2) and FC (Fusion Compiler) have limited ability to resolve crosstalk issues at chip module interfaces during the placement and routing stage. In such cases, an ECO stage is required for repair, which increases the workload of chip design engineers and reduces their efficiency. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a local layout and routing method for reducing crosstalk at the chip module interface in order to overcome the shortcomings of the prior art, thereby reducing crosstalk at the chip module interface and shortening the chip design cycle.

[0005] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0006] A local layout and routing method for reducing crosstalk at chip module interfaces specifically includes the following:

[0007] Step 1: Read the chip layout and routing data;

[0008] Step 2: Based on the netlist after chip layout, according to the chip design process node, use the Tcl scripting language to place at least one buffer cell on the pin extension line of the chip module interface and generate an EDA tool executable command script.

[0009] Step 3: Use the Tcl scripting language to preset the buffer cell position and wiring distance according to the buffer type and generate an executable command script for the EDA tool;

[0010] Step 4: Use a TCL script to extract the clock signal lines between the buffer cells where the chip module pins are laid out, and use different metal layers to create the backbone of the interconnects and generate an executable command script for the EDA tool.

[0011] Step 5: Execute the integration script files generated in steps 2, 3, and 4 in the EDA tool;

[0012] Step 6: After completing the local layout and routing at the chip module interface, use EDA tools to complete the subsequent chip design.

[0013] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, in step 1, the chip layout and routing data of the previous step is read based on the Samsung 5-nanometer process node.

[0014] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, in step 2, based on the netlist after chip layout, according to the Samsung 5nm process node, two buffer units BUF_X6N_A6ZTSL_C8 are laid out on the pin extension line of the chip module block1 interface using the TCL scripting language, and an EDA tool executable command script is generated.

[0015] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, the pin extension line of the chip module interface is determined by the position of a certain metal layer line that makes up the chip module pin.

[0016] As a further preferred embodiment of the local layout routing method for reducing crosstalk at the chip module interface of the present invention, the buffer unit of the chip layout is determined by the cell library in the process node adopted by the chip, and the preset routing distance is determined by the driving capability of the chip layout buffer unit.

[0017] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, the buffering capacity of the chip layout unit is obtained by reading the previous chip layout and routing data according to step 1.

[0018] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, in step 4, the clock signal line in the chip is extracted by using an EDA tool to extract interconnect information from the netlist after the chip layout.

[0019] As a further preferred embodiment of the local layout and routing method for reducing crosstalk at the chip module interface of the present invention, in step 4, the interconnect trunks created are parallel to each other, and the buffers are located on both sides of the interconnect trunks.

[0020] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0021] This invention provides a local layout and routing method for reducing crosstalk at chip module interfaces. By pre-laying local layout and routing at the chip interface, on the one hand, it reduces crosstalk between parallel signal lines, improves signal transmission integrity, and enhances the overall performance of the chip during operation; on the other hand, it reduces the time spent on ECO (Engineer Changing Order) iterations to repair crosstalk at the chip interface interconnects, thereby improving chip design efficiency, shortening chip time-to-market, and making products more competitive. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1A This is a diagram showing the physical information distribution of some interconnect lines at the interface of a chip module according to an embodiment of the prior art;

[0024] Figure 1B This is a crosstalk data diagram of some interconnect lines at the chip module interface of a prior art embodiment;

[0025] Figure 1C This is a diagram showing the physical information distribution of some interconnect lines at the chip module interface according to an embodiment of the present invention;

[0026] Figure 1D This is a crosstalk data diagram of some interconnect lines at the chip module interface according to an embodiment of the present invention;

[0027] Figure 2 This is a flowchart of a local layout and routing method for reducing crosstalk at the chip module interface, according to another embodiment of the present invention. Detailed Implementation

[0028] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] To make the technical strategy, objectives, and benefits of this invention clearer, the invention will be further described in detail below with reference to the specific embodiments and accompanying drawings. For ease of explanation of the embodiments of this invention, only the necessary parts for illustrating the objectives of this invention are shown in the accompanying drawings.

[0031] Figure 1A This is a diagram showing the physical information distribution of some interconnect lines at the interface of a chip module according to an embodiment of the prior art. For example... Figure 1A As shown, the chip is designed based on Samsung's 5nm process node. A buffer unit exists on one side of the interface of chip module 1, at a length of 150 to 200 micrometers. Interconnect A is approximately 150 micrometers long, and interconnect D is approximately 200 micrometers long. Interconnects A, B, C, and D all use the D5 metal layer for their main horizontal traces. Figure 1B This is a crosstalk data diagram of some interconnect lines at the interface of a chip module in an embodiment of the prior art. For example... Figure 1B As shown, both interconnects A and C have noise. This is because interconnects A, B, C, and D are all routed using the D5 metal layer, which causes crosstalk between them.

[0032] Figure 1C This is a diagram showing the physical information distribution of some interconnect lines at the chip module interface according to an embodiment of the present invention. Figure 1D This is a crosstalk data diagram of a portion of the interconnect lines at the chip module interface according to an embodiment of the present invention.

[0033] like Figure 1C As shown, buffer units are added at the right edge of the chip interface and at a distance of 100μm. Interconnect A uses the D7 metal layer for the main horizontal routing, interconnect B uses the D9 metal layer for the main horizontal routing, interconnect C uses the D11 metal layer for the main horizontal routing, and interconnect D uses the D7 metal layer for the main horizontal routing. Figure 1D As shown, due to the use of different layers of routing in advance, there is no noise on interconnects A, B, C, and D, which effectively reduces the impact of crosstalk.

[0034] This invention proposes a local layout and routing method to reduce crosstalk at chip module interfaces. By pre-laying local layout and routing at the chip interfaces, on the one hand, it reduces crosstalk between parallel signal lines, improves signal transmission integrity, and enhances the overall performance of the chip during operation; on the other hand, it reduces the time spent on ECO (Engineer Changing Order) iterations to repair crosstalk at the chip interface interconnects, thereby improving chip design efficiency, shortening chip time-to-market, and making products more competitive.

[0035] like Figure 2As shown in the figure, the local layout and routing method for reducing crosstalk at the chip module interface according to an embodiment of the present invention includes the following steps:

[0036] Step 1: In the chip design, read the previous chip layout and routing data;

[0037] Step 2: In the chip design, based on the netlist after chip layout, according to the chip design process node, at least one buffer cell is laid out on the pin extension line of the chip module interface using the tcl (tool command language) scripting language, and an EDA tool executable command script is generated.

[0038] Step 3: In the chip design, the TCL scripting language is used to preset the buffer cell position and wiring distance according to the buffer type and generate an executable command script for EDA tools;

[0039] Step 4: In the chip design, the clock signal lines between the buffer units where the chip module pins are laid out are extracted using a TCL script, and the backbone of the interconnect is created using different metal layers, and an executable command script for the EDA tool is generated.

[0040] Step 5: In the chip design, execute the integration script files generated in steps 2, 3, and 4 in the EDA tool;

[0041] Step 6: In the chip design, after completing the local layout and routing at the chip module interface, use EDA tools to complete the subsequent chip design.

[0042] This invention proposes a local layout and routing method to reduce crosstalk at chip module interfaces. By pre-laying local layout and routing at the chip interfaces, on the one hand, it reduces crosstalk between parallel signal lines, improves signal transmission integrity, and enhances the overall performance of the chip during operation; on the other hand, it reduces the time spent on ECO (Engineer Changing Order) iterations to repair crosstalk at the chip interface interconnects, thereby improving chip design efficiency, shortening chip time-to-market, and making products more competitive.

[0043] The local layout and routing method for reducing crosstalk at chip module interfaces according to an embodiment of the present invention includes the following steps:

[0044] Step 1: Based on Samsung's 5nm process node, read the previous chip layout and routing data;

[0045] Step 2: Based on the netlist after chip layout, according to Samsung's 5nm process node, use the tcl (tool command language) scripting language to lay out two buffer cells BUF_X6N_A6ZTSL_C8 on the pin extension line of the chip module block1 interface and generate an EDA tool executable command script.

[0046] Step 3: Use the Tcl scripting language to preset the buffer cell position and wiring distance according to the buffer type and generate an executable command script for the EDA tool;

[0047] Step 4: Use a TCL script to extract the clock signal lines between the buffer cells where the chip module pins are laid out, and use different metal layers to create the backbone of the interconnects and generate an executable command script for EDA tools;

[0048] Step 5: Execute the integration script files generated in steps 2, 3, and 4 in the EDA tool;

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055] Step 6: After completing the local layout and routing at the chip module interface, use EDA tools to complete the subsequent chip design.

[0056] This invention proposes a local layout and routing method to reduce crosstalk at chip module interfaces. By pre-laying local layout and routing at the chip interfaces, on the one hand, it reduces crosstalk between parallel signal lines, improves signal transmission integrity, and enhances the overall performance of the chip during operation; on the other hand, it reduces the time spent on ECO (Engineer Changing Order) iterations to repair crosstalk at the chip interface interconnects, thereby improving chip design efficiency, shortening chip time-to-market, and making products more competitive.

[0057] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A local layout and routing method for reducing crosstalk at chip module interfaces, characterized in that, Specifically, it includes the following: Step 1: Read the chip layout and routing data; Step 2: Based on the netlist after chip layout, according to the chip design process node, use the Tcl scripting language to place at least one buffer cell on the pin extension line of the chip module interface and generate an EDA tool executable command script. Step 3: Use the Tcl scripting language to preset the buffer cell position and wiring distance according to the buffer type and generate an executable command script for the EDA tool; Step 4: Use a TCL script to extract the clock signal lines between the buffer cells where the chip module pins are laid out, and use different metal layers to create the backbone of the interconnects and generate an executable command script for the EDA tool. Step 5: Execute the integration script files generated in steps 2, 3, and 4 in the EDA tool; Step 6: After completing the local layout and routing at the chip module interface, use EDA tools to complete the subsequent chip design. In step 2, based on the netlist after chip layout, according to Samsung's 5nm process node, two buffer cells BUF_X6N_A6ZTSL_C8 are laid out on the pin extension line of the chip module block1 interface using the Tcl scripting language, and an EDA tool executable command script is generated. The pin extension line of the chip module interface is determined by the position of a certain metal layer line that makes up the chip module pins; The buffer unit of the chip layout is determined by the cell library in the process node adopted by the chip, and the preset wiring distance is determined by the driving capability of the chip layout buffer unit.

2. The local layout and routing method for reducing crosstalk at chip module interfaces according to claim 1, characterized in that, In step 1, based on Samsung's 5nm process node, the previous chip layout and routing data is read.

3. The local layout and routing method for reducing crosstalk at chip module interfaces according to claim 1, characterized in that, The buffering capacity of the chip layout unit is obtained by reading the previous chip layout and routing data in step 1.

4. The local layout and routing method for reducing crosstalk at chip module interfaces according to claim 1, characterized in that, In step 4, the clock signal line in the chip is extracted by using an EDA tool to extract the interconnect information from the netlist after the chip layout.

5. A local layout and routing method for reducing crosstalk at chip module interfaces according to claim 1, characterized in that, In step 4, the interconnect backbones created are parallel to each other, and the buffers are located on both sides of the interconnect backbones.

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