Through-hole layer multi-layer layout splitting optimization method

Abstract

The application provides a through-hole layer multi-layer layout splitting optimization method, comprising the following steps: S1, providing an original unsplit layout; S2, splitting the original unsplit layout according to initial splitting rules; S3, performing OPC correction and simulation on the layout obtained after splitting in step S2 to obtain a hotspot area limiting the overlapping process window; S4, adjusting the splitting rules of the patterns in the hotspot area and performing OPC correction and simulation to eliminate the hotspot area; S5, adding the splitting rules of the patterns set when the hotspot area is eliminated to a rule library to obtain an updated rule library; and S6, splitting the original unsplit layout according to the splitting rules in the updated rule library and performing OPC correction and simulation. According to the application, the process window of the process hotspot pattern can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a method for optimizing the multi-layer layout of vias. Background Technology

[0002] As the feature size of integrated circuits continues to shrink, the traditional 193nm single-exposure technology is difficult to use for lithography of patterns below 22nm. Single-exposure lithography has reached the resolution limit, and lithography problems have become the focus of research.

[0003] For process nodes of 14nm and below, the via layer layout needs to be split into two or more sheets, typically before optical proximity correction (OPC).

[0004] The map splitting process, based on splitting rules, will split graphics with a spacing less than a certain value onto two or more maps. Other graphics with a spacing greater than the minimum splitting spacing can be split based on principles such as having a relatively equal overall density across the two or more maps.

[0005] The split layout has some process hotspots during OPC correction, mainly because the OPC target size is small and in a semi-dense cycle, making it impossible to insert sub-resolution auxiliary patterns (SRAF), which results in a small process window for vias. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for optimizing the multiple layout splitting of via layers, which can solve the problem of process hotspots in the photolithography process of via layers in the prior art.

[0007] To achieve the above and other related objectives, this application provides a method for optimizing the multi-layer layout of vias, comprising:

[0008] Step S1: Provide the original, unsplit layout;

[0009] Step S2: Split the original unsplit map according to the initial splitting rules;

[0010] Step S3: Perform OPC correction and simulation on the layout obtained after splitting in step S2 to obtain the hot spot area that limits the overlapping process window;

[0011] Step S4: Adjust the splitting rules of the graphics in the hot spot area, and perform OPC correction and simulation to eliminate the hot spot area;

[0012] Step S5: Add the graphic splitting rules set when eliminating hotspot areas to the rule base to obtain an updated rule base;

[0013] Step S6: According to the splitting rules in the updated rule base, split the original unsplit layout and perform OPC correction and simulation.

[0014] Preferably, the initial splitting rule is a dual-map splitting rule or a multi-map splitting rule.

[0015] Preferably, the initial splitting rule defines the minimum spacing between the original unsplit map splits.

[0016] Preferably, based on the minimum spacing of the original unsplit map, the graphic that violates the minimum splitting spacing is split into two or more maps.

[0017] Preferably, the hot spot area obtained by step S3 is a process hot spot area where the via layer cannot be expanded after OPC correction and sub-resolution auxiliary patterns cannot be added.

[0018] Preferably, the process hotspot pattern that cannot be expanded and cannot have sub-resolution auxiliary patterns added after OPC correction refers to a pattern that cannot be expanded due to the limitations of the upper and lower metal lines during OPC correction and cannot have sub-resolution auxiliary patterns added due to the spacing limitations of the via itself.

[0019] Preferably, in step S4, adjusting the splitting rules of graphics in the hot spot area means adding rules for splitting process hot spot graphics onto two or more layouts, provided that the splitting rules ensure that graphics that violate the minimum splitting interval are split into two or more layouts.

[0020] Preferably, in step S6, for a graphic that does not violate the minimum splitting spacing, if it is located in a hotspot area, the process hotspot graphic is split into two or more layouts according to the splitting rules for process hotspot graphics.

[0021] Preferably, in step S6, for graphics that do not violate the minimum splitting interval, if they are not located in hotspot areas, a random splitting method is adopted, but it is necessary to ensure that the graphic density of the two or more maps obtained after splitting is close and the difference is within the specified range.

[0022] As described above, the via layer multi-layout splitting optimization method provided in this application has the following beneficial effects: based on the OPC model to predict the smaller spacing of the process window, the multi-layout splitting rules are adjusted. For the spacing range that is not necessary to split, the smaller spacing of the process window is taken into account, so as to avoid the via pattern in the split layout being in the smaller spacing range of the process window, thereby improving the process window of the process hotspot pattern. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 The flowchart shown is a process for optimizing the multi-layout splitting of via layers provided in an embodiment of this application.

[0025] Figure 2 The diagram shown is a schematic representation of an original layout according to an embodiment of this application;

[0026] Figure 3A Displayed as will Figure 2 The diagram shows layouts A and B obtained after splitting the original unsplit layout.

[0027] Figure 3B Displayed as in Figure 3A A schematic diagram showing the insertion of sub-resolution auxiliary graphics in layout A;

[0028] Figure 3C Displayed as in Figure 3A A schematic diagram showing the insertion of sub-resolution auxiliary graphics in layout B;

[0029] Figure 4A The display shows that the via layer multi-layout splitting optimization method provided in the embodiments of this application will be used to... Figure 2 The diagram shows layouts A and B obtained after splitting the original unsplit layout.

[0030] Figure 4B Displayed as in Figure 4A A schematic diagram showing the insertion of sub-resolution auxiliary graphics in layout A;

[0031] Figure 4C Displayed as in Figure 4A The diagram shown illustrates the insertion of sub-resolution auxiliary graphics in layout B. Detailed Implementation

[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0033] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0036] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0037] Currently, Double Pattering Lithography (DPL) has become the preferred method for further miniaturizing photolithography. DPL involves breaking down a high-density circuit pattern into two separate, relatively low-density patterns, which are then imaged and etched separately, thereby transferring the high-density pattern onto the target wafer.

[0038] During the layout splitting process, the initial design layout is split into two non-conflicting layouts according to the splitting rules. Since the splitting rules are pre-set by humans, they will not completely meet the design requirements after splitting. Only during the later simulation optimization can hot spots with design defects be detected. Thus, it is necessary to reset the rules and split again, requiring repeated splitting and simulation, which makes the design complex and time-consuming.

[0039] For process nodes of 14nm and below, the via layer layout needs to be split into two or more sheets, typically before optical proximity correction (OPC). The split layout exhibits some process hotspots during OPC correction, primarily due to the small OPC target size and its semi-dense period, making it impossible to insert sub-resolution auxiliary patterns (SRAF), thus resulting in a smaller process window for the vias.

[0040] To address this issue, this application provides a method for optimizing the multi-layer layout splitting of via layers.

[0041] Please see Figure 1 The flowchart illustrates the via layer multi-layout splitting optimization method provided in the embodiments of this application.

[0042] like Figure 1 As shown, the via layer multi-layout splitting optimization method includes the following steps:

[0043] Step S1: Provide the original, unsplit layout;

[0044] Step S2: Split the original unsplit map according to the initial splitting rules;

[0045] Step S3: Perform OPC correction and simulation on the layout obtained after splitting in step S2 to obtain the hot spot area that limits the overlapping process window;

[0046] Step S4: Adjust the splitting rules of the graphics in the hot spot area, and perform OPC correction and simulation to eliminate the hot spot area;

[0047] Step S5: Add the graphic splitting rules set when eliminating hotspot areas to the rule base to obtain an updated rule base;

[0048] Step S6: According to the splitting rules in the updated rule base, split the original unsplit layout and perform OPC correction and simulation.

[0049] In step S1, the original unsplit layout is provided. Figure 2 An example of a raw, unsplit layout is shown.

[0050] In step S2, the original unsplit layout is split according to the initial splitting rules.

[0051] According to the initial splitting rules, such as the double-layer layout splitting rules, the split layout cannot violate the minimum spacing requirements between single-layer layout graphics. Located in Figure 2 The spacing between the three graphics in the middle position (the three graphics connected by dotted lines in the figure) does not conform to the double map splitting rules. Therefore, these three graphics cannot be in the same map after splitting.

[0052] According to the initial splitting rules Figure 2 The original unsplit layout shown can be split into the following results: Figure 3A In the diagrams A and B, for the three figures connected by dashed lines, the figure in the middle is located in map A, and the figures at both ends are located in map B.

[0053] In step S3, the layout obtained after splitting in step S2 is modified by OPC and simulated to obtain the hot spot area that limits the overlapping process window.

[0054] like Figure 3A As shown, the via in the middle of the layer in layout A is in a semi-dense period. During OPC correction and simulation, the spacing between the graphics in layout A is insufficient to insert sub-resolution auxiliary graphics. In extreme cases, this can lead to the inability to add sub-resolution auxiliary graphics around the graphics in layout A (which is in a semi-dense period). Figure 3A (The area marked by the dotted line in the image cannot be surrounded by sub-resolution auxiliary graphics), which results in a small depth of focus (DOF) for the graphic in the lithography process, forming a hot spot area in the process window. Under conditions of energy and depth of focus offset, the via size may be too small, causing the graphic to disappear.

[0055] like Figure 3B As shown, during the OPC correction and simulation process, sub-resolution auxiliary graphics cannot be inserted in the middle position of the graphics in layout B.

[0056] To address this issue, in step S4, the splitting rules of the graphics in the hotspot region are adjusted, and OPC correction and simulation are performed to eliminate the hotspot region.

[0057] right Figure 2 The original unsplit layout shown has its splitting rules adjusted in hotspot areas. Specifically, the split layout should avoid situations where sub-resolution auxiliary graphics cannot be added in any of the four directions (top, bottom, left, and right) of the graphics.

[0058] The specific change is that, during the splitting process, while ensuring the minimum splitting rule in the initial splitting rules (the split layout cannot violate the minimum spacing requirement between graphics in a single layer), a splitting optimization rule is formulated based on the rules for adding sub-resolution auxiliary graphics. That is, graphics with pitches that cannot be used to add sub-resolution auxiliary graphics are placed on different layout layers as much as possible, so that the split layout will not have situations where sub-resolution auxiliary graphics cannot be added in multiple directions.

[0059] In step S4, for Figure 2 The original unsplit layout shown is split to obtain the following: Figure 4AIn the diagrams A and B, for the three figures connected by dashed lines, the figure in the middle is located in map A, and the figures at both ends are located in map B.

[0060] like Figure 4B and Figure 4C As shown, during the OPC correction and simulation process, sub-resolution auxiliary graphics can be added in all four directions (up, down, left, and right) of the graphics in layouts A and B, thereby eliminating hot spots.

[0061] This application uses OPC models or process verification results to identify the small spacing period of the via layer process window or the hot spot area of ​​the process window, and optimizes the via layer splitting rules and splitting methods to minimize the presence of small spacing periods and hot spot areas of the process window in the split layout.

[0062] The above embodiments describe the scenario of splitting the original unsplit layout into two layouts. The via layer multi-layout splitting optimization method provided in this application is also applicable to the scenario of splitting the original unsplit layout into multiple layouts.

[0063] Specifically, according to the multiple splitting rules, the original dense map is split into multiple relatively sparse maps, thus obtaining the initial split map. The multiple splitting rules define the minimum spacing for splitting the original map, and split the graphics in the original map that violate the minimum splitting spacing into two or more maps, while other graphics that do not violate the minimum splitting spacing are generally randomly and evenly split into two or more maps.

[0064] OPC correction was performed on the initial split layout. The process hotspot pattern that could not be expanded and could not have sub-resolution auxiliary patterns added after the via layer was identified. The multi-layout splitting rules of the via layer were adjusted, and OPC correction was performed after splitting using a new splitting method. The original process hotspot pattern was simulated to confirm that the process window of the hotspot pattern was improved.

[0065] The process hotspot pattern that cannot be expanded and cannot have sub-resolution auxiliary patterns added after OPC correction refers to the pattern that cannot be expanded during OPC correction due to the limitations of the upper and lower metal lines, and cannot have sub-resolution auxiliary patterns added due to the spacing of the via itself. This location is more likely to become a process hotspot where the via breaks after exposure.

[0066] Adjusting the multi-layout splitting rules for via layers refers to adding rules for splitting vias with specific structures and spacings onto two or more layouts, while ensuring that the splitting rules guarantee that graphics that violate the minimum splitting spacing will be split into two or more layouts.

[0067] The adjusted multi-layout splitting rules adopt a more random splitting method for graphics that do not violate the minimum splitting spacing, except for the newly added splitting rules for specific process hotspots. However, it is necessary to ensure that the graphic density of the two or more layouts obtained after splitting is close and the difference is within the specified range.

[0068] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] In summary, the via layer multi-layout splitting optimization method provided in this application, based on the OPC model to predict the smaller spacing of the process window, adjusts the multi-layout splitting rules, and optimizes the parameters in the splitting script. For spacing ranges that are not necessarily split, the smaller spacing of the process window is taken into account, minimizing the possibility that the via patterns in the split layout fall within the smaller spacing range of the process window, thereby improving the process window of the process hotspot pattern. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0070] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for optimizing the multi-layer layout of via layers, characterized in that, The method includes: Step S1: Provide the original, unsplit layout; Step S2: Split the original unsplit map according to the initial splitting rules; Step S3: Perform OPC correction and simulation on the layout obtained after splitting in step S2 to obtain hot spot areas that limit the overlapping process windows. The hot spot areas are areas where the via layer cannot be expanded and sub-resolution auxiliary patterns cannot be added after OPC correction. The process hot spot patterns where the via layer cannot be expanded and sub-resolution auxiliary patterns cannot be added after OPC correction refer to patterns that cannot be expanded due to the limitations of the upper and lower metal lines and cannot have sub-resolution auxiliary patterns added due to the spacing of the via itself during the OPC correction process. Step S4: Adjust the splitting rules of the graphics in the hot spot area, and perform OPC correction and simulation to eliminate the hot spot area; Step S5: Add the graphic splitting rules set when eliminating the hotspot area to the rule base to obtain an updated rule base; Step S6: According to the splitting rules in the updated rule base, the original unsplit layout is split, and OPC correction and simulation are performed.

2. The method according to claim 1, characterized in that, The initial splitting rule is either a dual-map splitting rule or a multi-map splitting rule.

3. The method according to claim 1 or 2, characterized in that, The initial splitting rule defines the minimum spacing between the original unsplit map splits.

4. The method according to claim 3, characterized in that, Based on the minimum spacing of the original unsplit map, the graphic that violates the minimum splitting spacing is split into two or more maps.

5. The method according to claim 4, characterized in that, In step S4, adjusting the splitting rules of graphics in the hot spot area means adding rules for splitting process hot spot graphics onto two or more layouts, provided that the splitting rules ensure that graphics that violate the minimum splitting interval are split into two or more layouts.

6. The method according to claim 5, characterized in that, In step S6, for a graphic that does not violate the minimum splitting spacing, if it is located in the hotspot area, the process hotspot graphic is split into two or more layouts according to the splitting rules for process hotspot graphics.

7. The method according to claim 1, characterized in that, In step S6, for graphics that do not violate the minimum splitting interval, if they are not located in the hot spot area, a random splitting method is adopted, but it is necessary to ensure that the graphic density of the two or more maps obtained after splitting is close and the difference is within the specified range.

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