A circuit and PCB for reducing power consumption of a solid state drive

Abstract

The application relates to the technical field of solid state disks, and discloses a circuit and a PCB for reducing power consumption of a solid state disk, which adopts a group of ONFI communication signals to control two NANDs, the first group and the second group of communication signals of U7 and U8 are connected in series through the group of ONFI communication signals, and the first group and the second group of communication signals of U9 and U10 are connected in series through the group of ONFI communication signals; the stub line of the ONFI communication signal is shortened, ODT does not need to be opened, obvious effects are achieved in reducing power consumption, and energy saving is improved; because the new PCB does not need to open ODT, the maximum power consumption is reduced from 14.9 W to 8.1 W; very beneficial effects are achieved in reducing power consumption; a kind of circuit is designed, the circuit is matched with the PCB wiring, the stub of the PCB wiring can be obviously shortened, the stub is reduced, ODT does not need to be opened, and the purpose of reducing power consumption is achieved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, specifically to a circuit and PCB for reducing the power consumption of solid-state drives. Background Technology

[0002] Solid-state drives (SSDs) are storage devices that use semiconductor flash memory (NAND Flash) as their medium. The communication protocol for NAND is ONFI (Open NAND Flash Interface). A set of ONFI communication signals typically requires multiple NAND chips to be connected in series. Because the ONFI communication signals are connected in series with multiple NAND chips, there is a long stub in the ONFI communication signal traces on the PCB. The long stub causes the signal quality to deteriorate. In order to improve the signal quality, ODT (On-die Termination) needs to be enabled on the ONFI communication signals. Enabling ODT will significantly increase the power consumption of the hard drive.

[0003] A new circuit design, in conjunction with PCB traces, can significantly shorten the stub of the PCB traces. With a smaller stub, ODT (Optical Detachment Transmission) will not need to be enabled, thus reducing power consumption. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] To address the shortcomings of existing technologies, this invention provides a circuit and PCB for reducing the power consumption of solid-state drives.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, the present invention provides the following technical solution: a circuit and PCB for reducing the power consumption of a solid-state drive, wherein a set of ONFI communication signals controls two NAND flash memory modules, the ONFI0 set of ONFI communication signals is connected in series with the first and second sets of communication signals of U7 and U8, and the ONFI3 set of ONFI communication signals is connected in series with the first and second sets of communication signals of U9 and U10.

[0008] Preferably, the ONFI0 trace no longer needs to run from U7 to U9, but instead the two sets of ONFI communication signals are directly connected inside the U7 chip, reducing the maximum stub line to 393.7 mils.

[0009] Preferably, the maximum length of the stub line of the ONFI3 of the U9 is also reduced to 393.7 mils.

[0010] Preferably, U7 and U8 are placed back-to-back on the PCB, with U7 on the front and U8 on the back. Similarly, for other NAND positions, the red-lettered chip is on the front and the green-lettered chip is on the back.

[0011] Preferably, U7 and U8 are placed back-to-back on the PCB, and U9 and U10 are also placed back-to-back on the PCB.

[0012] (III) Beneficial Effects

[0013] Compared with the prior art, the present invention provides a circuit and PCB for reducing the power consumption of solid-state drives, which has the following beneficial effects:

[0014] 1. The circuitry and PCB design that reduces the power consumption of solid-state drives (SSDs) shorten the stub line of the ONFI communication signal, eliminating the need to enable ODT (Optical Distribution Module), resulting in significant power reduction and greater energy efficiency.

[0015] 2. The circuitry and PCB for reducing solid-state drive power consumption have been improved. Because the new PCB does not require enabling ODT (Optical Distribution Detection), the maximum power consumption has been reduced from 14.9 watts to 8.1 watts, achieving a very beneficial effect in power consumption reduction.

[0016] 3. The circuit and PCB for reducing solid-state drive power consumption are designed such that the circuit and PCB traces can be coordinated to significantly shorten the stub of the PCB traces. With a smaller stub, the ODT will not need to be enabled, thus achieving the purpose of reducing power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a classic circuit of the present invention;

[0018] Figure 2 This is a schematic diagram of the communication signals of the NAND chip containing two sets of ONFI communication signals according to the present invention.

[0019] Figure 3 This is a schematic diagram of the NAND chip of the present invention;

[0020] Figure 4 This is a schematic diagram of the PCB of the present invention;

[0021] Figure 5 This is the actual PCB routing diagram of the present invention;

[0022] Figure 6 This is a schematic diagram of the circuit for reducing solid-state drive power consumption according to the present invention;

[0023] Figure 7 This is a schematic diagram illustrating the complete circuit principle of the present invention for reducing solid-state drive power consumption;

[0024] Figure 8 A PCB schematic diagram of the circuit design for reducing solid-state drive power consumption according to the present invention;

[0025] Figure 9 The actual PCB routing diagram for the circuit design of the solid-state drive to reduce power consumption in this invention;

[0026] Figure 10 A power consumption test comparison diagram of the old and new PCBs of this invention is shown. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] Please see Figure 1-10 In the current technology, an SSD contains multiple sets of ONFI communication signals. Most mainstream controller manufacturers use 8 sets of ONFI communication signals, while a commonly used NAND chip contains 2 sets of ONFI communication signals.

[0029] The classic circuit design uses four NAND flash memory blocks connected in series for every two sets of ONFI communication signals, such as... Figure 1 As shown, the ONFI0 and ONFI3 groups are used as examples to illustrate the principle, while the other groups are based on the same principle.

[0030] The ONFI communication signal of group ONFI0 is connected in series with the first group of ONFI communication signals of NAND chips U7, U8, U9 and U10.

[0031] The ONFI communication signal of ONFI3 group is connected in series with the second group of ONFI communication signals of NAND chips U7, U8, U9 and U10.

[0032] U7 and U8 are placed back-to-back on the PCB, with U7 on the front and U8 on the back. When U7 is projected vertically onto U8, their positions completely overlap. U9 and U10 are placed in the same way as U7 and U8, back-to-back.

[0033] A schematic diagram of the communication signals of a NAND chip containing two sets of ONFI communication signals, namely... Figure 2 DQ[7:0]_0 is the first group of ONFI communication signals, and DQ[7:0]_1 is the second group of ONFI communication signals.

[0034] In the physical location of the NAND chip, two sets of ONFI communication signals are evenly distributed in the upper and lower halves of the NAND chip. The upper half contains the first set of ONFI communication signals, and the lower half contains the second set of ONFI communication signals. Figure 3 As shown.

[0035] The PCB schematic and actual PCB routing diagram based on the classic circuit design in section two are as follows: Figure 4 and Figure 5 Taking the ONFI0 group ONFI communication signal as an example, after ONFI0 comes out of the controller, it is first connected in series with U7 and U8, and then connected in series with U9 and U10. The section of the trace from U7 to U9 on the PCB becomes the long stub trace of the ONFI communication signal. The stub trace is 738.6 mils long. Because the stub trace is too long, the ONFI signal needs to enable ODT. U7 and U8 are placed back to back on the PCB, with U7 on the front and U8 on the back. Similarly, for other NAND positions, the red-lettered chip is on the front and the green-lettered chip is on the back.

[0036] A circuit and PCB for reducing solid-state drive power consumption, instead of using the conventional method of two sets of ONFI communication signals connected in series with four NAND flash units, uses one set of ONFI communication signals to control two NAND flash units, such as... Figure 6 As shown.

[0037] ONFI0 group ONFI communication signal is connected in series with the first and second group communication signals of U7 and U8.

[0038] ONFI3 group ONFI communication signals are connected in series with the first and second group communication signals of U9 and U10.

[0039] U7 and U8 are also placed back-to-back on the PCB.

[0040] U9 and U10 are also placed back-to-back on the PCB.

[0041] The PCB schematic and physical diagram are as follows, redesigned according to the new circuitry. Figure 8 and Figure 9 As shown, because the ONFI0 trace no longer needs to run from U7 to U9, but instead connects the two sets of ONFI communication signals directly inside the U7 chip, the longest stub line is reduced to 393.7 mils. Similarly, the longest stub line of the ONFI3 of U9 is also reduced to 393.7 mils. U7 and U8 are placed back to back on the PCB, with U7 on the front and U8 on the back. Similarly, for other NAND positions, the red-lettered chip is on the front and the green-lettered chip is on the back.

[0042] A power consumption test was conducted comparing the old and new PCBs. Because the new PCB does not require enabling ODT (Optical Distribution Transmission), the maximum power consumption decreased from 14.9 watts to 8.1 watts, achieving a very significant reduction in power consumption. Figure 10 As shown.

[0043] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A circuit for reducing the power consumption of a solid-state drive, characterized in that: A NAND chip contains two sets of ONFI communication signals. Physically, these two sets of ONFI communication signals are evenly distributed across the upper and lower halves of the NAND chip, with the upper half containing the first set and the lower half containing the second set. NAND chips U7 and U8 are placed back-to-back on the PCB, with U7 on the front and U8 on the back. When U7 is projected vertically onto U8, their positions completely overlap. NAND chips U9 and U10 are placed in the same back-to-back configuration as U7 and U8. Two NAND chips are controlled by a single set of ONFI communication signals. The ONFI0 set connects the first and second sets of communication signals for U7 and U8 in series, while the ONFI3 set connects the first and second sets of communication signals for U9 and U10 in series. The ONFI0 set's traces no longer need to run from U7 to U9; instead, the two sets of ONFI communication signals are directly connected within the U7 chip.

2. The circuit for reducing solid-state drive power consumption according to claim 1, characterized in that: The maximum length of the stub line of the ONFI0 of the U7 is reduced to 393.7 mils.

3. The circuit for reducing solid-state drive power consumption according to claim 1, characterized in that: The maximum length of the stub line of the ONFI3 of the U9 is reduced to 393.7 mils.

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