Write equalization detector, write equalization detection circuit, and memory

Abstract

The application provides a write equalization detector, a write equalization detection circuit and a memory, which realizes a recovery logic function (equivalent to XOR of MCK_R1 and MCK_F1) into a flip-flop NMOS branch of the write equalization detector, and uses a half-frequency clock signal (MCK_R1 and MCK_F1) as the input, so that the timing deviation information of the clock (CK) signal relative to the DQS signal can be obtained without setting a clock recovery circuit, and the limitation of the maximum operation frequency and the additional phase error caused by the clock recovery circuit can be avoided.

Description

Technical Field

[0001] This invention relates to a write equalization detector, a write equalization detection circuit, and a memory. Background Technology

[0002] Based on read / write capabilities, memory can be divided into Read-Only Memory (ROM) and Random Access Memory (RAM). ROM stores fixed information; it's a semiconductor memory that can only be read, not written to. RAM, on the other hand, allows both reading and writing. Furthermore, RAM can be further divided into SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). SRAM includes SDR SRAM, DDR SRAM, QDR SRAM, ZBT SRAM, etc.; DRAM includes SDRAM, DDR DRAM, and RDRAM.

[0003] DRAM is a clock-synchronous memory that operates based on a clock signal issued by the processor. Command signals defining actions and address signals specifying memory cells are sent in parallel and synchronized with the rising edge of the clock. In DDR data transfer, the DQ Strobe (DQS) signal serves as the reference instead of the clock and transmits data via the DQ bus. Command and address signals are synchronized only to the rising edge of the clock, while data signals are synchronized to both the rising and falling edges of the DQS. The clock, command, and address signals are unidirectionally input to the DRAM from the processor, while DQS and DQS are bidirectional, input to the DRAM during writing and output from the DRAM during reading.

[0004] In memory, timing deviations between the clock signal and the DQS signal can sometimes occur due to channel mismatch or on-chip distribution mismatch. To eliminate these timing deviations, write equalization training is performed. High-speed DRAM devices such as LPDDR4 and DDR5 use half-frequency clocks to mitigate timing constraints in their internal control logic design. Traditional write equalization detection circuits in these half-frequency clock systems typically employ clock recovery circuitry before capturing the clock signal via the DQS signal.

[0005] Figure 5 This illustrates a prior art write equalization detection circuit that senses the timing deviation of the clock (CK) signal relative to the DQS signal during write equalization training mode and sends the timing deviation information back to the controller via the DQ pin.

[0006] The full-frequency (F) CK_T / CK_C and DQS_T / DQS_C are input through the input receiver and converted into a half-frequency (F / 2) 4-phase clock through the clock divider and DQS divider (a divide-by-two circuit), respectively. That is, "MCK_R1 / MCK_F1, MCK_R2 / MCK_F2" are generated by dividing the external clocks "CK_T, CK_C", and "DQS_R1 / DQS_F1, DQS_R2 / DQS_F2" are generated by dividing the external DQS signals "DQS_T, DQS_C". The half-frequency clock makes the internal control logic design easier to implement and allows it to operate at higher frequencies. The command decoder, address latch, control logic for write and read delays, and SERDES (short for SERializer / DESerializer) are designed based on the 4-phase clock.

[0007] Then, the DQS repeater outputs the half-frequency DQS_R1 / DQS_R2 signals along the long-distance on-chip line to the write equalizer detector; and the clock repeater outputs the half-frequency MCK_R1 / MCK_F1 signals along the long-distance on-chip line to the clock recovery circuit, which restores them to the original frequency (F) before outputting them to the write equalizer detector. The clock recovery circuit can be implemented using simple logic gates (see...). Figure 6 Here, if the half-frequency MCK_R1 / MCK_F1 signals are not restored to their original frequencies, it is impossible to determine which gating pulse corresponds to the first phase of the split DQS and CK, and thus the timing relationship between DQS_T and CK_T cannot be known.

[0008] Write equalization detector (see) Figure 7 The timing information is determined by capturing the recovered clock signal (CLK_Restore) using DQS_R1 and DQS_R2, to determine whether CK_T is earlier or later than DQS_T. This timing information is fed back to the controller via the DQ pin. The controller (DRAM controller) can adjust the DQS delay based on the output of the write equalization detector and resend the write equalization command to the DRAM.

[0009] Previously, the sampling circuit DFF written into the equalization detector typically used a traditional D flip-flop (see...). Figures 8A to 8C ).also, Figure 9A and Figure 9B The timing diagrams shown are for illustrating the first and second scenarios of writing balanced training actions in the prior art. Summary of the Invention

[0010] However, existing clock recovery circuits limit the maximum operating frequency as the clock period becomes smaller, and also cause additional phase errors due to defects in the clock recovery circuit itself.

[0011] This invention was made to solve the above-mentioned problems. Its purpose is to provide a write equalization detector, which implements the recovery logic function (equivalent to the XOR function of MCK_R1 and MCK_F1) into the NMOS branch of the write equalization detector flip-flop and uses half-frequency clock signals (MCK_R1 and MCK_F1) as its input. Thus, the timing deviation information of the clock (CK) signal relative to the DQS signal can be obtained without setting up a separate clock recovery circuit. This can avoid the limitation of the maximum operating frequency and additional phase error caused by the clock recovery circuit.

[0012] The first aspect of the present invention relates to a write equalization detector disposed in a memory, comprising: a first write equalization detection unit, which inputs a first half-frequency clock signal to a first input terminal, inputs a second half-frequency clock signal to a second input terminal, and inputs a first half-frequency DQS signal to a third input terminal; the first write equalization detection unit uses the first half-frequency clock signal, the second half-frequency clock signal, and the first half-frequency DQS signal as inputs to generate and output first timing deviation information of the clock signal relative to the DQS signal; and a second write equalization detection unit, which inputs the first half-frequency clock signal to a fourth input terminal, inputs the second half-frequency clock signal to a fifth input terminal, and inputs the second half-frequency DQS signal to a sixth input terminal; the second write equalization detection unit uses the first half-frequency clock signal, the second half-frequency clock signal, and the second half-frequency DQS signal as inputs to generate and output second timing deviation information of the clock signal relative to the DQS signal.

[0013] Furthermore, the first half-frequency clock signal and the second half-frequency clock signal are obtained by using a clock divider to convert the signal obtained by comparing the first clock signal and the second clock signal with the first comparator into a half-frequency clock signal and outputting it through a clock repeater. The first half-frequency DQS signal and the second half-frequency DQS signal are obtained by using a DQS divider to convert the signal obtained by comparing the first DQS signal and the second DQS signal with the second comparator into a half-frequency DQS signal and outputting it through a DQS repeater.

[0014] Furthermore, the output terminals of the first write equalization detection unit and the second write equalization detection unit also include a first inverter and a second inverter connected in series.

[0015] The write equalization detection circuit according to a second aspect of the present invention includes: the write equalization detector described above; a first comparator that compares a first clock signal and a second clock signal; a clock divider that converts the signal obtained by the first comparator into a half-frequency clock signal; a clock repeater that outputs the half-frequency clock signal obtained by the clock divider to the write equalization detector via the clock repeater; a second comparator that compares a first DQS signal and a second DQS signal; a DQS divider that converts the signal obtained by the second comparator into a half-frequency DQS signal; and a DQS repeater that outputs the half-frequency DQS signal obtained by the DQS divider to the write equalization detector via the DQS repeater.

[0016] The memory according to the third aspect of the present invention includes the write equalization detection circuit described above.

[0017] Invention Effects

[0018] According to the write equalizer of the present invention, by implementing the recovery logic function (equivalent to the XOR function of MCK_R1 and MCK_F1) into the NMOS branch of the write equalizer flip-flop, and using the half-frequency clock signals (MCK_R1 and MCK_F1) as its input, the timing deviation information of the clock (CK) signal relative to the DQS signal can be obtained without setting up a separate clock recovery circuit. This avoids the limitation of the maximum operating frequency and additional phase error caused by the clock recovery circuit. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating a specific structural example of the write equalization detection circuit 1 according to an embodiment of the present invention.

[0020] Figure 2 This is a block diagram illustrating a specific structural example of the write equalization detector 10 according to an embodiment of the present invention.

[0021] Figure 3A , Figure 3B , Figure 3C This is a circuit diagram illustrating a specific structural example of the first write equalization detection unit 101 in the write equalization detector 10 according to an embodiment of the present invention.

[0022] Figure 4AThis is a timing diagram illustrating the first scenario of the write equalization training action performed by the write equalization detection circuit 1 according to an embodiment of the present invention. Figure 4B This is a timing diagram illustrating a second scenario of the write equalization training action performed by the write equalization detection circuit 1 according to an embodiment of the present invention.

[0023] Figure 5 This is a block diagram illustrating a write equalization detection circuit in the prior art that senses the timing deviation of the clock (CK) signal relative to the DQS signal during write equalization training mode and sends the timing deviation information back to the controller via the DQ pin.

[0024] Figure 6 This is a circuit diagram illustrating the specific structure of the clock recovery circuit written into the equalization detection circuit in the prior art.

[0025] Figure 7 This is a block diagram illustrating the specific structure of the write equalization detector in a prior art write equalization detection circuit.

[0026] Figure 8 is a circuit diagram showing the specific structure of the sampling circuit DFF of the write equalization detector in the prior art write equalization detection circuit.

[0027] Figure 9A This is a timing diagram illustrating the first scenario of the write equalization training action performed by the write equalization detection circuit in the prior art; Figure 9B This is a timing diagram illustrating a second scenario of the write equalization training action performed by the write equalization detection circuit in the prior art.

[0028] Label Explanation

[0029] 1. Write equalization detection circuit

[0030] 10 Write equalization detector

[0031] 21 First comparator

[0032] 31-Clock Divider

[0033] 41 Clock Repeater

[0034] 22 Second comparator

[0035] 32 DQS frequency divider

[0036] 42 DQS Repeater

[0037] 101 First Write Equalization Detection Unit

[0038] 102 Second Write Equalization Detection Unit

[0039] 103 First Inverter

[0040] 104 Second Inverter

[0041] 1021 First Crystal Oscillator

[0042] 1022 Second Crystal Oscillator

[0043] 1010 Third Inverter

[0044] 1011 Fourth Inverter

[0045] 1012 Fifth Inverter

[0046] 1013 Sixth Inverter

[0047] 1014 Seventh Inverter

[0048] 1015 Eighth Inverter

[0049] 1016 Ninth Inverter

[0050] 1017 Tenth Inverter

[0051] 1018 Eleventh Inverter

[0052] 1019 Twelfth Inverter

[0053] 1101 First Transistor

[0054] 1102 Second Transistor

[0055] 1103 Third Transistor

[0056] 1104 Fourth Transistor

[0057] 1105 Fifth Transistor

[0058] 1106 Sixth Transistor

[0059] 1107 Seventh Transistor

[0060] 1108 Eighth Transistor

[0061] 1109 Ninth Transistor

[0062] 1110 Tenth Transistor

[0063] 1111 Eleventh Transistor

[0064] 1112 Twelfth Transistor

[0065] 1113 The Thirteenth Transistor

[0066] 1114 Fourteenth Transistor

[0067] 1115 The Fifteenth Transistor

[0068] 1116 Sixteenth Transistor

[0069] 1117 Seventeenth Transistor

[0070] 1118 Eighteenth Transistor Detailed Implementation

[0071] The invention is described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention may be practiced in different ways and should not be limited to the embodiments set forth herein. The dimensions and relative dimensions of layers and regions may be enlarged in the drawings for clarity.

[0072] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure. It should be understood that spatial relative terms are intended to include different orientations of the device used or operated in addition to those shown in the figure. For example, if the device in the figure were flipped, an element described as “below” or “under” other elements or features would be oriented as “above” other elements or features.

[0073] Unless otherwise specified, the terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms should be understood to have the meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formalized manner, unless explicitly stated otherwise herein.

[0074] Below, refer to Figure 1 Figure 4 provides a detailed description of the write equalization detection circuit 1 and the write equalization detector 10 involved in the embodiments of the present invention.

[0075] Figure 1 This is a block diagram illustrating a specific structural example of the write equalization detection circuit 1 according to an embodiment of the present invention.

[0076] like Figure 1 As shown, the write equalization detection circuit 1 according to the embodiments of the present invention includes: a write equalization detector 10, a first comparator 21, a clock divider 31, a clock repeater 41, a second comparator 22, a DQS divider 32, and a DQS repeater 42. Furthermore, the memory according to the embodiments of the present invention includes the above-described write equalization detection circuit 1.

[0077] The first comparator 21 compares the first clock signal CK_T and the second clock signal CK_C, and outputs the result to the clock divider 31. The clock divider 31 then converts the signal obtained from the first comparator 21 into a half-frequency clock signal and outputs it to the clock repeater 41. The half-frequency clock signal obtained from the clock divider 31 is then transmitted through the clock repeater 41 to become the first half-frequency clock signal MCK_R1 and the second half-frequency clock signal MCK_F1, and output to the write equalization detector 10.

[0078] Furthermore, the second comparator 22 compares the first DQS signal DQS_T and the second DQS signal DQS_C, and outputs the obtained signal to the DQS divider 32. Then, the DQS divider 32 converts the signal obtained by the second comparator (22) into a half-frequency DQS signal and outputs it to the DQS repeater 42. Then, the half-frequency DQS signal obtained by the DQS divider 32 is transmitted through the DQS repeater 42 to become the first half-frequency DQS signal DQS_R1 and the second half-frequency DQS signal DQS_R2, and output to the write equalization detector 10.

[0079] Here, the first clock signal CK_T and the second clock signal CK_C, the first DQS signal DQS_T and the second DQS signal DQS_C are full-frequency signals. Figure 1 (shown as F in the diagram), the signals output by the first comparator 21 and the second comparator 22 are full-frequency signals ( Figure 1 (shown as F); the signals output by clock divider 31 and DQS divider 32 are half-frequency signals ( Figure 1 The signals MCK_R1 and MCK_F1 output by clock repeater 41 and DQS_R1 and DQS_R2 output by DQS repeater 42 are half-frequency signals (shown as F / 2). Figure 1 (shown as F / 2).

[0080] The write equalizer detector 10 takes the first half-frequency clock signal MCK_R1, the second half-frequency clock signal MCK_F1, the first half-frequency DQS signal DQS_R1, and the second half-frequency DQS signal DQS_R2 as inputs to generate first timing deviation information and second timing deviation information of the clock signal relative to the DQS signal, and outputs them to the controller through the DQ pin. The specific structure of the write equalizer detector 10 will be described in detail below.

[0081] Figure 2 This is a block diagram illustrating a specific structural example of the write equalization detector 10 according to an embodiment of the present invention.

[0082] like Figure 2As shown, the write equalization detector 10 involved in the embodiment of the present invention includes a first write equalization detection unit 101, a second write equalization detection unit 102, a first inverter 103, and a second inverter 104.

[0083] Specifically, a first half-frequency clock signal MCK_R1 is input to the first input terminal IN_A of the first write equalization detection unit 101, a second half-frequency clock signal MCK_F1 is input to the second input terminal IN_B of the first write equalization detection unit 101, and a first half-frequency DQS signal DQS_R1 is input to the third input terminal CK of the first write equalization detection unit 101. The first write equalization detection unit 101 uses the first half-frequency clock signal MCK_R1, the second half-frequency clock signal MCK_F1, and the first half-frequency DQS signal DQS_R1 as inputs to generate first timing deviation information of the clock signal relative to the DQS signal and outputs it through the Q pin.

[0084] In addition, the second write equalization detection unit 201 inputs a first half-frequency clock signal MCK_R1 to the fourth input terminal IN_A, inputs a second half-frequency clock signal MCK_F1 to the fifth input terminal IN_A, and inputs a second half-frequency DQS signal DQS_R2 to the sixth input terminal CK. The second write equalization detection unit 201 uses the first half-frequency clock signal MCK_R1, the second half-frequency clock signal MCK_F1, and the second half-frequency DQS signal DQS_R2 as inputs to generate second timing deviation information of the clock signal relative to the DQS signal and outputs it through the Q pin.

[0085] Furthermore, the first inverter 103 and the second inverter 104 are connected in series to the output terminal (Q pin) of the first write equalization detection unit 101 and the output terminal (Q pin) of the second write equalization detection unit 102. The first timing deviation information and the second timing deviation information are output to the controller via the first inverter 103 and the second inverter 104 and through the DQ pin.

[0086] Figure 3A , Figure 3B , Figure 3C This is a circuit diagram illustrating a specific structural example of the first write equalization detection unit 101 in the write equalization detector 10 according to an embodiment of the present invention.

[0087] like Figure 3A , Figure 3B , Figure 3CAs shown, the first write equalization detection unit 101 includes: a first crystal oscillator 1021, a second crystal oscillator 1022, a third inverter 1010, a fourth inverter 1011, a fifth inverter 1012, a sixth inverter 1013, a seventh inverter 1014, an eighth inverter 1015, a ninth inverter 1016, a tenth inverter 1017, an eleventh inverter 1018, a twelfth inverter 1019, a first transistor 1101, a second transistor 1102, and a third transistor 1019. Transistor 1103, transistor 1104, transistor 1105, transistor 1106, transistor 1107, transistor 1108, transistor 1109, transistor 1110, transistor 1111, transistor 1112, transistor 1113, transistor 1114, transistor 1115, transistor 1116, transistor 1117, and transistor 1118. The connection relationship of the above-mentioned components in the first write equalization detection unit 101 is as follows: Figure 3A , Figure 3B , Figure 3C As shown in the figure. Among them, the first transistor 1101, the second transistor 1102, the third transistor 1103, the fourth transistor 1104, and the seventeenth transistor 1117 are PMOS transistors; the fifth transistor 1105, the sixth transistor 1106, the seventh transistor 1107, the eighth transistor 1108, the ninth transistor 1109, the tenth transistor 1110, the eleventh transistor 1111, the twelfth transistor 1112, the thirteenth transistor 1113, the fourteenth transistor 1114, the fifteenth transistor 1115, the sixteenth transistor 1116, and the eighteenth transistor 1118 are NMOS transistors.

[0088] like Figure 3A As shown, the first half-frequency clock signal MCK_R1 is input from the first input terminal IN_A, output from terminal A after passing through the third inverter 1010 and the fourth inverter 1011, and output from terminal Ab after passing through the first crystal oscillator 1021 and the fifth inverter 1012. The second half-frequency clock signal MCK_F1 is input from the second input terminal IN_B, output from terminal B after passing through the sixth inverter 1013 and the seventh inverter 1014, and output from terminal Bb after passing through the second crystal oscillator 1022 and the eighth inverter 1015.

[0089] Then, as Figure 3BAs shown, the signal output from terminal A is input to the gate of the eleventh transistor 1111 and the gate of the fourteenth transistor 1114; the signal output from terminal Ab is input to the gate of the twelfth transistor 1112 and the gate of the thirteenth transistor 1113; the signal output from terminal B is input to the gate of the eighth transistor 1108 and the gate of the tenth transistor 1110; and the signal output from terminal Bb is input to the gate of the seventh transistor 1107 and the gate of the ninth transistor 1109. Furthermore, the first half-frequency DQS signal DQS_R1 is input to the gates (CLK) of the first transistor 1101, the fourth transistor 1104, the fifteenth transistor 1115, and the sixteenth transistor 1116.

[0090] Then, as Figure 3C As shown, the signal output from the output terminal Q_lat of the ninth inverter 1016 is input to the gate of the eighteenth transistor 1118, the signal output from the output terminal Qb_lat of the tenth inverter 1017 is input to the eleventh inverter 1018, and the first timing deviation information is output from the output terminal Q of the twelfth inverter 1019.

[0091] Furthermore, since the specific structure of the second write equalization detection unit 102 is similar to that of the first write equalization detection unit 101, the repeated description of the write equalization detection unit 102 is omitted here.

[0092] Figure 4A This is a timing diagram illustrating the first scenario of the write equalization training action performed by the write equalization detection circuit 1 according to an embodiment of the present invention. Figure 4B This is a timing diagram illustrating a second scenario of the write equalization training action performed by the write equalization detection circuit 1 according to an embodiment of the present invention.

[0093] like Figure 4A and Figure 4B As shown, regardless of the first or second scenario, the first timing deviation information and the second timing deviation information of the clock (CK) signal relative to the DQS signal can be output from the DQ pin of the equalization detector 10 without the need for a clock recovery circuit (i.e., without the need for a clock recovery circuit). Figure 9A , Figure 9B (CLK_restore in the context of CLK_restore).

[0094] Therefore, the write equalizer detector according to the present invention implements the recovery logic function (equivalent to the XOR function of MCK_R1 and MCK_F1) into the flip-flop NMOS branch of the write equalizer detector and uses half-frequency clock signals (MCK_R1 and MCK_F1) as its inputs. Thus, it can obtain the timing deviation information of the clock (CK) signal relative to the DQS signal without setting up a separate clock recovery circuit, thereby avoiding the limitation of the maximum operating frequency and additional phase error caused by the clock recovery circuit.

[0095] This invention has been described in detail, but the above embodiments are merely examples of all embodiments, and this invention is not limited thereto. Within the scope of this invention, embodiments can be freely combined, any constituent elements of each embodiment can be modified, or any constituent elements of each embodiment can be omitted.

[0096] Industrial practicality

[0097] The write equalization detector, write equalization detection circuit and memory of the present invention can be applied to high-speed DRAM memories such as LPDDR4 and DDR5.

Claims

1. A write equalization detector, disposed in a memory, comprising: The first write equalization detection unit inputs a first half-frequency clock signal to its first input terminal, inputs a second half-frequency clock signal to its second input terminal, and inputs a first half-frequency DQS signal to its third input terminal. The first write equalization detection unit uses the first half-frequency clock signal, the second half-frequency clock signal, and the first half-frequency DQS signal as inputs to generate and output first timing deviation information of the clock signal relative to the DQS signal. as well as The second write equalization detection unit inputs the first half-frequency clock signal to its fourth input terminal, the second half-frequency clock signal to its fifth input terminal, and the second half-frequency DQS signal to its sixth input terminal. Using the first half-frequency clock signal, the second half-frequency clock signal, and the second half-frequency DQS signal as inputs, the second write equalization detection unit generates and outputs second timing deviation information of the clock signal relative to the DQS signal. The first write equalization detection unit and the second write equalization detection unit each include: First crystal oscillator, second crystal oscillator, third inverter, fourth inverter, fifth inverter, sixth inverter, seventh inverter, eighth inverter, ninth inverter, tenth inverter, eleventh inverter, twelfth inverter, first transistor, second transistor, third transistor, fourth transistor, fifth transistor, sixth transistor, seventh transistor, eighth transistor, ninth transistor, tenth transistor, eleventh transistor, twelfth transistor, thirteenth transistor, fourteenth transistor, fifteenth transistor, sixteenth transistor, seventeenth transistor, and eighteenth transistor. The output of the third inverter is connected to the input of the fourth inverter, and the output of the first crystal oscillator is connected to the input of the fifth inverter. The output of the sixth inverter is connected to the input of the seventh inverter, and the output of the second crystal oscillator is connected to the input of the eighth inverter. The drain of the first transistor is connected to the drain of the second transistor, and is also connected to the gates of the third and sixth transistors, as well as the drain of the fifth transistor and the input of the ninth inverter. The drain of the fourth transistor is connected to the drain of the third transistor, and is also connected to the gates of the second and fifth transistors, and to the drain of the sixth transistor at the input of the tenth inverter. The source of the fifth transistor is connected to the drain of the seventh transistor and the drain of the eighth transistor; the source of the seventh transistor is connected to the drain of the eleventh transistor; the source of the eighth transistor is connected to the drain of the twelfth transistor; and the sources of the eleventh transistor and the twelfth transistor are connected to the drain of the fifteenth transistor. The source of the sixth transistor is connected to the drain of the ninth transistor and the drain of the tenth transistor; the source of the ninth transistor is connected to the drain of the thirteenth transistor; the source of the tenth transistor is connected to the drain of the fourteenth transistor; and the sources of the thirteenth transistor and the fourteenth transistor are connected to the drain of the fifteenth transistor. The first half-frequency clock signal is output from the first terminal after passing through the third inverter and the fourth inverter in sequence, and is output from the second terminal after passing through the first crystal oscillator and the fifth inverter in sequence. The second half-frequency clock signal passes sequentially through the sixth and seventh inverters and is output from the third terminal, and then passes sequentially through the second crystal oscillator and the eighth inverter and is output from the fourth terminal. In the first write equalization detection unit, the first half-frequency DQS signal is input to the gate of the first transistor, the gate of the fourth transistor, the gate of the fifteenth transistor, and the gate of the sixteenth transistor. In the second write equalization detection unit, the second half-frequency DQS signal is input to the gates of the first transistor, the fourth transistor, the fifteenth transistor, and the sixteenth transistor. The signal output from the first terminal is input to the gates of the eleventh transistor and the fourteenth transistor; the signal output from the second terminal is input to the gates of the twelfth transistor and the thirteenth transistor; the signal output from the third terminal is input to the gates of the eighth transistor and the tenth transistor; and the signal output from the fourth terminal is input to the gates of the seventh transistor and the ninth transistor. The output terminal of the ninth inverter is connected to the gate of the eighteenth transistor, the output terminal of the tenth inverter is connected to the input terminal of the eleventh inverter, the drain of the seventeenth transistor is connected to the drain of the eighteenth transistor and the input terminal of the twelfth inverter, and the gate of the seventeenth transistor is connected to the output terminal of the eleventh inverter. In the first write equalization detection unit, the output terminal of the twelfth inverter outputs the first timing deviation information. In the second write equalization detection unit, the output terminal of the twelfth inverter outputs the second timing deviation information.

2. The write equalization detector as described in claim 1, characterized in that, The first half-frequency clock signal and the second half-frequency clock signal are obtained by using a clock divider to convert the signal obtained by comparing the first clock signal and the second clock signal with the first comparator into a half-frequency clock signal, and then outputting it through a clock repeater. The first half-frequency DQS signal and the second half-frequency DQS signal are obtained by using a DQS divider to convert the signal obtained by comparing the first DQS signal and the second DQS signal with the second comparator into a half-frequency DQS signal and then outputting it through a DQS repeater.

3. The write equalization detector as described in claim 1 or 2, characterized in that, The output terminals of the first write equalization detection unit and the second write equalization detection unit also include a first inverter and a second inverter connected in series.

4. A write equalization detection circuit, comprising: Write equalization detector as claimed in any one of claims 1 to 3; A first comparator compares a first clock signal and a second clock signal; A clock divider that converts the signal obtained from the first comparator into a half-frequency clock signal; A clock repeater that outputs the half-frequency clock signal obtained by the clock divider to the write equalization detector via the clock repeater; A second comparator compares the first DQS signal and the second DQS signal; DQS divider, which converts the signal obtained from the second comparator into a half-frequency DQS signal; as well as The DQS repeater outputs the half-frequency DQS signal obtained from the DQS divider to the write equalization detector via the DQS repeater.

5. A memory comprising the write equalization detection circuit of claim 4.

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