Semiconductor memory device and method of boosting voltage of first and second wiring lines in semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of improving operation speed and a method of boosting voltage of a first wiring and a second wiring in the semiconductor storage device. The semiconductor storage device of the embodiments includes a first word line connected to a first memory cell, a second word line connected to a second memory cell, and a voltage generation circuit 14. The voltage generation circuit 14 supplies a voltage VOUT1 to a wiring LOUT1 electrically connected to the first word line and supplies a voltage VOUT2 to a wiring LOUT2 electrically connected to the second word line. The voltage generation circuit 14 includes a regulator 141_1 that outputs the voltage VOUT1 to the wiring LOUT1 and outputs a first signal corresponding to the voltage VOUT1, a regulator 141_2 that outputs the voltage VOUT2 to the wiring LOUT2 and outputs a second signal corresponding to the voltage VOUT2, and a switch circuit that maintains either a connection state or a block state between the wiring LOUT1 and the wiring LOUT2 based on at least either the first signal or the second signal.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on June 25, 2019, with application number 201910554490.2 and title "Semiconductor Memory Device".

[0003] [Related Applications]

[0004] This application claims priority to Japanese Patent Application No. 2018-239621 (filed on December 21, 2018). This application incorporates the entire contents of that basic application by reference. Technical Field

[0005] The implementation relates to a semiconductor memory device. Background Technology

[0006] Semiconductor memory devices with memory cells arranged in three dimensions are known. Summary of the Invention

[0007] The embodiment provides a semiconductor memory device that can improve operating speed.

[0008] A semiconductor memory device according to an embodiment includes: a first word line connected to a first memory cell; a second word line connected to a second memory cell; and a voltage generating circuit that supplies a first voltage to a first wiring electrically connected to the first word line and supplies a second voltage to a second wiring electrically connected to the second word line. The voltage generating circuit includes: a first regulator that outputs the first voltage to the first wiring line and outputs a first signal corresponding to the first voltage; a second regulator that outputs the second voltage to the second wiring line and outputs a second signal corresponding to the second voltage; and a switching circuit that maintains the first wiring line and the second wiring line in either a connected state or a blocked state based on at least one of the first signal or the second signal. Attached Figure Description

[0009] Figure 1 This is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0010] Figure 2 This is a circuit diagram of the blocks of the memory cell array in the first embodiment.

[0011] Figure 3 This is a cross-sectional view of a portion of the block in the first embodiment.

[0012] Figure 4This is a graph showing the available data and threshold voltage distribution of the memory cell transistor in the first embodiment.

[0013] Figure 5 This is a circuit diagram showing the configuration of the line decoder and driver in the first embodiment.

[0014] Figure 6 This is a diagram showing the configuration of the voltage generation circuit in the first embodiment.

[0015] Figure 7 This is a circuit diagram showing the configuration of the regulator group in the first embodiment.

[0016] Figure 8 This is a voltage waveform diagram showing the operation of the regulator group in the first embodiment.

[0017] Figure 9 This is a circuit diagram showing the configuration of the regulator group in the second embodiment.

[0018] Figure 10 This is a voltage waveform diagram showing the operation of the regulator group in the second embodiment.

[0019] Figure 11 This is a circuit diagram showing the configuration of the regulator group in the third embodiment.

[0020] Figure 12 This is a circuit diagram illustrating another first configuration example of the regulator group in the third embodiment.

[0021] Figure 13 This is a circuit diagram illustrating another second configuration example of the regulator group in the third embodiment.

[0022] Figure 14 This is a circuit diagram showing the configuration of the regulator group in the fourth embodiment.

[0023] Figure 15 This is a voltage waveform diagram showing the operation of the regulator group in the fourth embodiment.

[0024] Figure 16 This is a circuit diagram illustrating another configuration example of the regulator group in the fourth embodiment. Detailed Implementation

[0025] In the following description of the embodiments, constituent elements having the same function and structure are labeled with the same symbols. In addition, the embodiments shown below are illustrative devices or methods for embodying the technical concept of the embodiments, and do not specify the material, shape, structure, arrangement, etc. of the constituent parts as described below.

[0026] Each functional block can be implemented by hardware, computer software, or a combination of both. It is not necessary to distinguish between functional blocks as in the following example. For example, some functions can also be executed by functional blocks different from those illustrated. Furthermore, the illustrated functional blocks can be divided into more detailed functional sub-blocks. Here, as a semiconductor memory device, a three-dimensional stacked NAND (Not And) flash memory with memory cell transistors stacked on top of a semiconductor substrate is used as an example for explanation.

[0027] 1. First Implementation Method

[0028] The semiconductor memory device of the first embodiment will be described below.

[0029] 1.1 Composition of Semiconductor Memory Devices

[0030] use Figure 1 The configuration of the semiconductor memory device according to the first embodiment will be described. Figure 1 This is a block diagram showing the configuration of the semiconductor memory device according to the first embodiment.

[0031] The semiconductor memory device 10 is a non-volatile memory for storing data and has multiple memory cells. For example... Figure 1 As shown, the semiconductor memory device 10 includes a memory cell array 11, a row decoder 12, a driver 13, a voltage generation circuit 14, a sense amplifier 15, an address register 16, an instruction register 17, and a sequencer 18. Additionally, a controller 20 is connected externally to the semiconductor memory device 10 via a NAND bus, for example. The controller 20 accesses the semiconductor memory device 10 and controls it. Details of the NAND bus and the controller 20 are described below.

[0032] The memory cell array 11 comprises multiple blocks BLK0, BLK1, BLK2, ..., BLKn (n is an integer greater than or equal to 0) containing multiple non-volatile memory cells that correspond to rows and columns. Hereinafter, when denoted as block BLK, each block BLK0 to BLKn will be represented. The memory cell array 11 stores data provided by the controller 20. Details of the memory cell array 11 and the blocks BLK are described below.

[0033] Line decoder 12 selects any one of the blocks BLK, and then selects the word lines in the selected block BLK. The details of line decoder 12 are described below.

[0034] Driver 13 supplies voltage to the selected block BLK via line decoder 12.

[0035] The voltage generation circuit 14 generates various voltages required for writing, reading, and deleting data, and supplies them to the driver 13.

[0036] When reading data, the sensing amplifier 15 senses the data DAT read from the memory cell array 11 and performs the necessary calculations. Furthermore, it outputs the data DAT to the controller 20. When writing data, the sensing amplifier 15 transmits the write data DAT received from the controller 20 to the memory cell array 11.

[0037] Address register 16 stores the address ADD received from controller 20. Address ADD includes the block address of the block BLK that specifies the action object, and the page address of the word line indicating the action object within the specified block. Instruction register 17 stores the instruction CMD received from controller 20. Instruction CMD includes, for example, a write instruction that commands sequencer 18 to perform a write operation, and a read instruction that performs a read operation.

[0038] The sequencer 18 controls the operation of the semiconductor memory device 10 based on the instruction CMD stored in the instruction register 17. Specifically, the sequencer 18 controls the row decoder 12, driver 13, voltage generation circuit 14, and sense amplifier 15 based on the write instruction stored in the instruction register 17, and writes to the plurality of memory cell transistors specified by the address ADD. In addition, the sequencer 18 controls the row decoder 12, driver 13, voltage generation circuit 14, and sense amplifier 15 based on the read instruction stored in the instruction register 17, and reads from the plurality of memory cell transistors specified by the address ADD.

[0039] As described above, the controller 20 is connected to the semiconductor memory device 10 via a NAND bus. The NAND bus transmits and receives signals according to the NAND interface. Specifically, the NAND bus includes, for example, a bus for communication of chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, input / output (I / O) signals, and ready / busy signal R / Bn. The I / O signals are transmitted with an 8-bit bus width. The I / O signals facilitate communication of instructions (CMD), addresses (ADD), and data (DAT), etc.

[0040] Secondly, utilize Figure 1The configuration of controller 20 will be described below. Controller 20 includes host interface (I / F) circuit 21, built-in memory 22, processor (e.g., CPU (Central Processing Unit)) 23, buffer memory 24, NAND interface (I / F) circuit 25, and ECC (Error Checking and Correcting) circuit 26.

[0041] The host interface circuit 21 is connected to the host device (not shown) via the host bus. The host interface circuit 21 transmits commands and data received from the host device to the processor 23 and the buffer memory 24, respectively. In addition, the host interface circuit 21 responds to commands from the processor 23 by transmitting data from the buffer memory 24 to the host device.

[0042] The processor 23 controls the overall operation of the controller 20. For example, when the processor 23 receives a write command from the host device, it responds to the command by issuing a write command to the NAND interface circuit 25. The same applies to read and delete operations. In addition, the processor 23 performs various processes such as power averaging to manage the semiconductor memory device 10. Furthermore, the operation of the controller 20 described below can be implemented by the processor 23 executing software (or firmware), or it can be implemented by hardware.

[0043] The NAND interface circuit 25 is connected to the semiconductor memory device 10 via the NAND bus and is responsible for communication with the semiconductor memory device 10. Based on commands received from the processor 23, the NAND interface circuit 25 sends various signals to the semiconductor memory device 10 and receives various signals from the semiconductor memory device 10.

[0044] The buffer memory 24 temporarily stores data written or read. The buffer memory 24 may also include DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc.

[0045] The built-in memory 22 is a semiconductor memory such as DRAM or SRAM, and is used as the operating area of ​​the processor 23. The built-in memory 22 stores firmware or various management tables used to manage the semiconductor storage device 10.

[0046] ECC circuit 26 performs error detection and error correction processing related to the data stored in semiconductor memory device 10. That is, when data is written, ECC circuit 26 generates an error correction symbol and assigns it to the written data, and when data is read, it decodes it.

[0047] 1.1.1 Composition of memory cell array 11

[0048] As described above, the memory cell array 11 includes blocks BLK0 to BLKn. Here, the circuit configuration of one block BLK will be explained.

[0049] Figure 2 This is a circuit diagram of the block BLK of the memory cell array 11. As shown, the block BLK contains, for example, four serial cells SU0 to SU3. Hereinafter, each serial cell SU0 to SU3 will be referred to as a serial cell SU. Each serial cell SU contains multiple NAND strings NS.

[0050] Each NAND string NS contains, for example, eight memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Hereinafter, when referred to as memory cell transistor MT, each memory cell transistor MT0 to MT7 is indicated. The memory cell transistor (hereinafter also referred to as memory cell) MT has a control gate and a charge storage layer, and non-volatilely stores data. The memory cell transistor MT is connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0051] The gates of the select transistors ST1 in each string cell SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. Conversely, the gates of the select transistors ST2 in each string cell SU0 to SU3 are connected, for example, to a single select gate line SGS. The gates of the select transistors ST2 may also be connected to different select gate lines SGS0 to SGS3 for each string cell. Furthermore, the control gates of the memory cell transistors MT0 to MT7 in the string cells SU0 to SU3 within block BLK are connected to word lines WL0 to WL7, respectively.

[0052] Furthermore, the memory cell array 11 shares bit lines BL0 to BL(m-1) across multiple blocks BLK0 to BLKn. Here, m is a natural number greater than 2. Within the multiple string cells SU0 to SU3 in block BLK, each bit line BL is commonly connected to the drain of the select transistor ST1 of the NAND string NS located in the same column. That is, each bit line BL connects the NAND string NS across multiple string cells SU0 to SU3 in the same column. Furthermore, the sources of multiple select transistors ST2 are commonly connected to the source line SL. In other words, the string cell SU contains multiple NAND strings NS connected to different bit lines BL and connected to the same select gate line SGD.

[0053] In addition, block BLK contains multiple string units SU that are common to word lines WL.

[0054] Multiple memory cell transistors MT connected to a common word line WL within a serial cell SU are called a cell CU. The storage capacity of a cell CU varies correspondingly to the number of bits of data stored by the memory cell transistors MT. For example, a cell CU stores one page of data when each memory cell transistor MT stores 1 bit of data, two pages of data when storing 2 bits of data, and three pages of data when storing 3 bits of data.

[0055] Furthermore, the configuration of the memory cell array 11 is not limited to the configuration described above. For example, the number of string cells SU contained in each block BLK can be set to any number. The number of memory cell transistors MT and select gate transistors ST1 and ST2 contained in each NAND string NS can also be set to any number.

[0056] Secondly, the cross-sectional structure of a portion of the BLK block is explained. Figure 3 This is a cross-sectional view of a portion of the BLK block. As shown, multiple NAND strings NS are formed on the p-type well region 30. That is, on the well region 30, there are sequentially stacked wiring layers, such as a 4-layer wiring layer 31 that functions as the select gate line (SGS), an 8-layer wiring layer 32 that functions as word lines WL0 to WL7, and a 4-layer wiring layer 33 that functions as the select gate line (SGD). An insulating film (not shown) is formed between the stacked wiring layers.

[0057] A columnar conductor 34 is formed, penetrating these wiring layers 31, 32, and 33 to reach the well region 30. A gate insulating film 35, a charge storage film (insulating film) 36, and a block insulating film 37 are sequentially formed on the side of the conductor 34. Memory cell transistors MT and select transistors ST1 and ST2 are formed through these. The conductor 34 functions as a current path for the NAND string NS, becoming the channel region for forming each transistor. The upper end of the conductor 34 is connected via a contact plug 45 to a metal wiring layer 38, which functions as a bit line BL.

[0058] An n+ type impurity diffusion layer 39 is formed in the surface region of the well region 30. A contact plug 40 is formed on the diffusion layer 39 and is connected to a metal wiring layer 41 that functions as a source line SL. Furthermore, a p+ type impurity diffusion layer 42 is formed in the surface region of the well region 30. A contact plug 43 is formed on the diffusion layer 42 and is connected to a metal wiring layer 44 that functions as a well wiring CPWELL. The well wiring CPWELL is a wiring used to apply a potential to the conductor 34 via the well region 30.

[0059] The above composition is related to the record. Figure 3Multiple NAND strings are arranged in the orthogonal direction (depth direction) on the paper, and a string unit SU is formed by the collection of multiple NAND strings NS arranged in the depth direction.

[0060] Furthermore, the configuration of the memory cell array 11 can also be other configurations. That is, the configuration of the memory cell array 11 is described, for example, in U.S. Patent Application No. 12 / 407,403, entitled "Three-dimensional stacked non-volatile semiconductor memory", filed on March 19, 2009. Additionally, U.S. Patent Application No. 12 / 406,524, filed March 18, 2009, entitled "Three-dimensional stacked non-volatile semiconductor memory"; U.S. Patent Application No. 12 / 679,991, filed March 25, 2010, entitled "Non-volatile semiconductor memory device and method of manufacturing the same"; and U.S. Patent Application No. 12 / 532,030, filed March 23, 2009, entitled "Semiconductor memory and method for manufacturing the same" are described herein. The entire contents of these patent applications are incorporated herein by reference.

[0061] Furthermore, data deletion can be performed in units of block BLK or smaller units. Deletion methods are described, for example, in U.S. Patent Application No. 13 / 235,389, filed September 18, 2011, entitled "Non-Volatile Semiconductor Memory Device." Also described are U.S. Patent Application No. 12 / 694,690, filed January 27, 2010, entitled "Non-Volatile Semiconductor Memory Device." And also described are U.S. Patent Application No. 13 / 483,610, filed May 30, 2012, entitled "Non-Volatile Semiconductor Memory Device and Data Erassment Theory Thereof." These patent applications are incorporated herein by reference in their entirety.

[0062] 1.1.2 Threshold voltage distribution of memory cell transistors

[0063] Figure 4 This section shows the data available to the memory cell transistor MT in the first embodiment and its threshold voltage distribution. Here, the case where the memory cell has a TLC (Triple-Level Cell) configuration that stores 3 bits of data will be described.

[0064] like Figure 4 As shown, each memory cell transistor MT can store, for example, 3 bits of data based on its threshold voltage. This 3-bit data, starting from the lowest threshold voltage, is sequentially, for example, "111", "110", "100", "000", "010", "011", "001", and "101". The threshold voltage states of the memory cells storing this data, starting from the lowest state, are sequentially, for example, "Er" state (e.g., voltage below VA), "A" state (e.g., voltage above VA but below VB, VA < VB), "B" state (e.g., voltage above VB but below VC, VB < VC), "C" state (e.g., voltage above VC but below VD, VC < VD), "D" state (e.g., voltage above VD but below VE, VD < VE), "E" state (e.g., voltage above VE but below VF, VE < VF), "F" state (e.g., voltage above VF but below VG, VF < VG), and "G" state (e.g., voltage above VG). Furthermore, the relationship between the 3-bit data and the threshold voltage is not limited to this relationship; the relationship between the two can be appropriately selected.

[0065] The 3 bits of data stored in each memory cell transistor MT are called lower bits, middle bits, and upper bits, starting from the lower bit side. Furthermore, within the same string of cells SU, the set of lower bits stored in the cell CU, which contains multiple memory cells connected to the same word line, is called the lower page, the set of middle bits is called the middle page, and the set of upper bits is called the upper page. In other words, there are 3 pages allocated within the cell CU. Therefore, a "page" can also be defined as a portion of the memory space formed by the cell CU.

[0066] Data is written and read in units of pages or cells. In this example, since one string unit SU contains 8 word lines, each string unit SU contains (3×8) = 24 pages, and since one block BLK contains 4 string units SU, each block contains (24×4) = 96 pages.

[0067] 1.1.3 Composition of line decoder, driver and voltage generation circuit

[0068] Next, the configuration of the line decoder 12, driver 13, and voltage generation circuit 14 in the semiconductor memory device of the first embodiment will be described.

[0069] The voltage generation circuit 14 supplies various voltages, such as VUSEL, VSEL, and VSG, to the driver 13 for data writing, reading, and deletion. VUSEL is the voltage transmitted to the word line WL within the block BLK where the data is being written or read, but which is not the target word line. VSEL is the voltage transmitted to the word line WL within the block BLK where the data is being written or read. VSG is the voltage transmitted to the select gate line of the selected serial cell SU within the block BLK where the data is being written or read. The circuit configuration and operation of the voltage generation circuit 14 are described below.

[0070] In the following description, when the block, word line, and memory cell transistors are the objects of data writing or reading, they are referred to as select block, select word line, and select memory cell transistor (or select memory cell), respectively. Conversely, when the block, word line, and memory cell transistors are not the objects of data writing or reading, they are referred to as non-select block, non-select word line, and non-select memory cell transistor (or non-select memory cell), respectively.

[0071] 1.1.3.1 Line decoder and driver

[0072] Figure 5This is a circuit diagram showing the configuration of the line decoder 12 and driver 13 in the first embodiment.

[0073] Driver 13 includes drivers CGdv0 to CGdv7, drivers SGDdv0 to SGDdv3, and driver SGSdv. Hereinafter, when referred to as driver CGdv, each driver CGdv0 to CGdv7 is indicated; when referred to as driver SGDdv, each driver SGDdv0 to SGDdv3 is indicated. Each driver CGdv, driver SGDdv, and driver SGSdv can independently output the voltage supplied from the voltage generation circuit 14. Drivers CGdv0 to CGdv7 drive wirings CG0 to CG7 respectively. Drivers SGDdv0 to SGDdv3 drive wirings SGDL0 to SGDL3 respectively. Driver SGSdv drives wiring SGSL.

[0074] The line decoder 12 has multiple block decoders 12A_0 to 12A_m and multiple transmission transistor groups 12B_0 to 12B_m. The block decoders 12A_m and the transmission transistor groups 12B_m correspond to blocks BLKm. For example, in... Figure 5 In the example shown, the group of block decoder 12A_0 and transmission transistor group 12B_0 corresponds to block BLK0, and the group of block decoder 12A_1 and transmission transistor group 12B_1 corresponds to block BLK1. Hereinafter, when referred to as block decoder 12A, each block decoder 12A_0 to 12A_m will be represented; when referred to as transmission transistor group 12B, each transmission transistor group 12B_0 to 12B_m will be represented.

[0075] Block decoders 12A_0 to 12A_m receive row address signals from address register 16. The block decoder 12A selected according to the row address signal outputs a block selection signal BS. The block selection signal BS is supplied to the gates of multiple transmission transistors within the transmission transistor group 12B that selects the block.

[0076] The transfer transistor group 12B has multiple transfer transistors TRCO to TRC7, TRD0 to TRD3, and TRS. Wiring lines CG0 to CG7 are connected to word lines WL0 to WL7 via transfer transistors TRCO to TRC7, respectively. Wiring lines SGDL0 to SGDL3 are connected to select gate lines SGD0 to SGD3 via transfer transistors TRD0 to TRD3, respectively. Furthermore, wiring line SGSL is connected to select gate line SGS via transfer transistor TRS.

[0077] Each of the transmission transistors TRCO to TRC7 is turned on when a block select signal BS is supplied to the gate, transmitting the voltage supplied to the word lines WL0 to WL7 to the wirings CG0 to CG7, respectively. On the other hand, each of the transmission transistors TRCO to TRC7 is turned off when a block select signal BS is not supplied to the gate, and does not transmit the voltage supplied to the word lines WL0 to WL7 to the wirings CG0 to CG7, respectively.

[0078] Similarly, each of the transmission transistors TRD0 to TRD3 is turned on when a block selection signal BS is supplied to the gate, transmitting the voltage supplied to the wirings SGDL0 to SGDL3 to the selection gate lines SGD0 to SGD3, respectively. On the other hand, it is turned off when the block selection signal BS is not supplied to the gate, and the voltage supplied to the wirings SGDL0 to SGDL3 is not transmitted to the selection gate lines SGD0 to SGD3. Similarly, the transmission transistor TRS is turned on when a block selection signal BS is supplied to the gate, transmitting the voltage supplied to the wiring SGSL to the selection gate line SGS. On the other hand, it is turned off when the block selection signal BS is not supplied to the gate, and the voltage supplied to the wiring SGSL is not transmitted to the selection gate line SGS.

[0079] Using the driver 13 and line decoder 12 with the above configuration, the voltages VUSEL, VSEL and VSG supplied from the voltage generation circuit 14 are respectively supplied to the non-select word line WL, select word line WL and select gate line SGD of the selected block BLK via the block selection signal BS.

[0080] 1.1.3.2 Voltage Generation Circuit

[0081] Next, the voltage generation circuit 14 that supplies various voltages to the driver 13 will be described. Figure 6 This diagram illustrates the configuration of the voltage generation circuit 14 according to the first embodiment. The voltage generation circuit 14 includes, for example, a regulator group 14A that generates a voltage VUSEL supplied to the non-select word line during write or read operations, a regulator group 14B that generates a voltage VSEL supplied to the select word line, and a regulator group 14C that generates a voltage VSG supplied to the select gate line. Here, for example, we will illustrate the case where regulator group 14A supplies two voltages, VOUT1 and VOUT2, to the driver 13 as voltage VUSEL. Furthermore, in the following description, when referred to as voltage VOUT, each voltage VOUT1 or VOUT2 will be indicated.

[0082] Figure 7This is a circuit diagram showing the configuration of the regulator group 14A in the first embodiment. The regulator group 14A includes two regulators 141_1 and 141_2 and an equalization circuit (or switching circuit) 142. The voltage VSUP is the input voltage supplied to the regulators 141_1 and 141_2 to generate voltages VOUT1 and VOUT2.

[0083] The circuit connection of regulator 141_1 will be described below.

[0084] The regulator 141_1 includes a low-voltage amplifier circuit AP1, n-channel MOS (Metal Oxide Semiconductor) field-effect transistors (hereinafter, nMOS transistors) TSa1, TCa1, TTa1 and depletion-type (hereinafter, D-type) nMOS transistor TOa1, resistor Ra1, and variable resistor VR1.

[0085] A voltage VSUP is supplied to the drain of the D-type nMOS transistor TOa1. The source of the nMOS transistor TOa1 is connected to the ground voltage terminal GND via a variable resistor VR1. The node between the source of the nMOS transistor TOa1 and the variable resistor VR1 is connected to wiring LOUT1. Wiring LOUT1 outputs voltage VOUT1.

[0086] Additionally, a voltage VSUP is supplied to the drain of nMOS transistor TSa1 via resistor Ra1. The source of nMOS transistor TSa1 is connected to ground voltage terminal GND via nMOS transistors TCa1 and TTa1 connected in series. The node between the source of nMOS transistor TSa1 and the drain of nMOS transistor TCa1 is connected to the gate of nMOS transistor TOa1.

[0087] A reference voltage VREF is input to the inverting input (-) terminal (first input terminal) of amplifier circuit AP1. A variable resistor VR1 is connected to the resistance control terminal (second input terminal) of amplifier circuit AP1, and a voltage VS1 is input thereon. The output terminal of amplifier circuit AP1 is connected to the gate of nMOS transistor TTa1. The node between the output terminal of amplifier circuit AP1 and the gate of nMOS transistor TTa1 is connected to the gate of nMOS transistor TDb121 in equalization circuit 142.

[0088] Next, the circuit connection of regulator 141_2 will be described.

[0089] The regulator 141_2 includes a low-voltage amplifier circuit AP2, nMOS transistors TSa2, TCa2, TTa2 and D-type nMOS transistor TOa2, resistor Ra2 and variable resistor VR2.

[0090] A voltage VSUP is supplied to the drain of the D-type nMOS transistor TOa2. The source of the nMOS transistor TOa2 is connected to the ground voltage terminal GND via a variable resistor VR2. The node between the source of the nMOS transistor TOa2 and the variable resistor VR2 is connected to wiring LOUT2. Wiring LOUT2 outputs voltage VOUT2.

[0091] Additionally, a voltage VSUP is supplied to the drain of nMOS transistor TSa2 via resistor Ra2. The source of nMOS transistor TSa2 is connected to ground voltage terminal GND via nMOS transistors TCa2 and TTa2 connected in series. The node between the source of nMOS transistor TSa2 and the drain of nMOS transistor TCa2 is connected to the gate of nMOS transistor TOa2.

[0092] A reference voltage VREF is input to the inverting input (-) terminal (first input terminal) of amplifier circuit AP2. A variable resistor VR2 is connected to the resistance control terminal (second input terminal) of amplifier circuit AP2, and a voltage VS2 is input thereon. The output terminal of amplifier circuit AP2 is connected to the gate of nMOS transistor TTa2. The node between the output terminal of amplifier circuit AP2 and the gate of nMOS transistor TTa2 is connected to the gate of nMOS transistor TDb122 of equalization circuit 142.

[0093] Next, the circuit connection of the equalization circuit 142 will be described.

[0094] The equalization circuit 142 includes nMOS transistors TDb121, TDb122, TCb12, a D-type nMOS transistor TEQ, and a resistor Rb12. nMOS transistors TDb121 and TDb122 have the same transistor characteristics.

[0095] A voltage VSUP is supplied to the drain of nMOS transistor TCb12 via resistor Rb12. The node between the drain of nMOS transistor TCb12 and resistor Rb12 is connected to the gate of nMOS transistor TEQ. The source (or drain) of nMOS transistor TEQ is connected to wiring LOUT1, and the drain (or source) of nMOS transistor TEQ is connected to wiring LOUT2. Furthermore, the source of nMOS transistor TCb12 is connected to ground voltage terminal GND via nMOS transistors TDb121 and TDb122 connected in parallel. In other words, nMOS transistors TDb121 and TDb122 are connected in parallel between the source of nMOS transistor TCb12 and ground voltage terminal GND.

[0096] In the regulators 141_1, 141_2 and the equalization circuit 142, the following relationship holds.

[0097] [{Rb12·(channel width of TDb12) / (channel length of TDb12)} / {Ra1·(channel width of TDa1) / (channel length of TDa1)}]>1

[0098] Here, Rb12 and Ra1 represent the resistance values, respectively. TDb12 represents TDb121 or TDb122.

[0099] In addition, Ra1 = Ra2

[0100] (Channel width of TTa1) = (Channel width of TTa2)

[0101] (Channel length of TTa1) = (Channel length of TTa2)

[0102] Here, Ra2 represents the resistance value.

[0103] Next, the operation of the regulator group 14A in the first embodiment will be explained. Figure 8 This is a voltage waveform diagram showing the operation of the regulator group 14A in the first embodiment.

[0104] When the enable signal REG_EN input to the gates of nMOS transistors TSa1 and TSa2 is set (e.g., "H" (power supply voltage)), nMOS transistors TSa1 and TSa2 become switched on. This initiates the operation of regulators 141_1 and 141_2.

[0105] nMOS transistor TCa1 is a voltage-resistant transistor used to protect nMOS transistor TTa1 from high-voltage damage. A clamp signal CLA is input to the gate of nMOS transistor TCa1 to limit the current flowing through it. Similarly, nMOS transistor TCa2 is a voltage-resistant transistor used to protect nMOS transistor TTa2 from high-voltage damage. A clamp signal CLA is input to the gate of nMOS transistor TCa2 to limit the current flowing through it. Alternatively, if nMOS transistors TTa1 and TTa2 are high-voltage transistors, they may not be required.

[0106] The voltage VS1 of the resistance control terminal of the variable resistor VR1 is input to the non-inverting input (+) terminal of amplifier circuit AP1, and the reference voltage VREF is input to the inverting input (-) terminal. The reference voltage VREF is set to a value higher than the ground voltage (e.g., 1.2V). Amplifier circuit AP1 amplifies the voltage difference between voltage VS1 and reference voltage VREF and outputs voltage AO1. Voltage AO1 changes continuously with changes in voltage VS1 (or voltage VOUT1).

[0107] The voltage (or the first signal) AO1 output from amplifier circuit AP1 is input to the gates of nMOS transistor TTa1 and nMOS transistor TDb121. nMOS transistor TDb121 functions as a pull-down circuit to reduce the gate voltage Gb12 of nMOS transistor TEQ to "L" (e.g., ground voltage).

[0108] The voltage VS2 of the variable resistor VR2 is input to the non-inverting input (+) terminal of amplifier circuit AP2, and the reference voltage VREF is input to the inverting input (-) terminal. Amplifier circuit AP2 amplifies the voltage difference between voltage VS2 and reference voltage VREF and outputs voltage AO2. Voltage AO2 changes continuously with the change of voltage VS2 (or voltage VOUT2).

[0109] The voltage (or the second signal) AO2 output from amplifier circuit AP2 is input to the gates of nMOS transistor TTa2 and nMOS transistor TDb122. nMOS transistor TDb122 functions as a pull-down circuit to reduce the gate voltage Gb12 of nMOS transistor TEQ to "L".

[0110] In addition, variable resistor VR1 can be set to the final voltage (or target voltage) of voltage VOUT1, and variable resistor VR2 can be set to the final voltage of voltage VOUT2. Therefore, variable resistors VR1 and VR2 are set to boost voltage VOUT1 and voltage VOUT2 to the target voltage respectively.

[0111] In the aforementioned configuration, when the regulators 141_1 and 141_2 begin operation, the D-type nMOS transistor TEQ is in the ON state; therefore, as Figure 8 As shown, voltages VOUT1 and VOUT2 rise with the same voltage and the same slope. Furthermore, voltages VOUT1 and VOUT2 reach the target voltage of VOUT1. When voltage VOUT1 reaches the target voltage, voltage AO1 from amplifier circuit AP1 becomes "H", and nMOS transistors TTa1 and TDb121 switch to the ON state. Consequently, the gate voltage Gb12 of nMOS transistor TEQ decreases, and nMOS transistor TEQ switches to the OFF state. Thus, the connection between wiring LOUT1 and wiring LOUT2 changes from a connected state to a blocked state.

[0112] Subsequently, the voltage VOUT2 continues to rise until it reaches the target voltage. When the voltage VOUT2 reaches the target voltage, the voltage AO2 output from the amplifier circuit AP2 becomes "H", and the nMOS transistor TTa2 switches to the ON state.

[0113] Furthermore, the gate voltage Ga1 of nMOS transistor TOa1, after reaching voltage VOUT1, is fixed at a voltage lower than VOUT1. The gate voltage Ga2 of nMOS transistor TOa2, after reaching voltage VOUT2, is fixed at a voltage lower than VOUT2. The gate voltage Gb12 of nMOS transistor TEQ, after reaching voltage VOUT1, gradually decreases to "L".

[0114] 1.2 Effects of the first embodiment

[0115] According to the first embodiment, a semiconductor memory device capable of improving operating speed can be provided.

[0116] The effects of the first embodiment will now be described in detail. Generally, in semiconductor memory devices with memory cells arranged in three dimensions, the load capacitance of the word line WL connected to the gate of the memory cell transistor is relatively large. Furthermore, with each generation, as the number of memory cell layers or the capacity of the mounted memory increases, the load capacitance of the word line WL tends to increase. Therefore, a larger drive current is required to raise the voltage of the word line to the target voltage.

[0117] For example, when a voltage VOUT1 and a higher voltage VOUT2 are supplied to the word line from the regulator in the voltage generation circuit, in order to ensure a stable rise in voltages VOUT1 and VOUT2, during the period when voltage VOUT1 rises to the target voltage, the first line of the transmission voltage VOUT1 and the second line of the transmission voltage VOUT2 are made conductive, so that voltages VOUT1 and VOUT2 rise at the same voltage and the same slope. When voltage VOUT1 reaches the target voltage, the first line and the second line are made disconnected, and then voltage VOUT2 is allowed to rise to the target voltage. Hereinafter, the action of making the first line and the second line conductive will be called the equalization operation.

[0118] When the voltage VOUT1, which serves as the supply target voltage of regulator 141_1, is lower than the voltage VOUT2, which serves as the supply target voltage of regulator 141_2, it is preferable that the equalization operation continues during the period of boosting voltages VOUT1 and VOUT2 until the voltages of the first wiring and the second wiring reach voltage VOUT1, and ends immediately after reaching voltage VOUT1.

[0119] For example, one could consider installing the comparator and regulator 141_1 and 141_2, which are used to detect the voltages of the first and second wirings, separately, and based on their outputs, managing the end point of the balancing operation during the boosting of voltages VOUT1 and VOUT2.

[0120] Generally, in equalization operations using the comparator output, a non-detection region must be set for the signal input to the comparator to avoid false detections. If this non-detection region is set too large, the equalization operation may end prematurely during the voltage VOUT1 and voltage VOUT2 boosting process. On the other hand, if the non-detection region is set too small, the equalization operation may end at an inappropriate time.

[0121] Furthermore, during the equalization operation using the comparator's output, the gate of the switching circuit performing the equalization operation is digitally disconnected according to the comparator's output. At this time, the load capacitance of the word line is relatively large. Therefore, immediately after the equalization operation ends, the voltage waveform of voltage VOUT1 may experience a delay in rising or a dip in the voltage waveform due to the charging load of the word line.

[0122] Therefore, in the first embodiment, a regulator 141_1 outputs a voltage VOUT1 to wiring LOUT1, a regulator 141_2 outputs a voltage VOUT2 to wiring LOUT2, and an equalization circuit (or switching circuit) 142 maintains wiring LOUT1 and wiring LOUT2 in a connected or blocked state. Regulator 141_1 outputs a voltage AO1 (first signal) corresponding to voltage VOUT1, and regulator 141_2 outputs a voltage AO2 (second signal) corresponding to voltage VOUT2. The equalization circuit 142 maintains either a connected or blocked state based on at least one of the signals of voltage AO1 or AO2 output from regulator 141_1 or 141_2.

[0123] The voltages AO1 or AO2 output from regulators 141_1 or 141_2 are analog signals that differ from the digital signals output from comparators and change continuously. In the first embodiment, by switching the connection and blocking states in the equalization circuit 142 based on the voltages AO1 or AO2, which are analog signals, the equalization operation can continue until the voltage VOUT1 substantially reaches the target voltage, and situations that prevent the voltage VOUT2 from rising to the target voltage can be suppressed.

[0124] In other words, in the first embodiment, the analog signal output from the regulator is directly input to the equalization circuit as a detection signal to end the equalization operation. Therefore, the equalization operation can be continued during the period when equalization operation is needed, and the equalization operation can be ended when equalization operation is not needed.

[0125] In addition, as mentioned above, during the equalization operation using the comparator's output, the gate of the switching circuit that performs the equalization operation is digitally disconnected according to the comparator's output. Therefore, immediately after the equalization operation ends, the voltage waveform of voltage VOUT1 may experience a delay in rising or a dip in the voltage waveform due to the charging load of the word line.

[0126] In contrast, in the first embodiment, the equalization operation can be terminated at the appropriate time by using a continuously changing analog signal, thereby reducing the occurrence of delays or dips in the voltage waveform of the voltage VOUT1 output from the regulator 141_1.

[0127] As described above, the semiconductor memory device according to the first embodiment can supply the voltage required for data writing and reading operations earlier and more stably, thereby improving the operating speed.

[0128] 2. Second Implementation Method

[0129] Next, the semiconductor memory device of the second embodiment will be described. The second embodiment is... Figure 7 The equalization circuit in the first embodiment shown is supplemented with an equalization end determination circuit. In the second embodiment, the differences from the first embodiment will be mainly explained.

[0130] 2.1 Voltage Generation Circuit

[0131] The voltage generation circuit 14 of the second embodiment includes a regulator group 14Aa. Figure 9 This is a circuit diagram showing the configuration of the regulator group 14Aa in the second embodiment. The regulator group 14Aa includes two regulators 141_1 and 141_2, an equalization circuit 142A, and an equalization end determination circuit 143.

[0132] The circuit connection of the equalization circuit 142A is described below.

[0133] Connect nMOS transistor TSb12 between the drain of nMOS transistor TCb12 and one end of resistor Rb12. Supply voltage VSUP to the other end of resistor Rb12.

[0134] Next, the circuit connection of the equalization termination determination circuit 143 will be described.

[0135] The equalization termination determination circuit 143 includes a comparator (or electric shifter) CP1, a latch circuit LA1, an AND gate circuit AD1, and an electric shifter RS1. The node between the drains of nMOS transistors TDb121 and TDb122 and the source of nMOS transistor TCb12 is connected to the input of comparator CP1. The output of comparator CP1 is connected to the first input of latch circuit LA1, and a latch enable signal LAT_EN is input to the second input of latch circuit LA1. The output of latch circuit LA1 is connected to the first input of AND gate circuit AD1. An enable signal REG_EN is input to the second input of AND gate circuit AD1. The output of AND gate circuit AD1 is connected to the input of electric shifter RS1. Furthermore, the output of electric shifter RS1 is connected to the gate of nMOS transistor TSb12.

[0136] Here, signal Gb12_CL is the voltage input to the input terminal of comparator CP1 from the node between the drains of nMOS transistors TDb121 and TDb122 and the source of nMOS transistor TCb12. Signal FLG is the voltage input to the first input terminal of latch circuit LA1 from the output terminal of comparator CP1. Latch enable signal LAT_EN is the voltage input to the second input terminal of latch circuit LA1. Enable signal REG_EN is the signal input to the second input terminal of AND gate circuit AD1. Equalization end signal (or third signal) EQ_EN is the voltage input to the input terminal of electric shifter RS1 from the output terminal of AND gate circuit AD1. Other circuit connections of regulator group 14Aa are... Figure 7 The circuits shown are the same.

[0137] Next, the operation of the regulator group 14Aa in the second embodiment will be explained. Figure 10 This is a voltage waveform diagram showing the operation of the regulator group 14Aa in the second embodiment.

[0138] First, at time t1, the enable signal REG_EN input to the gates of nMOS transistors TSa1 and TSa2 is set to an off state (e.g., "H"), turning on nMOS transistors TSa1 and TSa2. This initiates the operation of regulators 141_1 and 141_2. Furthermore, the enable signal REG_EN input to the second input of AND gate AD1 is set to an off state (e.g., "H"), initiating the operation of the equalization end determination circuit 143.

[0139] Secondly, voltages VOUT1, VOUT2, and gate voltage Gb12 rise, and at time t2, the flag signal FLG changes from "L" to "H". Then, at time t3, the latch enable signal LAT_EN, input to the second input of the latch circuit LA1, changes from "L" to "H".

[0140] Subsequently, when voltage VOUT1 reaches the target voltage, nMOS transistors TTa1 and TDb121 switch to the ON state. As a result, the gate voltage Gb12 of nMOS transistor TEQ decreases, and nMOS transistor TEQ becomes OFF, changing the connection state between wiring LOUT1 and wiring LOUT2 from ON to OFF. At this time, at time t4, the flag signal FLG changes from "H" to "L". When the flag signal FLG changes to "L", the equalization end signal EQ_EN changes from "H" to "L".

[0141] Subsequently, the equalization end signal EQ_EN (“L”) is input to the gate of nMOS transistor TSb12 via the electric shifter RS1. This turns nMOS transistor TSb12 off, blocking the current flowing to resistor Rb12. Other operations are the same as in the first embodiment described above.

[0142] 2.2 Effects of the second embodiment

[0143] According to the second embodiment, the same as the first embodiment, a semiconductor memory device capable of improving operating speed can be provided.

[0144] Furthermore, the second embodiment includes an equalization end determination circuit 143 and an nMOS transistor TSb12 disposed within the equalization circuit 142A. The equalization end determination circuit 143 detects the end of the equalization operation in the equalization circuit 142A and outputs an equalization end signal EQ_EN. The equalization operation refers to the operation of connecting (or conducting) wiring LOUT1 and wiring LOUT2.

[0145] When the equalization end determination circuit 143 detects the end of the equalization operation, that is, when the nMOS transistor TEQ becomes off, the equalization end signal EQ_EN input to the gate of the nMOS transistor TSb12 changes from "H" to "L". As a result, the nMOS transistor TSb12 becomes off, blocking the current flowing to the resistor Rb12. In other words, in the second embodiment, the equalization operation in the equalization circuit 142A can be stopped as soon as the voltage VOUT1 rises to the target voltage, reducing the current flowing to the resistor Rb12. Other effects are the same as in the first embodiment.

[0146] 3. Third Implementation Method

[0147] Next, the semiconductor memory device of the third embodiment will be described. In the first and second embodiments, the generation of two voltages VOUT1 and VOUT2 as voltage VUSEL is shown, but in the third embodiment, the generation of three voltages VOUT1, VOUT2, and VOUT3 is shown. Hereinafter, when referred to as voltage VOUT, each voltage VOUT1, VOUT2, and VOUT3 will be indicated. Furthermore, the regulator group in the third embodiment includes an equalization termination determination circuit. In the third embodiment, the differences from the second embodiment will be mainly described.

[0148] 3.1 Voltage Generation Circuit

[0149] The voltage generation circuit 14 of the third embodiment includes a regulator group 14Ab. Figure 11 This is a circuit diagram showing the configuration of the regulator group 14Ab in the third embodiment. The regulator group 14Ab includes three regulators 141_1, 141_2, and 141_3, equalization circuits 142A_1, 142A_2, and 142A_3, and equalization end determination circuits C13, C12, and C23.

[0150] like Figure 11 As shown, the voltage AO1 output from amplifier circuit AP1 is connected to the gate of nMOS transistor TDb132 in equalization circuit 142A_1, and also to the gate of nMOS transistor TDb121 in equalization circuit 142A_2. The voltage AO2 output from amplifier circuit AP2 is connected to the gate of nMOS transistor TDb122 in equalization circuit 142A_2, and also to the gate of nMOS transistor TDb231 in equalization circuit 142A_3. Furthermore, the output voltage AO3 of amplifier circuit AP3 is connected to the gate of nMOS transistor TDb131 in equalization circuit 142A_1, and also to the gate of nMOS transistor TDb232 in equalization circuit 142A_3.

[0151] A balance termination determination circuit C13 is connected between the drains of nMOS transistors TDb131 and TDb132 and the gate of nMOS transistor TSb13. A balance termination determination circuit C12 is connected between the drains of nMOS transistors TDb121 and TDb122 and the gate of nMOS transistor TSb12. A balance termination determination circuit C23 is connected between the drains of nMOS transistors TDb231 and TDb232 and the gate of nMOS transistor TSb23.

[0152] Furthermore, the nMOS transistors TOa1, TOa2, and TOa3 of regulators 141_1, 141_2, and 141_3 output voltages VOUT1, VOUT2, and VOUT3 respectively via wiring LOUT1, LOUT2, and LOUT3.

[0153] exist Figure 10 In the regulator group 14Ab shown, the following relationship holds.

[0154] [{Rb12·(channel width of TDb12) / (channel length of TDb12)} / {Ra1·(channel width of TDa1) / (channel length of TDa1)}]>1

[0155] Here, Rb12 and Ra1 represent the resistance values, respectively. TDb12 represents TDb121 or TDb122.

[0156] In addition, Ra1 = Ra2 = Ra3

[0157] (Channel width of TTa1) = (Channel width of TTa2) = (Channel width of TTa3)

[0158] (Channel length of TTa1) = (Channel length of TTa2) = (Channel length of TTa3)

[0159] Rb13 = Rb12 = Rb23

[0160] (Channel width of TDb13) = (Channel width of TDb12) = (Channel width of TDb23)

[0161] (Channel length of TDb13) = (Channel length of TDb12) = (Channel length of TDb23)

[0162] Here, Ra2, Ra3, Rb13, Rb12, and Rb23 represent resistance values, respectively. TDb13 represents TDb131 or TDb132, TDb12 represents TDb121 or TDb122, and TDb23 represents TDb231 or TDb232.

[0163] The regulator group 14Ab in this third embodiment is to... Figure 9 The regulator group 14Aa shown generates two voltages VOUT1 and VOUT2 and is used to generate three voltages VOUT1, VOUT2 and VOUT3. The operation of the regulator group 14Ab is omitted.

[0164] 3.2 Another example of a voltage generation circuit configuration

[0165] Next, another configuration example of the regulator group 14Ab provided in the voltage generating circuit 14 of the third embodiment will be described. The voltage generating circuit 14 of the third embodiment includes regulator groups 14Ac or 14Ad.

[0166] 3.2.1 Regulator Group 14Ac

[0167] Figure 12 This is a circuit diagram showing the configuration of regulator group 14Ac. Regulator group 14Ac consists of drive circuits 144_1, 144_2, and 144_3 that respectively add drive voltages VOUT1, VOUT2, and VOUT3 to regulator group 14Ab.

[0168] like Figure 12 As shown, drive circuits 144_1, 144_2, and 144_3 are added to regulators 141_1, 141_2, and 141_3, respectively. Drive circuit 144_1 includes nMOS transistors TSc1, TCC1, TDC1, a D-type nMOS transistor TOC1, a ramp-up termination determination circuit C1, and a resistor Rc1. Drive circuit 144_2 includes nMOS transistors TSc2, TCC2, TDC2, a D-type nMOS transistor TOC2, a ramp-up termination determination circuit C2, and a resistor Rc2. Furthermore, drive circuit 144_3 includes nMOS transistors TSc3, TCC3, TDC3, a D-type nMOS transistor TOC3, a ramp-up termination determination circuit C3, and a resistor Rc3. Hereinafter, when referred to as drive circuit 144, each drive circuit 144_1, 144_2, and 144_3 will be indicated.

[0169] The circuit connection of the drive circuit 144_1 will be described below.

[0170] A voltage VSUP is supplied to the drain of the D-type nMOS transistor TOc1. The source of the nMOS transistor TOc1 is connected to wiring LOUT1.

[0171] A voltage VSUP is supplied to the drain of nMOS transistor TSC1 via resistor Rc1. The source of nMOS transistor TSC1 is connected to ground via nMOS transistors TCc1 and TDc1 connected in series. The node between the source of nMOS transistor TSC1 and the drain of nMOS transistor TCc1 is connected to the gate of nMOS transistor TDc1. Furthermore, the gate of nMOS transistor TDc1 is connected to the output terminal of amplifier circuit AP1.

[0172] The ramp-up termination determination circuit C1 has the same circuit configuration as the equalization termination determination circuit 143. The node between the source of nMOS transistor TCc1 and the drain of nMOS transistor TDc1 is connected to the input terminal of comparator CP1 of the ramp-up termination determination circuit C1. The output terminal of the electric shifter RS1 of the ramp-up termination determination circuit C1 is connected to the gate of nMOS transistor TSc1.

[0173] Next, the circuit connection of the drive circuit 144_2 will be described.

[0174] A voltage VSUP is supplied to the drain of the D-type nMOS transistor TOc2. The source of the nMOS transistor TOc2 is connected to wiring LOUT2.

[0175] A voltage VSUP is supplied to the drain of nMOS transistor TSC2 via resistor Rc2. The source of nMOS transistor TSC2 is connected to ground via nMOS transistors TCc2 and TDc2 connected in series. The node between the source of nMOS transistor TSC2 and the drain of nMOS transistor TCc2 is connected to the gate of nMOS transistor TDc2. Furthermore, the gate of nMOS transistor TDc2 is connected to the output terminal of amplifier circuit AP2.

[0176] The ramp-up termination determination circuit C2 has the same circuit configuration as the equalization termination determination circuit 143. The node between the source of nMOS transistor TCc2 and the drain of nMOS transistor TDc2 is connected to the input of comparator CP1 of the ramp-up termination determination circuit C2. The output of the electric shifter RS1 of the ramp-up termination determination circuit C2 is connected to the gate of nMOS transistor TSc2.

[0177] Next, the circuit connection of the drive circuit 144_3 will be described.

[0178] A voltage VSUP is supplied to the drain of the D-type nMOS transistor TOc3. The source of the nMOS transistor TOc3 is connected to wiring LOUT3.

[0179] A voltage VSUP is supplied to the drain of nMOS transistor TSc3 via resistor RC3. The source of nMOS transistor TSc3 is connected to ground GND via nMOS transistors TCC3 and TDC3 connected in series. The node between the source of nMOS transistor TSc3 and the drain of nMOS transistor TCC3 is connected to the gate of nMOS transistor TDC3. Furthermore, the gate of nMOS transistor TDC3 is connected to the output terminal of amplifier circuit AP3.

[0180] The ramp-up termination determination circuit C3 has the same circuit configuration as the equalization termination determination circuit 143. The node between the source of nMOS transistor TCc3 and the drain of nMOS transistor TDc3 is connected to the input terminal of comparator CP1 of the ramp-up termination determination circuit C3. The output terminal of the electric shifter RS1 of the ramp-up termination determination circuit C3 is connected to the gate of nMOS transistor TSc3.

[0181] The other circuit configurations of the regulator group 14Ac are similar to Figure 11 The circuit configuration of the regulator group 14Ab shown is the same.

[0182] Next, the operation of regulator group 14Ac will be explained.

[0183] The drive circuit 144_1 operates during the period when voltage VOUT1 rises to the target voltage, driving wiring LOUT1. Therefore, voltage VOUT1 reaches the target voltage in a shorter time compared to the first and second embodiments. Similarly, drive circuits 144_2 and 144_3 operate during the period when voltages VOUT2 and VOUT3 respectively rise to the target voltages, driving wiring LOUT2 and LOUT3 respectively. Therefore, voltages VOUT2 and VOUT3 reach the target voltage in a shorter time compared to the first and second embodiments.

[0184] When voltage VOUT1 reaches the target voltage, voltage AO1 from amplifier circuit AP1 becomes "H", and nMOS transistor TDc1 switches to the ON state. Consequently, the gate voltage Gc1 of nMOS transistor TOc1 decreases, and nMOS transistor TOc1 becomes OFF. Thus, the boosting of voltage VOUT1 using drive circuit 144_1 stops.

[0185] Additionally, the ramp-up end determination circuit C1 within the drive circuit 144_1 detects whether the voltage VOUT1 reaches the target voltage, and determines or denies the ramp-up end signal RUP_EN1. That is, when the voltage VOUT1 reaches the target voltage, the ramp-up end determination circuit C1 outputs the determined ramp-up end signal RUP_EN1 (e.g., "L") to the gate of the nMOS transistor TSC1. When the nMOS transistor TSC1 receives the ramp-up end signal RUP_EN1 ("L"), it switches to an off state. This blocks the current flowing to the resistor Rc1.

[0186] Similarly, when voltage VOUT2 reaches the target voltage, the voltage AO2 output from amplifier circuit AP2 becomes "H", and nMOS transistor TDc2 switches to the ON state. Consequently, the gate voltage Gc2 of nMOS transistor TOc2 decreases, and nMOS transistor TOc2 becomes OFF. Thus, the boosting of voltage VOUT2 using drive circuit 144_2 stops.

[0187] Additionally, the ramp-up end determination circuit C2 within the drive circuit 144_2 detects whether the voltage VOUT2 has reached the target voltage, determining or denying the ramp-up end signal RUP_EN2. That is, when the voltage VOUT2 reaches the target voltage, the ramp-up end determination circuit C2 outputs the determined ramp-up end signal RUP_EN2 (e.g., "L") to the gate of the nMOS transistor TSc2. When the nMOS transistor TSc2 receives the ramp-up end signal RUP_EN2 ("L"), it switches to an off state. This blocks the current flowing to the resistor RC2.

[0188] Similarly, when voltage VOUT3 reaches the target voltage, the output voltage AO3 from amplifier circuit AP3 becomes "H", and nMOS transistor TDc3 switches to the ON state. Consequently, the gate voltage Gc3 of nMOS transistor TOc3 decreases, and nMOS transistor TOc3 becomes OFF. Thus, the boosting of voltage VOUT3 using drive circuit 144_3 stops.

[0189] Additionally, the ramp-up end determination circuit C3 within the drive circuit 144_3 detects whether the voltage VOUT3 has reached the target voltage, and determines or denies the ramp-up end signal RUP_EN3. That is, when the voltage VOUT3 reaches the target voltage, the ramp-up end determination circuit C3 outputs the determined ramp-up end signal RUP_EN3 (e.g., "L") to the gate of the nMOS transistor TSc3. When the nMOS transistor TSc3 receives the ramp-up end signal RUP_EN3 ("L"), it switches to an off state. This blocks the current flowing to the resistor RC3.

[0190] Other actions of regulator group 14Ac and Figure 11 The regulator group 14Ab shown operates in the same way.

[0191] 3.2.2 Regulator Group 14Ad

[0192] Figure 13This is a circuit diagram showing the configuration of regulator group 14Ad. Regulator group 14Ad is a set of regulator group 14Ab with additional drive circuits 144_1 and 144_2 for drive voltages VOUT1 and VOUT2, respectively. In other words, in regulator group 14Ac, drive circuit 144_3 for drive voltage VOUT3 is omitted. This regulator group 14Ad is used when the capacitive load of the wiring (e.g., word line WL) supplying voltage VOUT3 is small.

[0193] Other circuit configurations of regulator group 14Ad and Figure 11 The circuit configuration of the regulator group 14Ab shown is the same. Furthermore, regarding the operation of the regulator group 14Ad, apart from the operation of the drive circuit 144_3, it is the same as... Figure 12 The regulator group 14Ac shown is the same.

[0194] 3.3 Effects of the third embodiment

[0195] According to the third embodiment, the same as the first embodiment, a semiconductor memory device capable of improving operating speed can be provided.

[0196] Furthermore, the voltage generation circuit of the third embodiment includes a drive circuit 144 for boosting the voltage VOUT generated by each regulator. The drive circuit 144 operates while the voltage VOUT rises to the target voltage, and stops operating when the voltage VOUT reaches the target voltage.

[0197] Therefore, compared to the first and second embodiments, the voltage VOUT to be boosted can be rapidly boosted to the target voltage. Furthermore, upon detecting that the voltage VOUT has reached the target voltage, the operation of the regulator can be stopped. Thus, after boosting the voltage VOUT to the target voltage, the current flowing to the drive circuit 144 corresponding to the voltage VOUT can be reduced during the period when the voltage VOUT is not boosted. Other effects are the same as in the second embodiment.

[0198] 4. Fourth Implementation Method

[0199] Next, the semiconductor memory device according to the fourth embodiment will be described. In the first to third embodiments, nMOS transistors were used as transistors for output voltage VOUT and for equalization, but in the fourth embodiment, p-channel MOS field-effect transistors (hereinafter, pMOS transistors) are used for these transistors. In the fourth embodiment, the differences from the first embodiment will be mainly described.

[0200] 4.1 Voltage Generation Circuit

[0201] The voltage generation circuit 14 of the fourth embodiment includes a regulator group 14Ae. Figure 14This is a circuit diagram showing the configuration of the regulator group 14Ae in the fourth embodiment. The regulator group 14Ae includes two regulators 145_1 and 145_2, and an equalization circuit 146.

[0202] The circuit connection of regulator 145_1 will be described below.

[0203] The regulator 145_1 includes a low-voltage amplifier circuit AP1A, nMOS transistors TCa1 and TTa1, a pMOS transistor TOa1A, a resistor Ra1, and a variable resistor VR1.

[0204] A voltage VSUP is supplied to the source of the pMOS transistor TOa1A. The drain of the pMOS transistor TOa1A is connected to the ground voltage terminal GND via a variable resistor VR1. The node between the drain of the pMOS transistor TOa1A and the variable resistor VR1 is connected to wiring LOUT1. Wiring LOUT1 outputs voltage VOUT1.

[0205] Additionally, a voltage VSUP is supplied to the drain of nMOS transistor TCa1 via resistor Ra1. The source of nMOS transistor TCa1 is connected to ground via nMOS transistor TTa1. The node between the drain of nMOS transistor TCa1 and resistor Ra1 is connected to the gate of pMOS transistor TOa1A.

[0206] A variable resistor VR1 is connected to the resistor control terminal of the inverting input (-) terminal (first input terminal) of amplifier circuit AP1A, and a voltage VS1 is input thereon. A reference voltage VREF is input to the non-inverting input (+) terminal (second input terminal) of amplifier circuit AP1A. The output terminal of amplifier circuit AP1A is connected to the gate of nMOS transistor TTa1. The node between the output terminal of amplifier circuit AP1A and the gate of nMOS transistor TTa1 is connected to the gate of nMOS transistor TDb121 of equalization circuit 146.

[0207] Next, the circuit connection of regulator 145_2 will be described.

[0208] The regulator 145_2 includes a low-voltage amplifier circuit AP2A, nMOS transistors TCa2 and TTa2, a pMOS transistor TOa2A, a resistor Ra2, and a variable resistor VR2.

[0209] A voltage VSUP is supplied to the source of the pMOS transistor TOa2A. The drain of the pMOS transistor TOa2A is connected to the ground voltage terminal GND via a variable resistor VR2. The node between the drain of the pMOS transistor TOa2A and the variable resistor VR2 is connected to wiring LOUT2. Wiring LOUT2 outputs voltage VOUT2.

[0210] Additionally, a voltage VSUP is supplied to the drain of nMOS transistor TCa2 via resistor Ra2. The source of nMOS transistor TCa2 is connected to ground via nMOS transistor TTa2. The node between the drain of nMOS transistor TCa2 and resistor Ra2 is connected to the gate of pMOS transistor TOa2A.

[0211] A variable resistor VR2 is connected to the resistor control terminal of the inverting input (-) terminal (first input terminal) of amplifier circuit AP2A, and a voltage VS2 is input thereon. A reference voltage VREF is input to the non-inverting input (+) terminal (second input terminal) of amplifier circuit AP2A. The output terminal of amplifier circuit AP2A is connected to the gate of nMOS transistor TTa2. The node between the output terminal of amplifier circuit AP2A and the gate of nMOS transistor TTa2 is connected to the gate of nMOS transistor TDb122 of equalization circuit 146.

[0212] Next, the circuit connection of the equalization circuit 146 will be described.

[0213] The equalization circuit 146 includes nMOS transistors TDb121, TDb122, TCb12, pMOS transistor TEQA, and resistor Rb12. nMOS transistors TDb121 and TDb122 have the same transistor characteristics.

[0214] A voltage VSUP is supplied to the drain of nMOS transistor TCb12 via resistor Rb12. The node between the drain of nMOS transistor TCb12 and resistor Rb12 is connected to the gate of pMOS transistor TEQA. The source (or drain) of pMOS transistor TEQA is connected to wiring LOUT1, and the drain (or source) of pMOS transistor TEQA is connected to wiring LOUT2.

[0215] The source of nMOS transistor TCb12 is connected to ground voltage terminal GND via nMOS transistors TDb121 and TDb122 connected in series. In other words, nMOS transistors TDb121 and TDb122 are connected in series between the source of nMOS transistor TCb12 and ground voltage terminal GND.

[0216] In the regulators 145_1, 145_2 and the equalization circuit 146, the following relationships hold true, as in the first embodiment.

[0217] [{Rb12·(channel width of TDb12) / (channel length of TDb12)} / {Ra1·(channel width of TDa1) / (channel length of TDa1)}]>1

[0218] Here, Rb12 and Ra1 represent the resistance values, respectively. TDb12 represents TDb121 or TDb122.

[0219] In addition, Ra1 = Ra2

[0220] (Channel width of TTa1) = (Channel width of TTa2)

[0221] (Channel length of TTa1) = (Channel length of TTa2)

[0222] Here, Ra2 represents the resistance value.

[0223] Other components and uses Figure 7 The configuration is the same as that of the first embodiment described.

[0224] Next, the operation of the regulator group 14Ae in the fourth embodiment will be explained. Figure 15 This is a voltage waveform diagram showing the operation of the regulator group 14Ae in the fourth embodiment.

[0225] A reference voltage VREF is input to the non-inverting input (+) terminal of amplifier circuit AP1A, and a voltage VS1 is input from the variable resistor VR1 to the inverting input (-) terminal. Amplifier circuit AP1A amplifies the voltage difference between the reference voltage VREF and the voltage VS1 and outputs voltage AO1. Voltage AO1 changes continuously with changes in voltage VS1 (or voltage VOUT1). The voltage AO1 output from amplifier circuit AP1A is input to the gates of nMOS transistor TTa1 and nMOS transistor TDb121.

[0226] A reference voltage VREF is input to the non-inverting input (+) terminal of amplifier circuit AP2A, and a voltage VS2 is input from the variable resistor VR2 to the inverting input (-) terminal. Amplifier circuit AP2A amplifies the voltage difference between the reference voltage VREF and the voltage VS2 and outputs voltage AO2. The voltage AO2 output from amplifier circuit AP2A is input to the gates of nMOS transistors TTa2 and TDb122. nMOS transistors TDb121 and TDb122 function as a boost circuit to raise the gate voltage Gb12 of pMOS transistor TEQA to "H".

[0227] In this configuration, when the regulators 145_1 and 145_2 begin operation, the pMOS transistor TEQA is in the ON state, therefore, as Figure 15As shown, voltages VOUT1 and VOUT2 rise with the same voltage and the same slope. Furthermore, voltages VOUT1 and VOUT2 reach the target voltage of VOUT1. When voltage VOUT1 reaches the target voltage, the voltage AO1 output from amplifier circuit AP1A becomes "L", and nMOS transistors TTa1 and TDb121 switch to the off state. Consequently, the gate voltage Gb12 of pMOS transistor TEQA rises, and pMOS transistor TEQA switches to the off state. Thus, the connection between wiring LOUT1 and wiring LOUT2 changes from a connected state to a blocked state.

[0228] Subsequently, the voltage VOUT2 continues to rise to reach the target voltage. When the voltage VOUT2 reaches the target voltage, the voltage AO2 output from the amplifier circuit AP2A becomes "L", and the nMOS transistor TTa2 switches to the off state.

[0229] Furthermore, the gate voltages Ga1 and Ga2 of the nMOS transistors TOa1A and TOa2A are fixed to be higher than the voltage VOUT2 and lower than the voltage VSUP. The gate voltage Gb12 of the pMOS transistor TEQA is fixed to be lower than the voltage VSUP.

[0230] 4.2 Another example of a voltage generation circuit configuration

[0231] Next, another configuration example of the regulator group 14Ae included in the voltage generation circuit 14 of the fourth embodiment will be described. The voltage generation circuit 14 of the fourth embodiment includes a regulator group 14Af.

[0232] Figure 16 This is a circuit diagram showing the configuration of regulator group 14Af. Regulator group 14Af is configured to modify the equalization circuit 146 of regulator group 14Ae. Regulator group 14Af includes two regulators 145_1 and 145_2, and equalization circuit 146A.

[0233] The circuit connection of the equalization circuit 146A is described below.

[0234] The equalization circuit 146A includes nMOS transistors TDb121, TDb122, TDb121A, TDb122A, TCb12, pMOS transistor TEQA, and resistor Rb12. The nMOS transistors TDb121, TDb122, TDb121A, and TDb122A have the same transistor characteristics.

[0235] The source of nMOS transistor TCb12 is connected to ground voltage terminal GND via nMOS transistors TDb1221 and TDb1211 connected in series, and also connected to ground voltage terminal GND via nMOS transistors TDb1212 and TDb1222 connected in series. In other words, between the source of nMOS transistor TCb12 and ground voltage terminal GND, nMOS transistors TDb1221 and TDb1211 connected in series and nMOS transistors TDb1212 and TDb1222 connected in series are connected in parallel.

[0236] The node between the output terminal of amplifier circuit AP1A and the gate of nMOS transistor TTa1 is connected to the gates of nMOS transistors TDb121 and TDb121A in equalization circuit 146A. The node between the output terminal of amplifier circuit AP2A and the gate of nMOS transistor TTa2 is connected to the gates of nMOS transistors TDb122 and TDb122A in equalization circuit 146A. Other configurations of regulator group 14Af are similar to... Figure 14 The regulator group 14Ae shown is the same.

[0237] In the regulators 145_1, 145_2 and the equalization circuit 146A, the following relationship holds true.

[0238] [{Rb12·(channel width of TDb12) / (channel length of TDb12)} / {Ra1·(channel width of TDa1) / (channel length of TDa1)}]>0.5

[0239] Here, Rb12 and Ra1 represent the resistance values, respectively. TDb12 represents TDb121 or TDb122, TDb121A, or TDb122A.

[0240] In addition, Ra1 = Ra2

[0241] (Channel width of TTa1) = (Channel width of TTa2)

[0242] (Channel length of TTa1) = (Channel length of TTa2)

[0243] Here, Ra2 represents the resistance value.

[0244] Next, the operation of the regulator group 14Af in the fourth embodiment will be explained.

[0245] The operation of regulator group 14Af can accelerate the switching from the connected state to the blocked state between wirings LOUT1 and LOUT2 by adding nMOS transistors TDb121A and TDb122A connected in series between the source of nMOS transistor TCb12 and the ground voltage terminal GND. Other operations are similar to... Figure 14 The regulator group 14Ae shown is the same.

[0246] 4.3 Effects of the fourth embodiment

[0247] According to the fourth embodiment, the same as the first embodiment, a semiconductor memory device capable of improving operating speed can be provided.

[0248] Furthermore, in the fourth embodiment, pMOS transistors TOa1A, TOa2A, and TEQA can be used instead of nMOS transistors TOa1, TOa2, and TEQ used in the first embodiment, and the same effect as in the first embodiment can be obtained.

[0249] 5. Other variations, etc.

[0250] In the described embodiment, NAND flash memory is used as an example of a semiconductor memory device, but it is not limited to NAND flash memory. It can be applied to other general semiconductor memories, as well as various memory devices other than semiconductor memories.

[0251] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in many other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included within the scope of the invention as described in the claims and their equivalents.

[0252] [Explanation of Symbols]

[0253] 10 Semiconductor memory devices

[0254] 11 Memory Cell Array

[0255] 12-line decoder

[0256] 13 drives

[0257] 14 Voltage Generation Circuit

[0258] Regulator group 14A, 14Aa, 14Ab, 14Ac, 14Ad, 14Ae, 14Af, 14B, 14C

[0259] 15 Sensing Amplifier

[0260] 16 Address Register

[0261] 17 Instruction Register

[0262] 18 Sequencer

[0263] 20 Controllers

[0264] Regulators 141_1, 141_2, and 141_3

[0265] Equalization circuits 142, 142A, 142A_1, 142A_2, 142A_3

[0266] 143 Equalization End Determination Circuit

[0267] 144_1, 144_2, 144_3 drive circuits

[0268] 145_1, 145_2 Regulators

[0269] 146, 146A Equalization Circuit

[0270] C1, C2, C3 Circuit for determining the end of ramp ascent

[0271] C13, C12, C23 Equalization End Detection Circuit

Claims

1. A semiconductor memory device comprising: The first line is electrically connected to the first memory cell; The second line is electrically connected to the second memory cell; and The voltage generating circuit is configured to supply a first voltage to a first wiring connected to the first word line and a second voltage to a second wiring connected to the second word line. The voltage generating circuit mentioned above includes: The first regulator is configured to output the first voltage to the first wiring and to output a first signal corresponding to the first voltage. The second regulator is configured to output the second voltage to the second wiring and output a second signal corresponding to the second voltage. A switching circuit includes: a first transistor electrically connected between the first wiring and the second wiring; and a second transistor and a third transistor connected in parallel between the gate of the first transistor and a ground voltage terminal; wherein the second transistor and the third transistor are turned on / off according to the first signal and the second signal, respectively.

2. The semiconductor memory device according to claim 1, wherein The first regulator includes: a first amplifier circuit configured to output the first signal based on the voltage difference between the first voltage and the first reference voltage, and The second regulator includes a second amplifier circuit configured to output the second signal based on the voltage difference between the second voltage and the second reference voltage.

3. The semiconductor memory device according to claim 2, wherein the first signal changes continuously with the change of the first voltage, and the second signal changes continuously with the change of the second voltage.

4. A method for boosting the voltage of a first wiring and a second wiring in a semiconductor memory device, the semiconductor memory device comprising: a first word line electrically connected to a first memory cell and the first wiring; and a second word line electrically connected to a second memory cell and the second wiring; the method comprising: When the first wiring and the second wiring are in a conductive state, the first voltage applied to the first wiring is increased and the second voltage applied to the second wiring is increased; When the first voltage is increased, a first signal that changes continuously with the change of the first voltage and a second signal that changes continuously with the change of the second voltage are generated; and Based on the first signal, the first wiring and the second wiring are electrically disconnected so that the first wiring and the second wiring are in a non-conductive state.

5. The method according to claim 4, further comprising: Based on the first signal, the power supply to the first wiring is cut off, and The power supply to the second wiring is cut off based on the second signal.

6. The method according to claim 5, further comprising: The first transistor is turned on based on the address input to the line decoder to transmit the first voltage from the first wiring to the first word line; and The second transistor is turned on based on the address input to the line decoder to transmit the second voltage from the second wiring to the second word line.

7. A semiconductor memory device comprising: A memory cell array is located above a semiconductor substrate and includes multiple memory strings, each memory string including: a first select gate transistor, a second select gate transistor, and multiple memory cell transistors between the first select gate transistor and the second select gate transistor; Multiple word lines, each extending in a first direction and a second direction intersecting the first direction, wherein the word lines are stacked in a third direction intersecting the first direction and the second direction and connected to the gate of the memory cell transistor; Multiple bit lines are respectively connected to the first end of the memory string; The source line is connected to the second end of the memory string; A line decoder includes multiple transmission transistors, each transmission transistor having a first terminal connected to a word line and a second terminal connected to multiple voltage supply lines; and The voltage generating circuit is configured to supply multiple voltages to the voltage supply line respectively; The voltage generating circuit mentioned above includes: The first power node, from which the first power supply voltage is supplied. The second power node is supplied with a second power voltage that is lower than the first power voltage. The first regulator has a first voltage output node from which a first voltage is output to at least one of the voltage supply lines; and a first signal output node from which a first signal corresponding to the voltage level at the first voltage output node is output. The second regulator has a second voltage output node from which a second voltage is output to at least one of the voltage supply lines; and a second signal output node from which a second signal corresponding to the voltage level at the second voltage output node is output. A switching circuit has the following characteristics: The first transistor has a first terminal connected to the first voltage output node, a second terminal connected to the second voltage output node, and a gate connected to the first node. The second transistor has a first terminal connected to the first node, a second terminal connected to the second power node, and a gate. The first signal is supplied from the first signal output node to the gate. The third transistor has a first terminal connected to the first node, a second terminal connected to the second power node, and a gate, wherein the second signal is supplied from the second signal output node to the gate.

8. The semiconductor memory device according to claim 7, wherein The first regulator includes a first amplifier circuit configured to output the first signal based on the voltage difference between the voltage level at the first voltage output node and a reference voltage. The second regulator includes a second amplifier circuit configured to output the second signal based on the voltage difference between the voltage level at the second voltage output node and the reference voltage.

9. The semiconductor memory device according to claim 7, wherein The voltage generating circuit further includes: The third regulator has a third voltage output node from which a third voltage is output to the other of the voltage supply lines; and a third signal output node from which a third signal corresponding to the voltage level at the third voltage output node is output. The second switching circuit has: The fourth transistor has a first terminal connected to the first voltage output node, a second terminal connected to the third voltage output node, and a gate connected to the second node. The fifth transistor has a first terminal connected to the second node, a second terminal connected to the second power supply node, and a gate. The first signal is supplied from the first signal output node to the gate. The sixth transistor has a first terminal connected to the second node, a second terminal connected to the second power supply node, and a gate. The third signal is supplied from the third signal output node to the gate. The third switching circuit has: The seventh transistor has a first terminal connected to the second voltage output node, a second terminal connected to the third voltage output node, and a gate connected to the third node. The eighth transistor has a first terminal connected to the third node, a second terminal connected to the second power node, and a gate. The second signal is supplied from the second signal output node to the gate. The 9th transistor has a first terminal connected to the 3rd node, a second terminal connected to the 2nd power node, and a gate, wherein the 3rd signal is supplied from the 2nd signal output node to the gate.

10. The semiconductor memory device according to claim 7, wherein Each of the first to the third transistors is an n-channel MOS field-effect transistor.

11. The semiconductor memory device according to claim 7, wherein The switching circuit further comprises: a first resistor having a first terminal connected to the first power supply node; and a tenth transistor having a first terminal connected to the second terminal of the first resistor and a gate supplied with a clamping signal. The first terminals of the second and third transistors are connected to the first node via the tenth transistor.

12. The semiconductor memory device according to claim 11, wherein The switching circuit further comprises: an 11th transistor having a first terminal connected to the second terminal of the first resistor, a second terminal connected to the first terminal of the 10th transistor, and a gate to which a control signal is supplied. The first terminal of the 10th transistor is connected to the second terminal of the 1st resistor via the 11th transistor.

13. The semiconductor memory device according to claim 12, wherein The voltage generating circuit further includes a first circuit configured to block the current flowing through the switching circuit when the first transistor of the switching circuit switches from an off state to an on state.

14. The semiconductor memory device of claim 13, wherein... The first circuit supplies the control signal to the gate of the eleventh transistor based on at least one of the voltage level at the first terminal of the second transistor and the voltage level at the first terminal of the third transistor.

15. The semiconductor memory device according to claim 7, wherein The line decoder further includes a block decoder configured to supply a block selection signal to the gate of the transmission transistor.

16. A semiconductor memory device comprising: A memory cell array is located above a semiconductor substrate and includes multiple memory strings, each memory string including: a first select gate transistor, a second select gate transistor, and multiple memory cell transistors between the first select gate transistor and the second select gate transistor; Multiple word lines, each extending in a first direction and a second direction intersecting the first direction, wherein the word lines are stacked in a third direction intersecting the first direction and the second direction and connected to the gate of the memory cell transistor; Multiple bit lines are respectively connected to the first end of the memory string; The source line is connected to the second end of the memory string; A line decoder includes multiple transmission transistors, each transmission transistor having a first terminal connected to a word line and a second terminal connected to multiple voltage supply lines; and The voltage generating circuit is configured to supply multiple voltages to the voltage supply lines respectively. The voltage generating circuit mentioned above includes: The first power node, from which the first power supply voltage is supplied. The second power node is supplied with a second power voltage that is lower than the first power voltage. The first regulator has a first voltage output node from which a first voltage is output to at least one of the voltage supply lines; and a first signal output node from which a first signal corresponding to the voltage level at the first voltage output node is output. The second regulator has a second voltage output node from which a second voltage is output to at least one of the voltage supply lines; and a second signal output node from which a second signal corresponding to the voltage level at the second voltage output node is output. A switching circuit has the following characteristics: The first transistor has a first terminal connected to the first voltage output node, a second terminal connected to the second voltage output node, and a gate connected to the first node. The second transistor and the third transistor are connected in series between the first node and the second power node, wherein the first signal is supplied from the first signal output node to the gate of the second transistor, and the second signal is supplied from the second signal output node to the gate of the third transistor.

17. The semiconductor memory device of claim 16, wherein... The first regulator includes a first amplifier circuit configured to output the first signal based on the voltage difference between the voltage level at the first voltage output node and a reference voltage. The second regulator includes a second amplifier circuit configured to output the second signal based on the voltage difference between the voltage level at the second voltage output node and the reference voltage.

18. The semiconductor memory device of claim 16, wherein The first transistor is a p-channel MOS field-effect transistor, and the second and third transistors are each n-channel MOS field-effect transistors.

19. The semiconductor memory device of claim 16, wherein The switching circuit further comprises: a first resistor having a first terminal connected to the first power supply node; and a fourth transistor having a first terminal connected to the second terminal of the first resistor and a gate supplied with a clamping signal. The first terminal of the third transistor is connected to the first node via the fourth transistor, and the second terminal of the third transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is connected to the second power node.

20. The semiconductor memory device of claim 19, wherein... The switching circuit further includes: a fifth transistor and a sixth transistor connected in series between the first node and the second power node, and The first signal is supplied from the first signal output node to the gate of the fifth transistor, and the second signal is supplied from the second signal output node to the gate of the sixth transistor.

21. The semiconductor memory device of claim 20, wherein... The first terminal of the fifth transistor is connected to the first node via the fourth transistor, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor, and the second terminal of the sixth transistor is connected to the second power node.

22. The semiconductor memory device of claim 16, wherein The line decoder further includes a block decoder configured to supply a block selection signal to the gate of the transmission transistor.

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