Test system and test method

Abstract

A test system includes a plurality of memory circuits and a test circuit. The test circuit is coupled to the memory circuits. The test circuit is configured to perform a read-write operation on the memory circuits, and each of the memory circuits has a read-write start time point corresponding to the read-write operation. The test circuit is further configured to control the read-write start time points of the memory circuits to be different from each other.

Description

Technical Field

[0001] This invention relates to a testing technique, and more particularly to a testing system and method for testing memory circuits. Background Technology

[0002] With the advancement of technology, the number of memory modules in electronic devices is increasing. However, due to manufacturing processes or other factors, memory modules may contain defects. In some related technologies, test circuits can be used to test the memory modules to confirm the presence of defects. Summary of the Invention

[0003] Some embodiments of the present invention relate to a testing system. The testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is used to perform a read / write operation on the memory circuits, and each of the memory circuits has a read / write start time point corresponding to the read / write operation. The testing circuit is also used to control the read / write start times points of the memory circuits to be distinct from each other.

[0004] Some embodiments of the present invention relate to a testing method. The testing method includes the following operations: performing a read / write operation on a plurality of memory circuits through a testing circuit, wherein each of these memory circuits has a read / write start time point corresponding to the read / write operation; and controlling these read / write start times points of the memory circuits to be different from each other through the testing circuit.

[0005] In summary, this invention utilizes a single test circuit to test multiple memory circuits, and the test circuit can stagger the read / write start times of these memory circuits. Therefore, this invention can avoid excessive instantaneous voltage drops without increasing the circuit area occupied by the test circuit (or by a small amount) or increasing the test time, thus ensuring the normal operation of the circuit. Attached Figure Description

[0006] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figure 1 This is a schematic diagram of a test system according to some embodiments of the present invention; Figure 2 This is illustrated in some embodiments of the present invention. Figure 1 Timing diagram of the test system in the document; Figure 3 This is a schematic diagram of an offset circuit according to some embodiments of the present invention; and Figure 4 This is a flowchart illustrating a test method according to some embodiments of the present invention.

[0007] Explanation of reference numerals in the attached figures: Detailed Implementation

[0008] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction between two or more components.

[0009] refer to Figure 1 . Figure 1 This is a schematic diagram of a test system 100 according to some embodiments of the present invention.

[0010] by Figure 1 For example, the test system 100 includes memory circuits M1-M3 and a test circuit 120. The test circuit 120 is coupled to the memory circuits M1-M3. In some embodiments, the test circuit 120 is implemented using a Memory Built-in Self Test (MBIST) circuit and is integrated with the memory circuits M1-M3 on a single chip.

[0011] In some embodiments, the storage capacities of these memory circuits M1-M3 are different from each other. In some other embodiments, the storage capacities of these memory circuits M1-M3 are not different from each other.

[0012] For ease of understanding, the following explanation will use the example of memory circuits M1-M3 having different storage capacities, but the invention is not limited thereto. Figure 1 For example, memory circuit M1 has Q entries, memory circuit M2 has P entries, and memory circuit M3 has N entries, where Q, P, and N are positive integers, Q is greater than P, and P is greater than N. In other words, the storage capacity of memory circuit M1 is greater than the storage capacity of memory circuit M2, and the storage capacity of memory circuit M2 is greater than the storage capacity of memory circuit M3.

[0013] It should be noted here that, Figure 1 The number of memory circuits is merely an example, and various applicable numbers are within the scope of this invention.

[0014] The test circuit 120 can be understood as a memory access controller used to perform a read / write operation on memory circuits M1-M3 to test them. For the same read / write operation, all entries in each memory circuit M1-M3 will be read or written. That is, for the same read / write operation, the memory circuit M1 (with the most entries, the largest storage capacity) will have the longest total operating time interval, while the memory circuit M3 (with the fewest entries, the smallest storage capacity) will have the shortest total operating time interval.

[0015] Please refer to the above. Figure 1 as well as Figure 2 . Figure 2 This is illustrated in some embodiments of the present invention. Figure 1 The timing diagram of the test system 100 is shown. The test circuit 120 can control the read / write start times ST1-ST3 of memory circuits M1-M3 to be different from each other based on the clock signal CLK. Figure 2 For example, for the same read / write operation, the test circuit 120 can control the memory circuit M1 to perform read / write operation at the read / write start time point ST1 based on the clock signal CLK, control the memory circuit M2 to perform read / write operation at the read / write start time point ST2 based on the clock signal CLK, and control the memory circuit M3 to perform read / write operation at the read / write start time point ST3 based on the clock signal CLK.

[0016] by Figure 1 For example, the test circuit 120 may include an enable signal generation circuit 121, an address generation circuit 122, an offset circuit 123, and an offset circuit 124.

[0017] Enable signal generation circuit 121 generates and outputs enable signals EN1-EN3. Enable signals EN1-EN3 are mainly used to enable or disable memory circuits M1-M3. Address generation circuit 122 generates and outputs address signals AD. Address signals AD are mainly used to determine which entry in memory circuits M1-M3 should be read or written.

[0018] exist Figure 1 In this circuit, the enable signal generation circuit 121 and the address generation circuit 122 are coupled to the memory circuit M1. The memory circuit M1 can receive the enable signal EN1 from the enable signal generation circuit 121 and the address signal AD from the address generation circuit 122. Accordingly, if the enable signal EN1 has an enable level at the read / write start time point ST1, then the memory circuit M1 can perform read / write operations at the read / write start time point ST1 based on the enable signal EN1 and the address signal AD.

[0019] On the other hand, the enable signal generation circuit 121 and the address generation circuit 122 are coupled to the offset circuit 123, and the offset circuit 123 is coupled to the memory circuit M2. The offset circuit 123 can receive the enable signal EN2 from the enable signal generation circuit 121 and the address signal AD from the address generation circuit 122. Then, the offset circuit 123 can generate an offset signal DS1 based on the enable signal EN2 and the address signal AD. The memory circuit M2 can then perform read / write operations at the read / write start time point ST2 based on the offset signal DS1.

[0020] In some embodiments, the offset circuit 123 may include a comparator. This comparator compares the address value carried by the address signal AD with a first offset value (e.g., 256). The address value carried by the address signal AD may be counted downwards from an initial address value (e.g., 0). When the current address value carried by the address signal AD (e.g., 256) equals the first offset value (e.g., time point ST2), the enable signal EN2 has an enable level. At this time, the offset circuit 123 may generate an offset signal DS1 to enable the memory circuit M2 at the read / write start time point ST2 and determine which entry (e.g., entry 0) in the memory circuit M2 to perform a read / write operation based on the difference between the current address value and the first offset value (e.g., 256 - 256 = 0).

[0021] Similarly, the enable signal generation circuit 121 and the address generation circuit 122 are coupled to the offset circuit 124, and the offset circuit 124 is coupled to the memory circuit M3. The offset circuit 124 can receive the enable signal EN3 from the enable signal generation circuit 121 and the address signal AD from the address generation circuit 122. Then, the offset circuit 124 can generate an offset signal DS2 based on the enable signal EN3 and the address signal AD. The memory circuit M3 can then perform read / write operations at the read / write start time point ST3 based on the offset signal DS2.

[0022] Similarly, in some embodiments, the offset circuit 124 may include a comparator. This comparator compares the address value carried by the address signal AD with a second offset value (e.g., 128). As previously described, the address value carried by the address signal AD may be counted downwards from an initial address value (e.g., 0). When the current address value carried by the address signal AD (e.g., 128) equals the second offset value (e.g., time point ST3), the enable signal EN3 has an enable level. At this time, the offset circuit 124 may generate an offset signal DS2 to enable the memory circuit M3 at the read / write start time point ST3 and determine which entry (e.g., entry 0) in the memory circuit M3 to perform a read / write operation based on the difference between the current address value and the second offset value (e.g., 128 - 128 = 0).

[0023] by Figure 2 For example, the read / write start time point ST1 is earlier than the read / write start time point ST3, and the read / write start time point ST3 is earlier than the read / write start time point ST2. That is, the read / write start time point ST1 of the memory circuit M1 with the largest storage capacity is the earliest. There is a first delay time interval (marked with halftone dots) between the read / write start time point ST3 and the read / write start time point ST1, and a second delay time interval (also marked with halftone dots) between the read / write start time point ST2 and the read / write start time point ST1, and the second delay time interval is longer than the first delay time interval. It should be noted here that although in... Figure 2 In this invention, the read / write start time point ST3 is earlier than the read / write start time point ST2, but this is not a limitation. In some other embodiments, the read / write start time point ST3 may be later than the read / write start time point ST2.

[0024] The time interval (operating time interval) between the start and end times of a read / write operation of a memory circuit is directly related to the memory circuit's storage capacity. Figure 2 For example, since memory circuit M1 has the largest storage capacity, the time interval between its read / write start time ST1 and read / write end time ET1 is the longest. Since memory circuit M3 has the smallest storage capacity, the time interval between its read / write start time ST3 and read / write end time ET3 is the shortest.

[0025] In some embodiments, the test circuit 120 can control the read / write end time point ET2 of memory circuit M2 and the read / write end time point ET3 of memory circuit M3 to be no later than (equal to or earlier than) the read / write end time point ET1 of memory circuit M1 with the maximum storage capacity. This avoids incurring additional test time. Figure 2 In the example, the read / write end time points ET1, ET2, and ET3 of the memory circuit M3 controlled by the test circuit 120 are different from each other.

[0026] In some embodiments, the disable time point of a memory circuit is the end time point of the read / write operation of the memory circuit. Figure 1 as well as Figure 2 For example, enable signal EN1 can be disabled at the read / write end time ET1 to disable memory circuit M1. Enable signal EN2 can be disabled at the read / write end time ET2 to enable the corresponding offset signal DS1 to be used to disable memory circuit M2. Enable signal EN3 can be disabled at the read / write end time ET3 to enable the corresponding offset signal DS2 to be used to disable memory circuit M3. This achieves power saving.

[0027] In some other embodiments, the disable time points for all memory circuits M1-M3 are the read / write completion time points of memory circuit M1 with the largest storage capacity. That is, enable signals EN1-EN3 only have a disable level at the read / write completion time point ET1 to disable memory circuits M1-M3. The period between the read / write completion time point ET2 of memory circuit M2 and the read / write completion time point ET1 of memory circuit M1 is the idle period for memory circuit M2, and the period between the read / write completion time point ET3 of memory circuit M3 and the read / write completion time point ET1 of memory circuit M1 is the idle period for memory circuit M3.

[0028] In some related technologies, to save circuit space occupied by memory testing circuits, a single test circuit is used to test multiple memory circuits. In this case, when the test begins (the process of transitioning from idle to test state), a very large current will be generated. This very large current can cause insufficient power supply, resulting in an excessive instantaneous voltage drop and ultimately causing circuit failure.

[0029] In some related technologies, to avoid excessive instantaneous voltage drops, multiple test circuits are used to test multiple memory circuits separately. However, this increases the circuit area occupied by the test circuits, thus increasing the overall chip size. In other related technologies, to avoid excessive instantaneous voltage drops, these memory circuits are divided into multiple groups for time-sharing testing. However, this increases the testing time.

[0030] Compared to the aforementioned related technologies, in this invention, a single test circuit 120 is used to test multiple memory circuits M1-M3, and the test circuit 120 can stagger the read / write start times ST1-ST3 of the memory circuits M1-M3. Accordingly, this invention can avoid excessive instantaneous voltage drops caused by extremely high current without increasing the circuit area occupied by the test circuit or increasing the test time, thereby ensuring normal circuit operation. The less overlap in the operating time intervals of the memory circuits M1-M3, the better the effect of avoiding extremely high current.

[0031] refer to Figure 3 . Figure 3 This is a schematic diagram of an offset value generation circuit 300 according to some embodiments of the present invention. In some embodiments, Figure 1 The offset circuit 123 or 124 may further include an offset value generation circuit 300, which can be used to generate the aforementioned first offset value. Figure 3 (indicated by OF1) or the second offset value ( Figure 3 (In Chinese, it is indicated by OF2).

[0032] by Figure 3For example, the offset value generation circuit 300 includes a multiplexer 310 and a register 320. The multiplexer 310 includes multiple inputs. One input of the multiplexer 310 is coupled to the register 320, and the other inputs of the multiplexer 310 are used to receive candidate offset values ​​OFFSET1, OFFSET2, and OFFSET3, respectively. The register 320 can generate a candidate offset value OFFSET4 based on system requirements or application scenarios and according to a user operation or a command from a control circuit.

[0033] The multiplexer 310 can output one of the candidate offset values ​​OFFSET1, OFFSET2, OFFSET3, and OFFSET4 from the selection signal SS to generate the aforementioned first offset value OF1 or second offset value OF2. The selection signal SS can be generated based on system requirements or application scenarios and according to a user operation or a command from a control circuit. Then, as described above, the offset circuit 123 or 124 can further generate offset signals DS1 or DS2 based on the first offset value OF1 or the second offset value OF2.

[0034] Since the candidate offset value OFFSET4 or the selection signal SS can be adjusted based on system requirements or application scenarios, this structure has greater application flexibility and can be applied to more usage environments.

[0035] It should be noted here that, Figure 3 The number of candidate offset values ​​or registers is merely an example, and various applicable numbers are within the scope of this invention.

[0036] refer to Figure 4 . Figure 4 This is a flowchart illustrating a test method 400 according to some embodiments of the present invention. Figure 4 For example, test method 400 includes operation S410 and operation S420.

[0037] In some embodiments, test method 400 can be applied to Figure 1 The present invention is not limited to the test system 100 described herein. However, for ease of understanding, the test method 400 will be used in conjunction with... Figure 1 The test system 100 in the text is described.

[0038] In operation S410, a read / write operation is performed on memory circuits M1-M3 via test circuit 120. Each memory circuit M1-M3 has a read / write start time point corresponding to this read / write operation. Figure 2 For example, memory circuit M1 corresponds to the read / write start time point ST1, memory circuit M2 corresponds to the read / write start time point ST2, and memory circuit M3 corresponds to the read / write start time point ST3.

[0039] In operation S420, the test circuit 120 controls the read / write start times ST1-ST3 of memory circuits M1-M3 to be different from each other. In some embodiments, the read / write start time ST1 of memory circuit M1 with the largest storage capacity is the earliest, while the read / write start times ST2-ST3 of other memory circuits M2-M3 are later than the read / write start time ST1.

[0040] In summary, this invention utilizes a single test circuit to test multiple memory circuits, and the test circuit can stagger the read / write start times of these memory circuits. Therefore, this invention can avoid excessive instantaneous voltage drops without increasing the circuit area occupied by the test circuit (or by a small amount) or increasing the test time, thus ensuring normal circuit operation.

[0041] Although the embodiments of the present invention have been disclosed above, they are not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be determined by the claims of the present invention.

Claims

1. A testing system, comprising: Multiple memory circuits; as well as A test circuit is coupled to the plurality of memory circuits, wherein the test circuit is used to perform a read / write operation on the plurality of memory circuits, and each of the plurality of memory circuits has a read / write start time point corresponding to the read / write operation. The test circuit is further configured to control the multiple read / write start times of the multiple memory circuits to be distinct from each other. The multiple memory circuits have different total operating time intervals. The plurality of memory circuits includes a first memory circuit and a second memory circuit, wherein the storage capacity of the first memory circuit is greater than the storage capacity of the second memory circuit, and the read / write start time of the first memory circuit is earlier than the read / write start time of the second memory circuit. The read / write end time point of the second memory circuit corresponding to the read / write operation is the same as or earlier than the read / write end time point of the first memory circuit corresponding to the read / write operation.

2. The testing system according to claim 1, characterized in that, The test circuit includes: An enable signal generation circuit is used to generate a first enable signal and a second enable signal; An address generation circuit is used to generate an address signal; and A first offset circuit is configured to generate a first offset signal based on the second enable signal and the address signal. The first memory circuit performs the read / write operation based on the first enable signal and the address signal. The second memory circuit performs the read / write operation according to the first offset signal.

3. The testing system according to claim 2, characterized in that, The first offset circuit is used to compare an address value carried by the address signal with an offset value, wherein when the address value is equal to the offset value, the first offset circuit generates the first offset signal according to the second enable signal and the address signal to perform the read and write operation on the second memory circuit.

4. The testing system according to claim 3, characterized in that, The first offset circuit includes: A multiplexer is configured to receive a plurality of candidate offset values ​​and output one of the candidate offset values ​​as the offset value according to a selection signal; and A register, coupled to the multiplexer, wherein the register is used to generate one of the plurality of candidate offset values.

5. The testing system according to claim 2, characterized in that, The second memory circuit has a read / write end time point corresponding to the read / write operation, and the second enable signal has a disabled level at the read / write end time point of the second memory circuit.

6. The testing system according to claim 2, characterized in that, The first memory circuit has a read / write end time point corresponding to the read / write operation, and the second enable signal has a disabled level at the read / write end time point of the first memory circuit.

7. The testing system according to claim 2, characterized in that, The plurality of memory circuits further includes a third memory circuit, wherein the enable signal generating circuit is further configured to generate a third enable signal, and wherein the test circuit further includes: A second offset circuit is configured to generate a second offset signal based on the third enable signal and the address signal. The third memory circuit is subjected to the read / write operation according to the second offset signal.

8. A testing method, comprising: A test circuit performs a read / write operation on multiple memory circuits, each of which has a read / write start time point corresponding to the read / write operation. as well as The test circuit controls the multiple read / write start times of the multiple memory circuits to be different from each other. The multiple memory circuits have different total operating time intervals. The plurality of memory circuits includes a first memory circuit and a second memory circuit. The testing method further includes, wherein the testing circuit controls a storage capacity of the first memory circuit to be greater than a storage capacity of the second memory circuit, and the read / write start time of the first memory circuit is earlier than the read / write start time of the second memory circuit. The test circuit controls the second memory circuit to have a read / write end time point corresponding to the read / write operation that is the same as or earlier than the first memory circuit to have a read / write end time point corresponding to the read / write operation.

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