Alscn passivated algan-gan hems device and fabrication method

Abstract

The application discloses an AlScN passivation-based AlGaN-GaN HEMTs device and a manufacturing method thereof, and comprises the following steps: epitaxially growing a substrate layer, a GaN buffer layer and an AlGaN barrier layer in a bottom-up stacking mode; depositing an AlScN passivation layer on the AlGaN barrier layer; forming an opening area slightly larger than the source electrode and the drain electrode area on the AlScN passivation layer by using overexposure photolithography, and etching the AlScN passivation layer of the opening area until the AlGaN barrier layer; evaporating ohmic metal on the source electrode and the drain electrode pattern area on the AlGaN barrier layer and annealing to form ohmic contact to obtain the source electrode and the drain electrode; etching a gate slot on the AlScN passivation layer, and photoetching a gate electrode area on the AlScN passivation layer on both sides of the gate slot; evaporating gate metal in the gate slot and the gate electrode area to form a T-shaped gate electrode. The application further improves the performance of the AlGaN / GaN HEMTs device.

Description

Technical Field

[0001] This invention belongs to the field of microelectronics technology, specifically relating to an AlGaN-GaN HEMTs device based on AlScN passivation and its fabrication method. Background Technology

[0002] With advancements in technology, existing first- and second-generation semiconductor materials can no longer meet the demands of higher-frequency, higher-power electronic devices. However, electronic devices based on nitride semiconductor materials can fulfill these requirements, significantly improving device performance. This has led to the widespread application of third-generation semiconductor materials, represented by GaN, in the manufacture of microwave and millimeter-wave devices. GaN possesses characteristics such as high breakdown field strength, high electron drift velocity, and the ability to form a high-concentration two-dimensional electron gas (2-DEG) at the heterojunction interface through AlGaN / GaN heterojunction structures. GaN-based high electron mobility transistors (HEMTs) can be applied to mobile SoCs, 5G millimeter-wave base station systems, satellite communications, and other scenarios. Especially in the currently popular 5G millimeter-wave and even 6G, terahertz, and other high-frequency application areas, there is a need to optimize the frequency characteristics of current devices.

[0003] However, since the crystal growth of GaN HEMT devices is a repetitive cyclic process, dangling bonds and defects, known as surface states, exist on the device surface when growth ceases. These surface states trap electrons injected by the gate and generate a layer of charge on the surface, depleting the channel in the high-field region between the gate and drain. This causes current collapse, resulting in surface electrons not being able to fully modulate the channel charge during RF operation, thus reducing the device's output power and significantly affecting its breakdown voltage. To suppress the current collapse effect and maximize the power and RF capabilities of GaN HEMT devices, researchers both domestically and internationally have conducted extensive research and finally developed the surface passivation layer method. Surface passivation involves growing one or more polycrystalline thin films with lattice constants close to AlGaN, such as SiN, SiO2, and AlN, on the device surface. The passivation layer can cover the device surface, reducing the surface state density of the barrier layer through continuous crystalline layers, thereby improving the device's breakdown voltage and output power. Furthermore, it can prevent damage to the device from external factors such as water, oxygen, and high temperatures during fabrication and use, thus improving the device's lifetime and stability. Current solutions involve using different deposition methods to prepare passivation layers. For example, in 2000, Bruce M. Green et al. used an undoped AlGaN barrier layer and plasma-enhanced chemical vapor deposition (PECVD) to grow a Si3N4 passivation layer, thus growing an AlGaN / GaN HEMT device with a gate length of 0.5 μm on an undoped sapphire substrate. This increased the saturation power density from 1.0 W / mm to 2.0 W / mm at 4 GHz and increased the breakdown voltage by 25%. In 2012, Sen Huang et al. first performed in-situ remote plasma pretreatment, then grew an AlN thin film using plasma-enhanced atomic layer deposition (PEALD) as the passivation layer for AlGaN / GaN HEMTs. Under high drain bias conditions, ALD-AlN passivated AlGaN / GaN HEMTs achieved significant current collapse suppression and dynamic resistance reduction.

[0004] However, the aforementioned existing technologies still have the following problems:

[0005] (1) Existing manufacturing processes require high precision, SiN x The quality of the thin film has a significant impact on passivation efficiency, and the silicon to nitrogen ratio must be precisely calibrated and monitored.

[0006] (2) Due to the growth modes of PECVD and PEALD, plasma damage will be caused to the surface of the AlGaN barrier layer, which will increase the off-state leakage current, reduce the breakdown, and degrade the device characteristics.

[0007] (3) SiN x The lattice constant of AlN thin films differs from that of AlGaN, which can cause adverse stress on the AlGaN barrier layer, thereby reducing the two-dimensional electron gas (2DEG) surface density and thus affecting the on-state performance of the device.

[0008] (4) The commonly used process of "annealing first and then passivating" cannot protect the surface of the AlGaN barrier layer during the annealing process.

[0009] The aforementioned problems prevent further improvement in the performance of existing AlGaN / GaN HEMTs devices. Summary of the Invention

[0010] To address the aforementioned problems in the prior art, this invention provides an AlGaN-GaN HEMTs device based on AlScN passivation and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0011] In a first aspect, embodiments of the present invention provide a method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation, comprising:

[0012] Epitaxial growth of heterojunction material; the heterojunction material includes a substrate layer, a GaN buffer layer, and an AlGaN barrier layer stacked from bottom to top;

[0013] An AlScN passivation layer is deposited on the AlGaN barrier layer;

[0014] An opening region slightly larger than the source and drain electrode regions is formed at both ends of the AlScN passivation layer using overexposure photolithography, and the AlScN passivation layer in the opening region is etched down to the AlGaN barrier layer.

[0015] The source electrode and drain electrode patterned regions are photolithographically formed on the AlGaN barrier layer. Ohmic metal is evaporated and annealed in the source electrode and drain electrode patterned regions to form ohmic contacts, thus obtaining the source electrode and drain electrode.

[0016] A gate trench is etched in the middle region of the AlScN passivation layer, and gate electrode regions are photolithographically formed on the AlScN passivation layer on both sides of the gate trench. Schottky gate metal is evaporated in the gate trench and the gate electrode regions to form a T-shaped gate electrode.

[0017] In one embodiment of the present invention, an AlScN passivation layer is deposited on the AlGaN barrier layer, comprising:

[0018] An AlScN passivation layer was deposited on the AlGaN barrier layer using a magnetron sputtering device.

[0019] In one embodiment of the present invention, an AlScN passivation layer is deposited on the AlGaN barrier layer using a magnetron sputtering apparatus, including:

[0020] An AlScN thin film with a thickness of 20 nm to 120 nm was grown on the AlGaN barrier layer using a magnetron sputtering apparatus.

[0021] In one embodiment of the present invention, the process of growing an AlScN thin film with a thickness of 20 nm to 120 nm on the AlGaN barrier layer using a magnetron sputtering device includes:

[0022] The vacuum level in the sputtering reaction chamber was reduced to 1×10⁻⁶. -6 Torr, and heat the heterojunction material to the target temperature;

[0023] Pure argon gas is introduced into the sputtering reaction chamber to pre-sputter the Al target. The sputtering power is DC 90W to 110W and the sputtering time is 5min to 10min to remove impurities from the surface of the Al target.

[0024] Stop Al target pre-sputtering and pre-sputter the Sc target with a sputtering power of RF 65W to 85W and a sputtering time of 5 to 10 minutes to remove impurities from the Sc target surface;

[0025] An argon-nitrogen mixture of 1:1.5 to 1:3 is introduced into the sputtering reaction chamber, and the Al target and Sc target are pre-sputtered simultaneously. The sputtering power is DC 100W and RF 75W, and the sputtering time is 5min to 10min, so that the voltage and current of the Al target and Sc target in the sputtering reaction chamber reach a stable state.

[0026] Under the above stable conditions, an AlScN thin film with a thickness of 20 nm to 120 nm is grown on the AlGaN barrier layer, and the reaction time is 25 min to 30 min.

[0027] In one embodiment of the present invention, an opening region slightly larger than the source electrode and drain electrode regions is formed at both ends of the AlScN passivation layer using overexposure photolithography, including:

[0028] Photolithography was performed on the source and drain electrode regions of the AlScN passivation layer;

[0029] Photoresist is spin-coated in the source and drain electrode regions;

[0030] By controlling the exposure time, the photoresist in the source and drain electrode areas is increased to form an opening region.

[0031] In one embodiment of the present invention, the exposure time is 500ms to 1s.

[0032] In one embodiment of the present invention, ohmic metal is evaporated and annealed in the patterned regions of the source electrode and drain electrode to form an ohmic contact, thereby obtaining the source electrode and drain electrode, including:

[0033] The vacuum level in the reaction chamber of the electron beam evaporation stage was evacuated to 2 × 10⁻⁶. -6 Torr;

[0034] An ohmic metal consisting of four layers of metal—Ti, Al, Ni, and Au—is evaporated from bottom to top in the source and drain electrode pattern regions.

[0035] In a rapid annealing furnace, the ohmic metal is annealed to allow the ohmic metal in the source and drain electrode regions to sink into the AlGaN barrier layer to form an ohmic contact, thus obtaining the source and drain electrodes.

[0036] In one embodiment of the present invention, the process of annealing the ohmic metal includes:

[0037] Nitrogen gas was introduced into the rapid annealing furnace for 10 minutes, and then the furnace temperature was set to 860℃ in the nitrogen atmosphere for 60 seconds of high-temperature annealing.

[0038] In one embodiment of the present invention, a T-shaped gate electrode is formed by evaporating Schottky gate metal within the gate trench and the gate electrode region, including:

[0039] The vacuum level in the reaction chamber of the electron beam evaporation stage was evacuated to 2 × 10⁻⁶. -6 Torr;

[0040] Schottky gate metal, consisting of two layers of metal, Ni and Au, is evaporated from bottom to top within the gate trench and the gate electrode region.

[0041] Secondly, embodiments of the present invention provide an AlGaN-GaN HEMTs device based on AlScN passivation, which is fabricated by any of the above-described fabrication methods for AlGaN-GaN HEMTs devices based on AlScN passivation.

[0042] The beneficial effects of this invention are:

[0043] The fabrication method of AlGaN-GaN HEMTs based on AlScN passivation proposed in this invention is a novel fabrication method based on AlScN passivation. Specifically, it involves: epitaxially growing a heterojunction material; the heterojunction material includes a substrate layer, a GaN buffer layer, and an AlGaN barrier layer stacked from bottom to top; depositing an AlScN passivation layer on the AlGaN barrier layer; forming opening regions slightly larger than the source and drain electrode regions at both ends of the AlScN passivation layer using overexposure photolithography, and etching the AlScN passivation layer in the opening regions down to the AlGaN barrier layer; photolithographically etching source and drain electrode pattern regions on the AlGaN barrier layer; evaporating ohmic metal in the source and drain electrode pattern regions and annealing to form ohmic contacts to obtain source and drain electrodes; etching a gate trench in the middle region of the AlScN passivation layer, and photolithographically etching gate electrode regions on the AlScN passivation layers on both sides of the gate trench; evaporating Schottky gate metal in the gate trench and gate electrode regions to form a T-type gate electrode. As can be seen, the embodiments of the present invention utilize the advantages of AlScN, such as its excellent physicochemical properties, large dielectric constant, wide band gap, small lattice mismatch with AlGaN, and low interface state density at the AlScN / AlGaN interface, to achieve passivation of the AlGaN barrier layer surface. This significantly reduces the lattice mismatch of the AlGaN barrier layer and, while protecting the AlGaN barrier layer surface during the process, suppresses current collapse, improves the breakdown voltage, and further enhances the performance of AlGaN / GaN HEMTs devices. Furthermore, in the fabrication process, by enlarging the aperture pattern through overexposure lithography, a "passivation before annealing" process can be implemented. This not only protects the AlGaN barrier layer during annealing but also solves the metal overflow phenomenon that occurs in similar process schemes, further improving the performance of AlGaN / GaN HEMTs devices.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0045] Figure 1 This is a schematic flowchart of a method for fabricating an AlGaN-GaN HEMTs device based on AlScN passivation provided in an embodiment of the present invention.

[0046] Figure 2 (a)~ Figure 2 (g) is a schematic diagram of the fabrication process of the AlGaN-GaN HEMTs device based on AlScN passivation provided in the embodiments of the present invention.

[0047] Figure 3 This is a schematic diagram of the structure of an AlGaN-GaN HEMTs device based on AlScN passivation provided in an embodiment of the present invention.

[0048] Explanation of reference numerals in the attached figures:

[0049] 1-Substrate layer; 2-GaN buffer layer; 3-AlGaN barrier layer; 4-AlScN passivation layer; 5-Photoresist; 6-Source electrode; 7-Drain electrode; 8-T-type gate electrode. Detailed Implementation

[0050] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0051] To further improve the performance of AlGaN / GaN HEMTs devices, this invention provides an AlGaN-GaN HEMTs device and its fabrication method based on AlScN passivation.

[0052] In a first aspect, embodiments of the present invention provide a method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation, comprising:

[0053] S10, Epitaxial growth of heterojunction material; the heterojunction material includes a substrate layer 1, a GaN buffer layer 2, and an AlGaN barrier layer 3 stacked from bottom to top.

[0054] Using Metal-Organic Chemical Vapor Deposition (MOCVD), a heterojunction material is formed by epitaxially growing a substrate layer 1, a GaN buffer layer 2, and an AlGaN barrier layer 3 sequentially from bottom to top. Figure 2 As shown in (a); or directly using existing heterojunction materials such as substrate layer 1, GaN buffer layer 2, and AlGaN barrier layer 3 stacked from bottom to top. Figure 2 As shown in (a).

[0055] Correspondingly, the more detailed process of S10 includes:

[0056] For epitaxially grown or existing heterojunction materials, surface cleaning is performed to remove organic and inorganic contaminants and surface oxides introduced during material storage. Specifically: First, the sample (heterojunction material) is placed in acetone and sonicated for 2 minutes. Then, it is heated in a positive adhesive stripping solution heated in a 60°C water bath for 10 minutes. Subsequently, the sample is placed in acetone and isopropanol and sonicated for 3 minutes each. After washing away residual acetone and ethanol with deionized water, the sample is cleaned with HF (HF:H2O = 1:5) for 30 seconds. Finally, it is cleaned with deionized water and dried with ultrapure nitrogen.

[0057] S20. Deposit an AlScN passivation layer 4 on the AlGaN barrier layer 3.

[0058] Traditionally, SiN is used more often. x Thin film is used as a passivation layer, but SiN x The quality of the silicon-to-nitrogen ratio has a significant impact on passivation efficiency, requiring precise calibration and monitoring. Furthermore, the fabrication process primarily utilizes PECVD to grow SiN on the AlGaN barrier layer 3. x AlN films are grown on AlGaN barrier layer 3 using PECVD or PEALD growth mode. However, PECVD or PEALD growth mode causes plasma damage to the surface of AlGaN barrier layer 3, leading to increased off-state leakage current, reduced breakdown voltage, and degraded device characteristics. The inventors have discovered that AlScN possesses excellent physicochemical properties, a high dielectric constant, a wide band gap, low lattice mismatch with AlGaN, and a low interface state density at the AlScN / AlGaN interface, making it suitable for surface passivation of AlGaN barrier layer 3. Therefore, this invention implements, for example... Figure 2 (b) shows that surface passivation is achieved by depositing an AlScN passivation layer 4 on the AlGaN barrier layer 3.

[0059] Furthermore, as is well known, magnetron sputtering, compared to traditional passivation layer growth techniques such as PECVD or PEALD, does not cause plasma damage to the surface of the AlGaN barrier layer 3 and has low growth costs, meeting the needs of large-area mass production in industry. However, since there are currently no precedents for using AlScN as a passivation layer, even though magnetron sputtering is a relatively conventional process, inventors still need to explore the magnetron sputtering process parameters. Based on proposing the use of AlScN as a passivation layer, this invention also provides a feasible process scheme for depositing an AlScN passivation layer 4 on the AlGaN barrier layer 3, including: depositing the AlScN passivation layer 4 on the AlGaN barrier layer 3 using a magnetron sputtering device; preferably, growing an AlScN thin film with a thickness of 20nm to 120nm on the AlGaN barrier layer 3 using a magnetron sputtering device; more preferably, growing an AlScN thin film with a thickness of 60nm on the AlGaN barrier layer 3 using a magnetron sputtering device.

[0060] Furthermore, the embodiment of the present invention employs a magnetron sputtering device to grow an AlScN thin film with a thickness of 20 nm to 120 nm on the AlGaN barrier layer 3. A more detailed process includes:

[0061] The vacuum level in the sputtering reaction chamber was reduced to 1×10⁻⁶. -6 Torr ensures that the content of impurity gases in the sputtering reaction chamber is low enough and heats the heterojunction material to the target temperature, such as 650°C.

[0062] Pure argon gas is introduced into the sputtering reaction chamber to pre-sputter the Al target. The sputtering power is 90W to 110W from a DC source, and the sputtering time is 5 to 10 minutes to remove impurities from the surface of the Al target.

[0063] Turn off the Al target power, stop Al target pre-sputtering, and pre-sputter the Sc target. The sputtering power is 65W to 85W of radio frequency (RF) source, and the sputtering time is 5min to 10min to remove impurities on the Sc target surface.

[0064] A mixture of argon and nitrogen gas in a ratio of 1:1.5 to 1:3 is introduced into the sputtering reaction chamber, and the Al and Sc targets are pre-sputtered simultaneously. The sputtering power is DC 100W and RF 75W, the sputtering time is 5 min to 10 min, and the sputtering rate under this process is set to 2 nm / min to 2.4 nm / min, so that the voltage and current of the Al and Sc targets in the sputtering reaction chamber reach a stable state.

[0065] Under the above stable conditions, the baffle is opened, and an AlScN thin film with a thickness of 20 nm to 120 nm is grown on the AlGaN barrier layer 3 for a reaction time of 25 min to 30 min.

[0066] S30. Using overexposure lithography, open-hole regions slightly larger than the source and drain electrode regions are formed at both ends of the AlScN passivation layer 4, and the AlScN passivation layer 4 in the open-hole regions is etched up to the AlGaN barrier layer 3.

[0067] Most existing fabrication processes employ an "annealing followed by passivation" approach. However, this approach suffers from plasma damage to the AlGaN barrier layer surface during annealing. Therefore, a "passivation followed by annealing" approach is preferred because it protects the device during annealing and improves the lattice integrity of the AlGaN barrier layer. However, because ohmic metals expand thermally during annealing, some ohmic metal can be squeezed out of the passivation layer's pre-reserved holes after high-temperature annealing, resulting in metal spillage. Metal spillage not only alters device design parameters (such as source-drain spacing) but also creates metal spikes. Charge accumulation at these spikes reduces the device's breakdown voltage. The common approach to addressing these problems is to modify the ohmic metal scheme and lower the annealing temperature. However, altering the ohmic metal scheme generally impacts device performance. To address the problems of existing methods, this invention proposes a method to slightly increase the opening area of ​​the AlScN passivation layer 4. This method increases the opening area by increasing the photolithography exposure time, thereby increasing the exposure area and thus the opening area of ​​the AlScN passivation layer 4. The solution is simple and safe. Specifically, this invention forms opening areas slightly larger than the source and drain electrode regions in the source and drain electrode regions, and utilizes an overexposure photolithography process to increase the opening area. Specifically, the overexposure photolithography process forms opening areas slightly larger than the source and drain electrode regions at both ends of the AlScN passivation layer 4, including:

[0068] Source and drain electrode regions are photolithographically etched on the AlScN passivation layer 4. Photoresist is spin-coated onto the source and drain electrode regions. By controlling the exposure time, the photoresist in the source and drain electrode regions is increased to form an opening region. Preferably, the opening region is 10nm to 30nm larger than the source and drain electrode regions, and more preferably, the opening region is 20nm larger than the source and drain electrode regions. Here, reasonable control of the exposure time is crucial for forming the opening region. The inventors have found that the preferred exposure time for the opening region in this embodiment is 500ms to 1s, and more preferably, 800ms. During the exposure process, if the exposure time is too short, the opening area cannot be expanded; if the exposure time is too long, the photolithographic image area will be too large, affecting the design parameters and causing a part of the working area between the source and drain electrodes to lose the passivation layer protection. Furthermore, due to stress release after losing the passivation layer, the electron mobility of the device will decrease, thereby affecting the on-state characteristics of the device.

[0069] Correspondingly, the more detailed process of S30 includes:

[0070] A1. An opening region slightly larger than the source electrode and drain electrode regions is formed at both ends of the AlScN passivation layer 4, such as... Figure 2 As shown in (c).

[0071] First, the sample with the AlScN passivation layer 4 grown is baked on a hot plate at 200°C for 5 minutes. Then, the sample is spin-coated with photoresist at 3500 rpm and baked on a hot plate at 90°C for 1 minute. Next, the sample is placed in a lithography machine to expose the photoresist in the source and drain electrode areas for 500 ms to 1 s, which is called overexposure lithography. Finally, the overexposed sample is placed in a developing solution to remove the photoresist in the source and drain electrode areas, leaving only the photoresist 5 on the AlScN passivation layer 4 as a mask, and then rinsed with ultrapure water and dried with nitrogen.

[0072] A2, Etch the AlScN passivation layer 4 in the aperture area up to the AlGaN barrier layer 3 as shown. Figure 2 As shown in (d).

[0073] For the photolithographically lithographically completed sample, the AlScN passivation layer 4 in the opening area was etched using an inductively coupled plasma (ICP) dry etching process based on Cl. The specific etching process was as follows: the etching gas used was Cl2 / BCl3, the pressure was 5 mTorr, the upper electrode power was 100 W, the lower electrode power was 10 W, the etching time was 8 min, the etching rate was 7.5 nm / min, and the etching depth was the thickness of the AlScN passivation layer 4, up to the AlGaN barrier layer 3.

[0074] A3. Remove the photoresist mask after etching.

[0075] The sample after A2 etching was sequentially placed in acetone solution, stripping solution, acetone solution and ethanol solution for cleaning to remove photoresist outside the opening area, and then rinsed with deionized water and dried with nitrogen gas.

[0076] S40. Evaporate ohmic metal in the patterned areas of the source electrode and drain electrode and anneal to form ohmic contacts to obtain source electrode 6 and drain electrode 7.

[0077] In one embodiment of the present invention, ohmic metal is evaporated and annealed in the source electrode and drain electrode pattern regions to form the source electrode 6 and drain electrode 7, as shown in the figure. Figure 2 As shown in (e), it includes:

[0078] The vacuum level in the reaction chamber of the electron beam evaporation stage was evacuated to 2 × 10⁻⁶. -6 Torr; Evaporate ohmic metal consisting of four layers of metal, Ti, Al, Ni and Au, from bottom to top, in the source electrode and drain electrode pattern regions; Anneal the ohmic metal in a rapid annealing furnace so that the ohmic metal in the source electrode and drain electrode regions sinks to the AlGaN barrier layer 3 to form the source electrode 6 and drain electrode 7.

[0079] In one embodiment of the present invention, the process of annealing ohmic metal includes: introducing nitrogen gas into a rapid annealing furnace for 10 minutes, and then setting the furnace temperature to 860°C in a nitrogen atmosphere for 60 seconds of high-temperature annealing.

[0080] Correspondingly, the more detailed manufacturing process of S40 includes:

[0081] B1. Photolithography of the source electrode region and drain electrode region on AlGaN barrier layer 3.

[0082] First, the sample with the mesa etched is baked on a 200°C hot plate for 5 minutes. Then, a stripper is applied to the sample to a thickness of 0.35 μm, and the sample is baked on a 200°C hot plate for 5 minutes. Next, photoresist is applied to the sample to a thickness of 0.77 μm, and the sample is baked on a 90°C hot plate for 1 minute. After that, the sample is placed in a lithography machine to expose the photoresist in the source and drain electrode areas for 280 ms. Finally, the exposed sample is placed in a developing solution to remove the photoresist and stripper in the source and drain electrode areas, and then rinsed with ultrapure water and dried with nitrogen.

[0083] B2. Apply base coat.

[0084] After photolithography of the source and drain electrode areas, the undeveloped photoresist layer in the patterned area is removed using a plasma stripper. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0085] B3, Ohmic metal in the evaporation source electrode and drain electrode regions.

[0086] The sample after plasma resist removal is placed in an electron beam evaporation stage. After the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10-6 Torr, ohmic metal is evaporated on the AlGaN barrier layer 3 in the source and drain electrode regions and on the photoresist outside the source and drain electrode regions. The ohmic metal is a metal stack structure composed of four metal layers Ti, Al, Ni and Au in sequence from bottom to top.

[0087] B4. Remove ohmic metal and anneal.

[0088] First, the sample with the ohmic metal evaporated in the source and drain electrode regions was immersed in acetone for more than 40 minutes and then ultrasonically treated. Then, the sample was placed in a stripping solution at 60°C and heated in a water bath for 10 minutes to remove the photoresist outside the source and drain electrode regions. After that, the sample was ultrasonically cleaned in acetone and ethanol solutions for 3 minutes in sequence. Next, the sample was rinsed with ultrapure water and dried with nitrogen. Finally, the sample was placed in a rapid annealing furnace, nitrogen was introduced into the annealing furnace for 10 minutes, and the furnace temperature was set to 860°C in a nitrogen atmosphere for 60 seconds of high-temperature annealing to allow the ohmic metal on the source and drain electrode regions to sink to the AlGaN barrier layer 3, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel, and finally forming the source electrode 6 and drain electrode 7.

[0089] S50. A gate trench is etched in the middle region of the AlScN passivation layer 4, and a gate electrode region is photolithographically formed on the AlScN passivation layer 4 on both sides of the gate trench. Schottky gate metal is evaporated in the gate trench and the gate electrode region to form a T-type gate electrode 8.

[0090] In one embodiment of the present invention, a gate trench region is first photolithographically etched in the AlScN passivation layer 4 using photolithography. The AlScN passivation layer 4 is then etched in this gate trench region until a gate trench is formed on the surface of the AlGaN barrier layer. Figure 2 As shown in (f), the gate electrode region is then photolithographically etched, and Schottky gate metal is evaporated in the gate trench and the gate electrode region to form a T-shaped gate electrode 8. Figure 2 (g) includes: evacuating the reaction chamber of the electron beam evaporation stage to a vacuum level of 2 × 10⁻⁶. -6 Torr; a Schottky gate metal consisting of two layers of metal, Ni and Au, evaporated from bottom to top within the gate trench and gate electrode region.

[0091] Correspondingly, the more detailed manufacturing process of the S50 includes:

[0092] C1. Etch the middle region of AlScN passivation layer 4 to form a gate trench region on AlScN passivation layer 4.

[0093] First, the S40-completed sample is baked on a 200°C hot plate for 5 minutes. Then, a stripper is applied to the sample to a thickness of 0.35 μm, and the sample is baked on a 200°C hot plate for 5 minutes. Next, a photoresist is applied to the sample to a thickness of 0.77 μm, and the sample is baked on a 90°C hot plate for 1 minute. After that, the sample is placed in a lithography machine to expose the photoresist in the gate trench area. Finally, the exposed sample is placed in a developing solution to remove the photoresist and stripper in the gate trench area, and then rinsed with ultrapure water and dried with nitrogen.

[0094] C2. The AlScN passivation layer 4 in the gate trench area is removed by dry etching using an ICP device to form a trench gate.

[0095] The AlScN passivation layer 4 in the gate trench region was etched using an ICP dry etching method up to the surface of the AlGaN barrier layer to form a trench gate. The ICP dry etching conditions were: reaction gas Cl2 / BCl3, pressure 5 mTorr, upper electrode power 100 W, lower electrode power 10 W, etching time 8 min, etching rate 7.5 nm / min, and etching depth equal to the thickness of the AlScN passivation layer 4, up to the surface of the AlGaN barrier layer 3.

[0096] C3. The gate electrode region is photolithographically etched again on the AlScN passivation layer 4.

[0097] First, the sample with the completed gate etching is baked on a hot plate at 200°C for 5 minutes. Then, a stripper is applied to the sample to a thickness of 0.35 μm, and the sample is baked on a hot plate at 200°C for 5 minutes. Next, photoresist is applied to the sample to a thickness of 0.77 μm, and the sample is baked on a hot plate at 90°C for 1 minute. After that, the sample is placed in a lithography machine to expose the photoresist in the gate electrode area. Finally, the exposed sample is placed in a developing solution to remove the photoresist and stripper in the gate electrode area, and then rinsed with ultrapure water and dried with nitrogen.

[0098] C4. Apply base coat.

[0099] After the sample with the gate electrode area photolithography completed is processed, the undeveloped photoresist layer in the pattern area is removed using a plasma stripper. The processing time is 5 minutes, which greatly improves the yield of the stripped product.

[0100] C5, Evaporated Schottky gate metal.

[0101] The sample after plasma degumming is placed in the electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage is allowed to reach 2 × 10⁻⁶. -6 After Torr, Schottky gate metal is evaporated on the AlGaN barrier layer 3 in the groove and the gate electrode region, as well as on the photoresist outside the gate electrode region. The Schottky gate metal is a metal stack structure composed of two metal layers, Ni and Au, arranged sequentially from bottom to top.

[0102] C6. Strip the Schottky gate metal.

[0103] First, the sample with the Schottky gate metal evaporated was immersed in acetone for more than 40 minutes and then ultrasonically treated. Then, the sample was placed in a stripping solution at 60°C and heated in a water bath for 10 minutes to strip the photoresist outside the gate electrode area. Next, the sample was ultrasonically cleaned in acetone solution and ethanol solution for 3 minutes in sequence. Finally, the sample was rinsed with ultrapure water and dried with nitrogen.

[0104] In summary, the AlGaN-GaN based on AlScN passivation proposed in this embodiment of the invention... The fabrication method for HEMTs devices is a novel fabrication method based on AlScN passivation. Specifically, the method involves: epitaxially growing a heterojunction material; the heterojunction material includes a substrate layer 1, a GaN buffer layer 2, and an AlGaN barrier layer 3 stacked from bottom to top; depositing an AlScN passivation layer 4 on the AlGaN barrier layer 3; forming aperture regions slightly larger than the source and drain electrode regions at both ends of the AlScN passivation layer 4 using overexposure photolithography, and etching the AlScN passivation layer 4 in the aperture regions down to the AlGaN barrier layer 3; photolithographically etching source electrode 6 and drain electrode 7 pattern regions on the AlGaN barrier layer 3; evaporating ohmic metal in the source electrode 6 and drain electrode 7 pattern regions and annealing to form ohmic contacts to obtain source electrode 6 and drain electrode 7; etching a gate trench in the middle region of the AlScN passivation layer 4, and photolithographically etching gate electrode regions on the AlScN passivation layer 4 on both sides of the gate trench; evaporating Schottky gate metal in the gate trench and gate electrode regions to form a T-type gate electrode 8. As can be seen, the embodiments of the present invention utilize the advantages of AlScN, such as its excellent physicochemical properties, large dielectric constant, wide band gap, small lattice mismatch with AlGaN, and low interface state density at the AlScN / AlGaN interface, to achieve passivation of the AlGaN barrier layer 3 surface. This significantly reduces the lattice mismatch of the AlGaN barrier layer 3 and, while protecting the surface of the AlGaN barrier layer 3 during the process, suppresses current collapse effect, improves breakdown voltage, and further enhances the performance of AlGaN / GaN HEMTs devices. Furthermore, in the fabrication process, by enlarging the aperture pattern through overexposure photolithography, a "passivation before annealing" process can be implemented. This not only protects the AlGaN barrier layer 3 during annealing but also solves the metal overflow phenomenon that occurs in similar process schemes, further improving the performance of AlGaN / GaN HEMTs devices.

[0105] Meanwhile, in the fabrication process of this embodiment, magnetron sputtering technology is used to deposit the AlScN passivation layer 4, which has low growth cost and can meet the needs of large-area mass production in industry. It can be applied in scenarios such as mobile phone SoC, 5G millimeter wave base station system, and satellite communication.

[0106] Secondly, please see Figure 3This invention provides an AlGaN-GaNHEMTs device based on AlScN passivation, which is fabricated using any of the AlGaN-GaN HEMTs device fabrication methods described in the first aspect. As for the device structure embodiments of the second aspect, since they are basically similar to the method embodiments of the first aspect, they will not be described again here; relevant details can be found in the descriptions of the method embodiments of the first aspect.

[0107] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0108] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0109] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation, characterized in that, include: Epitaxial growth of heterojunction material; the heterojunction material includes a substrate layer, a GaN buffer layer, and an AlGaN barrier layer stacked from bottom to top; An AlScN passivation layer is deposited on the AlGaN barrier layer; An opening region slightly larger than the source and drain electrode regions is formed at both ends of the AlScN passivation layer using overexposure photolithography, and the AlScN passivation layer in the opening region is etched down to the AlGaN barrier layer. The source electrode and drain electrode patterned regions are photolithographically formed on the AlGaN barrier layer. Ohmic metal is evaporated and annealed in the source electrode and drain electrode patterned regions to form ohmic contacts, thus obtaining the source electrode and drain electrode. A gate trench is etched in the middle region of the AlScN passivation layer, and gate electrode regions are photolithographically formed on the AlScN passivation layer on both sides of the gate trench. Schottky gate metal is evaporated in the gate trench and the gate electrode regions to form a T-shaped gate electrode.

2. The fabrication method of AlGaN-GaN HEMTs device based on AlScN passivation according to claim 1, characterized in that, Depositing an AlScN passivation layer on the AlGaN barrier layer includes: An AlScN passivation layer was deposited on the AlGaN barrier layer using a magnetron sputtering device.

3. The fabrication method of AlGaN-GaN HEMTs device based on AlScN passivation according to claim 2, characterized in that, An AlScN passivation layer is deposited on the AlGaN barrier layer using a magnetron sputtering apparatus, including: An AlScN thin film with a thickness of 20 nm to 120 nm was grown on the AlGaN barrier layer using a magnetron sputtering apparatus.

4. The fabrication method of AlGaN-GaN HEMTs device based on AlScN passivation according to claim 3, characterized in that, The process of growing AlScN thin films with a thickness of 20 nm to 120 nm on the AlGaN barrier layer using a magnetron sputtering apparatus includes: The vacuum level in the sputtering reaction chamber was reduced to 1×10⁻⁶. -6 Torr, and heat the heterojunction material to the target temperature; Pure argon gas is introduced into the sputtering reaction chamber to pre-sputter the Al target. The sputtering power is DC 90W to 110W and the sputtering time is 5min to 10min to remove impurities from the surface of the Al target. Stop Al target pre-sputtering and pre-sputter the Sc target with a sputtering power of RF 65W to 85W and a sputtering time of 5 to 10 minutes to remove impurities from the Sc target surface; An argon-nitrogen mixture of 1:1.5 to 1:3 is introduced into the sputtering reaction chamber, and the Al target and Sc target are pre-sputtered simultaneously. The sputtering power is DC 100W and RF 75W, and the sputtering time is 5min to 10min, so that the voltage and current of the Al target and Sc target in the sputtering reaction chamber reach a stable state. Under the above stable conditions, an AlScN thin film with a thickness of 20 nm to 120 nm is grown on the AlGaN barrier layer, and the reaction time is 25 min to 30 min.

5. The method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation according to claim 1, characterized in that, An opening region slightly larger than the source and drain electrode regions is formed at both ends of the AlScN passivation layer using overexposure photolithography, including: Photolithography was performed on the source and drain electrode regions of the AlScN passivation layer; Photoresist is spin-coated in the source and drain electrode regions; By controlling the exposure time, the photoresist in the source and drain electrode areas is increased to form an opening region.

6. The method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation according to claim 5, characterized in that, The exposure time is 500ms to 1s.

7. The method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation according to claim 1, characterized in that, Omegametal is evaporated and annealed in the patterned regions of the source and drain electrodes to form ohmic contacts, resulting in source and drain electrodes, including: The vacuum level in the reaction chamber of the electron beam evaporation stage was evacuated to 2 × 10⁻⁶. -6 Torr; An ohmic metal consisting of four layers of metal—Ti, Al, Ni, and Au—is evaporated from bottom to top in the source and drain electrode pattern regions. In a rapid annealing furnace, the ohmic metal is annealed to allow the ohmic metal in the source and drain electrode regions to sink into the AlGaN barrier layer to form an ohmic contact, thus obtaining the source and drain electrodes.

8. The method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation according to claim 7, characterized in that, The process of annealing the ohmic metal includes: Nitrogen gas was introduced into the rapid annealing furnace for 10 minutes, and then the furnace temperature was set to 860℃ in the nitrogen atmosphere for 60 seconds of high-temperature annealing.

9. The method for fabricating AlGaN-GaN HEMTs devices based on AlScN passivation according to claim 1, characterized in that, Evaporating Schottky gate metal within the gate trench and the gate electrode region to form a T-shaped gate electrode includes: The vacuum level in the reaction chamber of the electron beam evaporation stage was evacuated to 2 × 10⁻⁶. -6 Torr; Schottky gate metal, consisting of two layers of metal, Ni and Au, is evaporated from bottom to top within the gate trench and the gate electrode region.

10. An AlGaN-GaN HEMTs device based on AlScN passivation, characterized in that, The device is fabricated using the fabrication method of AlGaN-GaN HEMTs based on AlScN passivation as described in any one of claims 1 to 9.

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