High-voltage non-crosstalk darlington transistor and preparation method thereof

Abstract

The application provides a high-voltage crosstalk-free Darlington transistor device and a preparation method thereof. A combined terminal structure is adopted to effectively avoid the electric field terminal edge concentration effect, effectively improve the device breakdown voltage, and ensure that the voltage reaches 850V or above. An N-type isolation cutoff strip structure is arranged between T1 and T2 tubes, effectively suppresses the amplification crosstalk abnormality of the high-voltage Darlington transistor, improves the gain of the power amplifier circuit, and avoids the abnormal loss of harmonics. The T2 tube is opened to form a ring structure, and a parallel acceleration diode loop is formed to compound and discharge the excess charge accumulated in the emitter during the Darlington transistor shutdown process, reduce the switching loss of the power supply, and improve the efficiency and power density of the power converter.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, specifically to Darlington transistors and their fabrication methods. Background Technology

[0002] High-voltage Darlington power transistors are widely used in ignition and speed control circuits of gasoline engines, regulation circuits of regulated power supplies, and inverter circuits, and have a broad market prospect. A Darlington transistor is a semiconductor device consisting of two or more bipolar transistors connected together. This structure was invented to meet requirements such as high gain and high voltage withstand capability. Specific application circuits can be found in [the documentation / reference needed]. Figure 1 The circuit shows that the emitters and bases of two adjacent NPN transistors are connected. Each base switching device is connected to the logic circuit. A low base input current can drive multiple NPN transistors and shorten the turn-off delay of multiple NPN transistors, which greatly reduces switching losses, significantly reduces packaging costs, and saves circuit board space.

[0003] Current Darlington transistors primarily employ a resistive band structure. However, due to increasingly demanding requirements in system applications, higher demands are being placed on the operating range of these devices. In many applications, achieving low power, high power, and high reverse voltage requires control, necessitating that Darlington transistors conduct and operate under low current. In power device design, the drift region concentration and width are designed based on the breakdown voltage. However, in practical applications, the concentrated electric field at the device's edges can lead to premature breakdown. Therefore, a well-designed termination structure is needed to reduce the excessive dependence on the high-resistivity thickness for breakdown voltage, minimize the impact of high-resistivity material thickness on forward conduction parameters, and improve the reverse breakdown capability of the Darlington transistor and the switching efficiency of the power supply.

[0004] When Darlington devices are used in LLC (a resonant circuit that achieves constant output voltage by controlling the switching frequency) applications, high switching efficiency is required. The circuit essentially achieves zero-voltage turn-on, but the turn-off power remains high. Turn-off losses affect the temperature rise of the power transistor and the circuit efficiency (this is particularly noticeable in high-voltage applications). The turn-off speed significantly impacts turn-off power consumption; therefore, circuit applications require high switching efficiency. f The size should be as small as possible. Therefore, the emitter structure needs to be optimized. A parallel accelerating diode is designed in the T2 emitter region to recombine and discharge the excess charge accumulated in the emitter during the Darlington transistor turn-off process. This significantly improves the turn-off speed and increases the efficiency and power density of the power converter circuit.

[0005] The amplification parameter of a Darlington transistor is the product of two transistors, and its amplification factor is relatively large. However, this also makes it susceptible to amplification crosstalk, which can cause the amplifier circuit gain to fail. Therefore, when designing the device, it is necessary to design isolation cutoff strips for transistors T1 and T2 to prevent amplification crosstalk distortion.

[0006] In conclusion, it is essential to develop a novel high-voltage crosstalk-free Darlington transistor device with a simple manufacturing process and high reliability, featuring a combined terminal and isolation cutoff strip structure. Summary of the Invention

[0007] The purpose of this invention is to provide a high-voltage, crosstalk-free Darlington transistor with a combined terminal and isolation cutoff strip structure, which avoids the field concentration effect at the terminal edge and effectively improves the device breakdown voltage. An isolation cutoff strip structure is set between transistors T1 and T2 to prevent minority carriers injected into the emitter region of transistor T1 from being directly absorbed by transistor T2, thus amplifying crosstalk. A parallel diode structure is designed at the emitter of the Darlington transistor to recombine and discharge excess charge accumulated in the emitter during the turn-off process of the Darlington transistor, which significantly improves the turn-off speed.

[0008] The technical solution of this invention is: a method for fabricating a high-voltage crosstalk-free Darlington transistor, comprising the following steps:

[0009] Step 1: Use a high resistivity 49-52Ω·cm silicon N-type crystal orientation single crystal wafer, dope phosphorus oxychloride on both sides, and form a deep junction substrate region through a high temperature diffusion process. Then, perform isolation oxidation on both sides of the substrate region to form an oxide layer, substrate region, high resistivity region, substrate region, oxide layer structure. Then, remove the oxide layer and substrate region on one side through a grinding and polishing process to expose the high resistivity region.

[0010] Step 2: A silicon dioxide layer is grown on the surface of the high-resistivity region exposed in Step 1 using thermal oxidation. A junction termination extension window is created using photolithography, and 1E13-1E14 P-type boron ions are implanted. The boron impurities are then diffused to a certain depth using a high-temperature oxidation diffusion process to form P. - Doped region, P - A silicon dioxide oxide layer is grown on the doped region to form a junction termination extension structure;

[0011] Step 3: Use photolithography to etch the silicon dioxide layer to form the P layer. - Two base region windows adjacent to the doped region are then enclosed by a silicon dioxide layer as a masking layer. Boron ion implantation of type 1E14-8E14P is then performed, and the impurity boron is diffused to a certain depth using a high-temperature oxidation-diffusion process to form P. + Doped region, P + A silicon dioxide oxide layer is grown on the doped region to form the base region structure of transistors T1 and T2, wherein a ring-shaped accelerating diode structure is formed in transistor T2.

[0012] Step 4: Using photolithography to etch the silicon dioxide layer, a third doping window is simultaneously created above the base doped region, in the die edge scribe groove area, and between T1 and T2. Liquid phosphorus is used as the impurity source in the furnace tube to dope phosphorus atoms, forming the emitter N-type doped region, the terminal N-type doped region, and the isolation N-type doped region for T1 and T2 tubes, thus completing the combined terminal structure and the isolation stop bar structure. This step also preserves the thermally oxidized PSG formed during the doping process.

[0013] Step 5: Using a hydrogen-oxygen synthesis oxidation process and a high-temperature diffusion process, Darlington transistors T1 and T2 are made capable of current amplification h. FE ;

[0014] Step 6: A silicon dioxide layer is grown by CVD deposition and a furnace tube high-temperature annealing process is used to form an isolation oxide layer under the front metal.

[0015] Step 7: Using photolithography to etch the silicon dioxide layer, bare silicon contact holes are made in the die edge scribing groove area, P-type base doped area, and N-type emitter doped area above the base doped area.

[0016] Step 8: Deposit a front electrode metal layer using PVD process, and form a bonding metal layer for the device finished lead using photolithography and wet etching process. Connect T1 and T2 in series, and connect the diode in T2 in parallel with the emitter region. Connect an accelerating diode in parallel in the base region and emitter region of the Darlington transistor to form a complete Darlington transistor structure.

[0017] Step 9: Finally, a low-temperature alloying process for furnace tubes is used to ensure good ohmic contact between the front metal layer and the contact holes.

[0018] Step 10: Form a protective layer on the front metal surface using polyimide photoresist, and then form the bonding window using photolithography.

[0019] Step 11: Thin the back side of the silicon substrate to the required thickness using mechanical grinding, and then use a wet silicon etching process to etch and grind the exposed silicon surface to a thickness of 2μm-5μm.

[0020] Step 12: Deposit a back electrode metal layer on the back side of the silicon substrate by evaporation to serve as the cathode metal layer.

[0021] Furthermore, the diffusion depth of the substrate region of the deep junction in step one is 165μm-230μm; the thickness of the high-resistivity region is 70μm-95μm.

[0022] The diffusion junction depth of the terminal extension region in step two is 7-10 μm, and the junction depth of the base region in step three is 17-25 μm.

[0023] Furthermore, P - Terminal extended doped region capping P + The base region doping window is 50-65 μm.

[0024] Furthermore, the thickness of the isolation oxide layer beneath the front metal described in step six is ​​0.6-0.9 μm;

[0025] The thickness of the front electrode metal layer mentioned in step eight is 4.0-5.5 μm.

[0026] Furthermore, in step three, the high-temperature oxidation diffusion process employs a hydrogen-oxygen synthesis oxidation process for thermal oxidation, with the process time controlled at 360 min. The furnace tube temperature is controlled at 995℃-1005℃, the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min, the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min, and the hydrogen chloride gas flow rate in the furnace tube is controlled at 230 ml / min-270 ml / min. The diffusion process employs a nitrogen diffusion process, with the time controlled at 230 min, the furnace tube temperature controlled at 1195℃-1205℃, the nitrogen gas flow rate controlled at 9 L / min-10 L / min, and the oxygen gas flow rate controlled at 30 ml / min-50 ml / min.

[0027] Furthermore, the liquid phosphorus source mentioned in step four is used as an impurity source to dope impurity phosphorus atoms, with a doping sheet resistance of 12-18 ohms per block.

[0028] Furthermore, in step five, the hydrogen-oxygen synthesis oxidation process is controlled for a time of 300 min; the furnace tube temperature is controlled at 895℃-905℃; the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min; the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min; and the hydrogen chloride gas flow rate in the furnace tube is controlled at 230 ml / min-270 ml / min. The high-temperature diffusion process uses nitrogen diffusion, with a time controlled at 120 min; the furnace tube temperature is controlled at 1145℃-1155℃; the nitrogen gas flow rate is controlled at 7.2 L / min-8.8 L / min; and the oxygen gas flow rate is controlled at 720 ml / min-880 ml / min.

[0029] In step nine, the process time in the furnace tube low-temperature alloying process is controlled at 15-25 minutes in the isothermal section; the temperature inside the furnace tube is controlled at 468℃ / min-472℃ / min; and the hydrogen gas flow rate inside the furnace tube is controlled at 5.5L / min-6.5L / min.

[0030] The present invention also provides a high-voltage crosstalk-free Darlington transistor prepared according to the above-described method for preparing a high-voltage crosstalk-free Darlington transistor.

[0031] Furthermore, a junction P is opened on the high-resistivity region. - The N+ doped region formed by the terminal extension structure and the scribe line area at the die edge creates an N+ doped region. + N - P - The combined terminal structure;

[0032] An N-type isolation cutoff strip structure is provided between Darlington transistors T1 and T2;

[0033] T2 transistors are arranged in a ring structure and connected in parallel to form an accelerating diode circuit.

[0034] Furthermore, the reverse working voltage of the CB reaches over 850V.

[0035] The positive and progressive effects of this invention are as follows:

[0036] This invention provides a high-voltage, crosstalk-free Darlington transistor device with a combined terminal and isolation cut-off strip structure, as well as its fabrication method. An N-type doped region (digging groove area) is set at the die edge to effectively isolate the influence of the surface electric field and cut off the surface channel current; P - The terminal extension structure weakens the phenomenon of electric field intensity concentration in the space charge region during reverse bias, forming N + N - P - The combined terminal structure effectively improves the device breakdown voltage. An N-type isolation cutoff strip structure is set between transistors T1 and T2 to avoid amplification crosstalk abnormalities caused by the direct absorption of minority carriers injected into the emitter region of transistor T1 by transistor T2. A parallel diode structure is designed at the emitter of the Darlington transistor to recombine and discharge the excess charge accumulated in the emitter during the turn-off process of the Darlington transistor, which significantly improves the turn-off speed. Attached Figure Description

[0037] Figure 1 This is a typical application circuit for Darlington circuits.

[0038] Figure 2 This is a cross-sectional view after step twelf of a specific embodiment of the present invention;

[0039] Wherein: 1 is silicon substrate, 2 is high-resistivity region, 3 is terminal extended P-doped region, 4 is base region P-type doped region, 5 is ring diode doped region, 6 is emitter region N-type doped region, 7 is terminal cutoff N-type doped region, 8 is isolation cutoff strip N-type doped region, 9 is front anode metal layer, 10 is front imine passivation layer, and 11 is back cathode metal layer. Detailed Implementation

[0040] The present invention will now be further described with reference to the accompanying drawings.

[0041] See Figure 2 In specific embodiment 1, the present invention provides a high-voltage crosstalk-free Darlington transistor device with a combined terminal and isolation stop bar structure and a method for its fabrication, characterized by comprising the following steps:

[0042] Step 1: Use high resistivity 49-52Ω·cm silicon N-type silicon. <111> The crystal-oriented single wafer is doped with phosphorus oxychloride on both sides (the surface cube after doping is <0.4Ω·cm). A substrate region with a diffusion junction depth of 175μm is formed through a high-temperature diffusion process (1250℃-1300℃). Isolation oxidation is performed on both sides of the substrate region, and the oxide layer thickness is 2.0μm, forming an oxide layer, substrate region, high-resistivity region, substrate region, and oxide layer structure. Through a grinding and polishing process, the oxide layer and substrate region on one side are removed, exposing the high-resistivity region, and the high-resistivity layer thickness is 77-91μm.

[0043] Step 2: A silicon dioxide layer is grown on the surface of the high-resistivity region using thermal oxidation at a temperature of 995-1005℃ for 45 minutes. The oxygen gas flow rate is controlled at 5.9 L / min-6.1 L / min, and the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min. A junction termination extension window is created using photolithography, and 1E13-1E14P-type boron ions are implanted. A high-temperature oxidation diffusion process is then used to diffuse the impurity boron to a depth of 7-10 μm, forming a P-type junction. - Doped region, P - A 0.65-1.0 μm silicon dioxide oxide layer is grown on the doped region to form a junction termination extension structure;

[0044] Step 3: Use photolithography to etch the silicon dioxide layer to form the P layer. - Two base region windows adjacent to the doped region are then enclosed by a silicon dioxide layer as a masking layer. Boron ion implantation of type 1E14-8E14P is then performed, and a high-temperature oxidation-diffusion process is used to diffuse the impurity boron junction to a depth of 17-25 μm, forming a P0 group. + Doped region, P +A 0.5-1.0 μm silicon dioxide oxide layer is grown on the doped region to form the base structure of transistors T1 and T2. A ring structure is formed in transistor T2 to create an accelerating diode structure. The high-temperature oxidation-diffusion process uses a hydrogen-oxygen synthesis oxidation process with a process time controlled at 360 min. The furnace temperature is controlled at 995℃-1005℃, the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min, the hydrogen gas flow rate is controlled at 10.3 L / min-10.7 L / min, and the hydrogen chloride gas flow rate is controlled at 230 ml / min-270 ml / min. The diffusion process uses a nitrogen diffusion process with a time controlled at 230 min, the furnace temperature is controlled at 1195℃-1205℃, the nitrogen gas flow rate is controlled at 9 L / min-10 L / min, and the oxygen gas flow rate is controlled at 30 ml / min-50 ml / min.

[0045] Step 4: Using photolithography to etch the silicon dioxide layer, a third doping window is simultaneously created above the base doped region, at the die edge (dicing groove area), and between T1 and T2. A liquid phosphorus source is used as the impurity source in the furnace tube to dope phosphorus atoms, achieving a sheet resistance of 12-18 ohms per square block. This forms the emitter N-type doped region, the terminal N-type doped region, and the isolation N-type doped region for tubes T1 and T2, completing the combined termination structure and isolation stop bar structure. Furthermore, this step preserves the thermally oxidized PSG formed during the doping process.

[0046] Step 5: Using a hydrogen-oxygen synthesis oxidation process and a high-temperature diffusion process, Darlington transistors T1 and T2 are made capable of current amplification h. FE The hydrogen-oxygen synthesis oxidation process is controlled for 300 min; the furnace tube temperature is controlled at 895℃-905℃; the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min; the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min; and the hydrogen chloride gas flow rate in the furnace tube is controlled at 230 ml / min-270 ml / min. The high-temperature diffusion process uses nitrogen diffusion, with a time controlled at 120 min; the furnace tube temperature is controlled at 1145℃-1155℃; the nitrogen gas flow rate is controlled at 7.2 L / min-8.8 L / min; and the oxygen gas flow rate is controlled at 720 ml / min-880 ml / min.

[0047] Step Six: Grow a 0.6-0.9 μm thick silicon dioxide layer using CVD deposition. The deposition temperature is 410-450℃, and the deposition time is 75-105 seconds. At 410-450℃, the SiH4 process flow rate is controlled at 15-45 SCCM, and the PH3 process flow rate is controlled at 20-50 SCCM. The gas pressure is 260-310 mtorr. A high-temperature furnace tube annealing process is then used to improve the oxide layer quality, forming an insulating oxide layer beneath the front metal. The constant temperature section of the furnace tube annealing process is controlled for 60 minutes; the furnace tube temperature is controlled at 1195℃ / min-1105℃ / min; the oxygen gas flow rate is controlled at 7.2 L / min-8.8 L / min; and the hydrogen chloride gas flow rate is controlled at 320 mL / min-480 mL / min.

[0048] Step 7: Using photolithography to etch the silicon dioxide layer, bare silicon contact holes are made in the die edge scribing groove area, P-type base doped area, and N-type emitter doped area above the base doped area.

[0049] Step 8: Deposit a 4.0-5.5μm thick front electrode metal layer using PVD process at a deposition temperature of 110±5℃. Use photolithography and wet etching process to form the bonding metal layer of the device finished lead. Connect T1 and T2 in series. At the same time, connect the diode in T2 in parallel with the emitter region. Connect an accelerating diode in parallel in the base region and emitter region of the Darlington transistor to form a complete Darlington transistor structure.

[0050] Step 9: Finally, a low-temperature alloying process for furnace tubes is adopted to ensure good ohmic contact between the front metal layer and the contact hole. The process time in the isothermal section of the low-temperature alloying process for furnace tubes is controlled at 15-25 minutes. The temperature inside the furnace tube is controlled at 468℃ / min-472℃ / min, and the hydrogen gas flow rate inside the furnace tube is controlled at 5.5L / min-6.5L / min.

[0051] Step 10: Form a protective layer on top of the front metal using polyimide photoresist, and then use photolithography to form the bonding window. The thickness of the polyimide protective film is 3.5-5.0 μm.

[0052] Step 11: The back side of the silicon substrate is thinned to the required thickness by mechanical polishing, and then the exposed silicon surface is etched and polished to a thickness of 2μm-5μm using a wet silicon etching process to remove the mechanical damage layer and stress.

[0053] Step 12: A 1.9 μm thick back electrode metal layer is deposited on the back side of the silicon substrate by evaporation to serve as the cathode metal layer. From bottom to top, a titanium layer, a nickel layer, and a silver layer are sequentially arranged.

[0054] See Figure 1The Darlington transistor device after step 12 includes, from top to bottom, an imine passivation layer 10, an anode metal layer 9, an isolation cutoff strip-shaped N-type doped region 8, a termination cutoff N-type doped region 7, an emitter N-type doped region 6, a ring diode doped region 5, a base P-type doped region 4, and a termination extension P-type doped region. - Doped region 3, high-resistivity region 2, silicon substrate 1, back cathode metal layer 11.

[0055] A high-voltage, crosstalk-free Darlington transistor device with a combined termination and isolation cutoff strip structure has a CB reverse operating voltage of 850V and a CE reverse breakdown voltage of 400V. FE The magnification range is selectable from 225 to 1500.

[0056] This embodiment provides a high-voltage, crosstalk-free Darlington transistor device with a combined termination and isolation stop bar structure. It includes an N-type heavily doped substrate, on which a high-resistivity layer is formed using a triple diffusion process. A lightly doped P-type window region is photolithographically formed on the high-resistivity layer, and a termination extension structure is formed through diffusion oxidation. Two adjacent doped windows of the same type form the base P-type doped regions of Darlington transistors T1 and T2. A third doped window is simultaneously formed above the base doped region, at the die edge, and between T1 and T2, forming the emitter N-type doped region, thus completing the combined termination and isolation stop bar structure. A ring structure is formed in T2 to create an accelerating diode loop, improving the turn-off speed of the Darlington transistor. Contact holes are formed in the P-type doped region of the base region and the N-type doped region of the emitter region, and a front electrode metal layer is deposited to form an ohmic contact between the front electrode metal layer and the doped filling layer at the window. T1 and T2 are connected in series. A protective layer is formed on the front electrode metal layer using polyimide photoresist, and a bonding window is formed using photolithography. After mechanical polishing, a back electrode metal layer is deposited as the cathode metal layer. The combined termination structure effectively avoids the field concentration effect at the termination edge, effectively improves the device breakdown voltage, and ensures that the voltage reaches above 850V. An N-type isolation cutoff strip structure is set between T1 and T2 to effectively suppress the amplification crosstalk abnormality of the high-voltage Darlington transistor, improve the gain of the power amplifier circuit, and avoid harmonic loss abnormalities. A ring structure is formed in T2 and connected in parallel to form an accelerating diode circuit for recombination and discharge of excess charge accumulated in the emitter during the turn-off process of the Darlington transistor, reducing the switching loss of the power supply and improving the efficiency and power density of the power converter.

[0057] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-voltage, crosstalk-free Darlington transistor, characterized in that, Includes the following steps: Step 1: Use a high resistivity 49-52Ω·cm silicon N-type crystal orientation single crystal wafer, dope phosphorus oxychloride on both sides, and form a deep junction substrate region through a high temperature diffusion process. Then, perform isolation oxidation on both sides of the substrate region to form an oxide layer, substrate region, high resistivity region, substrate region, oxide layer structure. Then, remove the oxide layer and substrate region on one side through a grinding and polishing process to expose the high resistivity region. Step 2: A silicon dioxide layer is grown on the surface of the high-resistivity region exposed in Step 1 using thermal oxidation. A junction termination extension window is created using photolithography, and 1E13-1E14 P-type boron ions are implanted. The boron impurities are then diffused to a certain depth using a high-temperature oxidation diffusion process to form P. - Doped region, P - A silicon dioxide oxide layer is grown on the doped region to form a junction termination extension structure; Step 3: Use photolithography to etch the silicon dioxide layer to form the P layer. - Two base region windows adjacent to the doped region are then enclosed by a silicon dioxide layer as a masking layer. Boron ion implantation of type 1E14-8E14P is then performed, and the impurity boron is diffused to a certain depth using a high-temperature oxidation-diffusion process to form P. + Doped region, P + A silicon dioxide oxide layer is grown on the doped region to form the base region structure of transistors T1 and T2, wherein a ring-shaped accelerating diode structure is formed in transistor T2. Step 4: Using photolithography to etch the silicon dioxide layer, a third doping window is simultaneously created above the base doped region, in the die edge scribe groove area, and between T1 and T2. Liquid phosphorus is used as the impurity source in the furnace tube to dope phosphorus atoms, forming the emitter N-type doped region, the terminal N-type doped region, and the isolation N-type doped region for T1 and T2 tubes, thus completing the combined terminal structure and the isolation stop bar structure. This step also preserves the thermally oxidized PSG formed during the doping process. Step 5: Using a hydrogen-oxygen synthesis oxidation process and a high-temperature diffusion process, Darlington transistors T1 and T2 are made capable of current amplification h. FE ; Step 6: A silicon dioxide layer is grown by CVD deposition and a furnace tube high-temperature annealing process is used to form an isolation oxide layer under the front metal. Step 7: Using photolithography to etch the silicon dioxide layer, bare silicon contact holes are made in the die edge scribing groove area, P-type base doped area, and N-type emitter doped area above the base doped area. Step 8: Deposit a front electrode metal layer using PVD process, and form a bonding metal layer for the device finished lead using photolithography and wet etching process. Connect T1 and T2 in series, and connect the diode in T2 in parallel with the emitter region. Connect an accelerating diode in parallel in the base region and emitter region of the Darlington transistor to form a complete Darlington transistor structure. Step 9: Finally, a low-temperature alloying process for furnace tubes is used to ensure good ohmic contact between the front metal layer and the contact holes. Step 10: Form a protective layer on the front metal surface using polyimide photoresist, and then form the bonding window using photolithography. Step 11: Thin the back side of the silicon substrate to the required thickness using mechanical grinding, and then use a wet silicon etching process to etch and grind the exposed silicon surface to a thickness of 2μm-5μm. Step 12: Deposit a back electrode metal layer on the back side of the silicon substrate by evaporation to serve as the cathode metal layer.

2. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, The diffusion depth of the substrate region in the deep junction mentioned in step one is 165μm-230μm; the thickness of the high-resistivity region is 70μm-95μm. The diffusion junction depth of the terminal extension region in step two is 7-10 μm, and the junction depth of the base region in step three is 17-25 μm.

3. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, P - Terminal extended doped region capping P + The base region doping window is 50-65 μm.

4. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, The thickness of the isolation oxide layer under the front metal mentioned in step six is ​​0.6-0.9 μm; The thickness of the front electrode metal layer mentioned in step eight is 4.0-5.5 μm.

5. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, In step three, the high-temperature oxidation diffusion process employs a hydrogen-oxygen synthesis oxidation process for thermal oxidation, with a process time controlled at 360 min. The furnace tube temperature is controlled at 995℃-1005℃, the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min, the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min, and the hydrogen chloride gas flow rate in the furnace tube is controlled at 230 ml / min-270 ml / min. The diffusion process employs a nitrogen diffusion process, with a time controlled at 230 min, the furnace tube temperature controlled at 1195℃-1205℃, the nitrogen gas flow rate controlled at 9 L / min-10 L / min, and the oxygen gas flow rate controlled at 30 ml / min-50 ml / min.

6. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, In step four, the liquid phosphorus source is used as an impurity source to dope phosphorus atoms, with a doping sheet resistance of 12-18 ohms per block.

7. The method for fabricating a high-voltage crosstalk-free Darlington transistor according to claim 1, characterized in that, In step five, the hydrogen-oxygen synthesis oxidation process is controlled for a time of 300 min; the furnace tube temperature is controlled at 895℃-905℃; the oxygen gas flow rate for hydrogen-oxygen synthesis is controlled at 5.9 L / min-6.1 L / min; the hydrogen gas flow rate for hydrogen-oxygen synthesis is controlled at 10.3 L / min-10.7 L / min; and the hydrogen chloride gas flow rate in the furnace tube is controlled at 230 ml / min-270 ml / min. The high-temperature diffusion process uses nitrogen diffusion, with a time controlled at 120 min; the furnace tube temperature is controlled at 1145℃-1155℃; the nitrogen gas flow rate is controlled at 7.2 L / min-8.8 L / min; and the oxygen gas flow rate is controlled at 720 ml / min-880 ml / min. In step nine, the process time in the furnace tube low-temperature alloying process is controlled at 15-25 minutes in the isothermal section; the temperature inside the furnace tube is controlled at 468℃ / min-472℃ / min; and the hydrogen gas flow rate inside the furnace tube is controlled at 5.5L / min-6.5L / min.

8. A high-voltage crosstalk-free Darlington transistor prepared by any one of the high-voltage crosstalk-free Darlington transistor preparation methods according to any one of claims 1-7.

9. The high-voltage crosstalk-free Darlington transistor according to claim 8, characterized in that: A junction P is opened on the high-resistivity region. - The N+ doped region formed by the terminal extension structure and the scribe line area at the die edge creates an N+ doped region. + N - P - The combined terminal structure; An N-type isolation cutoff strip structure is provided between Darlington transistors T1 and T2; T2 transistors are arranged in a ring structure and connected in parallel to form an accelerating diode circuit.

10. The high-voltage crosstalk-free Darlington transistor according to claim 8, characterized in that: The reverse working voltage of CB reaches over 850V.

Images