An integrated method of vertical channel complementary field effect transistor

Abstract

The application provides an integrated method of vertical channel complementary field effect transistor, and belongs to the technical field of ultra large scale integrated circuit manufacturing technology. The application realizes the integration of vertical channel complementary field effect transistor in the vertical direction, can reduce the projection area of a circuit unit, realizes further miniaturization, and continues Moore's law. Compared with the prior art, the application can reduce the interconnection line length under the same device density, reduce the delay and power consumption on the interconnection line, and improve the performance of the circuit unit.

Description

Technical Field

[0001] This invention belongs to the field of very large-scale integrated circuit manufacturing technology, and relates to an integration scheme for vertical channel complementary field-effect transistors in the vertical direction. Background Technology

[0002] As Moore's Law progresses, proportional scaling gradually reaches the lithographic and physical limits of device size. Short-channel effects and continuously rising miniaturization costs hinder the scaling down process. Gate length and via size compete with each other and are simultaneously limited by the fixed CGP size of each node. Therefore, as a continuation of Moore's Law, the proposed vertical channel structure frees the gate length from the limitation of projected area, alleviates the short-channel effect, and has lower parasitic resistance and capacitance.

[0003] Currently, reported integration schemes for vertical channel devices employ horizontal interconnect wiring on a single layer of devices. The minimum isolation distance between N-type and P-type devices remains a limitation, hindering further miniaturization of circuit cell area. Furthermore, the length of horizontal wiring increases significantly with integration density and the number of devices. Compared to the device's own delay, the RC delay on the interconnect becomes the main component of circuit delay, leading to increased power consumption in the circuit cell.

[0004] Therefore, in order to further reduce the area of ​​circuit units and reduce circuit delay and power consumption, the industry urgently needs a new integration solution for vertical channel devices. Summary of the Invention

[0005] To address the above problems, this invention provides a method for integrating N-type and P-type devices in the vertical direction, which is beneficial for achieving circuit area miniaturization and performance improvement.

[0006] The technical solution of the present invention is as follows:

[0007] A method for integrating a vertical-channel complementary field-effect transistor includes the following steps:

[0008] A. Epitaxially form a heavily doped lower active region on the substrate to serve as the bottom source / drain of the lower vertical channel device and form inter-device isolation;

[0009] B. Deposit the dummy gate stack of the underlying device;

[0010] C. Deposit a sacrificial layer material, and pattern the sacrificial layer by photolithography and anisotropic etching. Its size and shape define the common interconnect of the top active region of the lower device and the bottom active region of the upper device.

[0011] D. Deposit a dummy gate stack for the upper-layer device;

[0012] E. Etch deep holes to expose the active region surface described in step A;

[0013] F. The lower device channel, the top active region of the lower device, the bottom active region of the upper device, the upper device channel, and the top source region of the upper device are formed sequentially through selective epitaxy.

[0014] G. Form an interlayer dielectric, remove local interconnect sacrificial layers, and fill with interconnect metal;

[0015] H. Remove the dummy gate sacrificial layer and fill with HKMG material;

[0016] I. Forming metal contacts at each end of the device;

[0017] J. Integrate vertical channel complementary field-effect transistors in the vertical direction using existing back-end processes.

[0018] Furthermore, step A specifically includes:

[0019] A1. Epitaxially grow a heavily doped semiconductor layer on a semiconductor substrate. The doping can be formed by in-situ epitaxy or by ion implantation.

[0020] A2. Deposit a hard mask on the active region and pattern it using photolithography; the area of ​​the mask defines the area of ​​the active region.

[0021] A3. The bottom active region of the underlying device is formed by etching with a hard mask pattern, and the isolation between devices is formed.

[0022] Furthermore, step B specifically includes:

[0023] B1. Deposit a dielectric layer as the gate isolation material for the underlying device to define the length of the extended region (LDD) between the lower active region and the gate;

[0024] B2. Deposit a sacrificial layer material as a dummy gate for the underlying device, the thickness of which defines the gate length of the underlying device;

[0025] B3. The dummy gate layer is patterned using photolithography and anisotropic etching to form gate lines;

[0026] B4. Deposit a dielectric layer as the gate isolation material for the underlying device and planarize it using CMP to define the active region thickness and the length of the extended region (LDD) between the active region and the gate.

[0027] Furthermore, step D specifically includes:

[0028] D1. Deposit a dielectric layer as the gate isolation material for the upper-layer device and planarize it using CMP to define the thickness of the lower active region and the length of the extended region (LDD) between it and the gate;

[0029] D2. Deposit a sacrificial layer material as a dummy gate for the upper-layer device, the thickness of which defines the gate length of the upper-layer device;

[0030] D3. The dummy gate layer is patterned using photolithography and anisotropic etching to form gate lines;

[0031] D4. Deposit a dielectric layer as the gate isolation material for the upper-layer device and planarize it using CMP to define the length of the extended region (LDD) between the active region and the gate.

[0032] Furthermore, step F specifically includes:

[0033] F1. An extended region between the bottom active region and the gate of the lower-level device is formed by selective epitaxy;

[0034] F2. Lightly doped channels for the underlying device are formed by selective epitaxy;

[0035] F3. Selectively epitaxially form the extended region between the top active region and the gate of the lower device and the heavily doped source / drain, and its top interface should be within the thickness range of the sacrificial layer material described in step C;

[0036] F4. Selective epitaxy is used to form heavily doped bottom source / drain regions and extended regions between the active region and the gate of the upper-layer device;

[0037] F5. Lightly doped channels for upper-layer devices are formed through selective epitaxy;

[0038] F6. Selective epitaxy is used to form the extended region between the top active region and the gate of the upper-layer device, as well as the heavily doped source / drain.

[0039] Furthermore, step G specifically includes:

[0040] G1. Deposit an interlayer medium and planarize using CMP;

[0041] G2. The surface of the local interconnect sacrificial layer is exposed by photolithography etching;

[0042] G3. Remove the sacrificial layer material by isotropic etching;

[0043] G4. By isotropically growing locally interconnected metallic materials, it is ensured that the voids formed after the removal of the sacrificial layer in G2 are completely filled.

[0044] G5. Remove the metallic material grown on top of the dielectric in step G1 by anisotropic etching.

[0045] Furthermore, step H specifically includes:

[0046] H1. A dummy gate layer for both upper and lower devices is simultaneously exposed by defining a window through photolithography and anisotropic etching;

[0047] H2. Removal of dummy gate material through isotropic etching;

[0048] H3. By sequentially filling the gate oxide layer material and the metal gate material with isotropic conformal properties, the voids formed after the removal of the dummy gate in step H2 are completely filled.

[0049] H4. Remove the metal and gate dielectric material grown on top of the dielectric in step H1 by anisotropic etching.

[0050] Furthermore, step I specifically includes:

[0051] I1. Deposit a layer of medium for interlayer isolation and achieve planarization through CMP;

[0052] I2. Contact holes at each end of the device are formed by photolithography and anisotropic etching;

[0053] I3. Each contact hole is filled with Metal 0;

[0054] I4. Perform CMP on the metal 0 to separate the conductive layers between devices and achieve device isolation.

[0055] Furthermore, the substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, or a GOI substrate.

[0056] Furthermore, the filler metal Metal 0, which serves as the conductive layer, is required to have low resistivity, and can be selected from materials such as W and Cu.

[0057] The advantages and positive effects of this invention are as follows:

[0058] 1) Compared with the existing horizontal integration method of vertical channel devices, the present invention adopts vertical N / P device integration, which can reduce the projected area of ​​circuit unit, achieve further miniaturization, and continue Moore's Law;

[0059] 2) This invention can reduce interconnect length, reduce latency and power consumption on interconnects, and improve circuit unit performance under the same device density. Attached Figure Description

[0060] Figures 1 to 19 These are schematic diagrams illustrating the key processes for fabricating vertically integrated vertical-channel CMOS devices in a specific embodiment of the present invention. In each figure, (a) is a top view, (b) is a cross-sectional view along A-A' in (a), and (c) is a cross-sectional view along B-B' in (a), wherein:

[0061] Figure 1 In the substrate, the heavily doped active regions of the bottom source and drain of the lower device are formed by in-situ doping epitaxy, and STI isolation is formed in the active regions;

[0062] Figure 2 The bottom gate isolation dielectric layer and the dummy gate sacrificial layer of the lower device are deposited sequentially;

[0063] Figure 3 Define the gate lines graphically for the dummy gate layer of the lower-level device;

[0064] Figure 4 A top gate isolation dielectric layer for the underlying device is deposited and planarized using CMP.

[0065] Figure 5 Deposition of sacrificial layer medium;

[0066] Figure 6 The sacrificial layer material is patterned to form local interconnect lines;

[0067] Figure 7 The bottom gate isolation dielectric layer of the upper device is deposited and planarized by CMP.

[0068] Figure 8 Deposit a dummy gate sacrificial layer for the upper-layer device;

[0069] Figure 9 Define the gate lines graphically for the dummy gate layer of the upper-layer device;

[0070] Figure 10 A top gate isolation dielectric layer for the upper-layer device is formed by deposition and CMP planarization;

[0071] Figure 11 Photolithography is used to etch deep holes to expose the active region at the bottom of the underlying device as an epitaxial window;

[0072] Figure 12 By selective epitaxy and in-situ doping, the bottom LDD, lightly doped channel, top LDD and heavily doped source / drain of the lower-layer device are formed sequentially.

[0073] Figure 13 By selective epitaxy and in-situ doping, the bottom heavily doped source / drain and LDD, lightly doped channel, top LDD and heavily doped source / drain of the upper device are formed sequentially.

[0074] Figure 14 Interlayer isolation medium was deposited and planarization was achieved using CMP.

[0075] Figure 15 Photolithography is used to etch through-holes to expose the surface of the local interconnect sacrificial layer material, and isotropic etching is used to remove the sacrificial layer material.

[0076] Figure 16 Isotropically deposited metallic material fills to form local interconnects, and the metallic material on the interlayer isolation surface is etched away;

[0077] Figure 17 Photolithography etches vias to simultaneously expose the dummy gate surfaces of both the lower and upper layer devices, and removes the sacrificial layer material through isotropic etching.

[0078] Figure 18 HKMG material is filled sequentially, and HK and metal materials on the interlayer isolation surface are etched away.

[0079] Figure 19 Interlayer dielectric isolation is achieved by photolithography etching to form contact holes V0, filling the contact holes with metal Metal 0, and then performing CMP to achieve isolation of the device's conductive layer.

[0080] Figure 20 for Figures 1 to 19 Legend of the diagram. Detailed Implementation

[0081] The present invention will now be described in detail with reference to the accompanying drawings and specific examples.

[0082] In a specific embodiment of the present invention, the lower-level device is PMOS and the upper-level device is NMOS.

[0083] CMOS integration of bulk silicon vertical nanowire devices with a diameter of 10 nm can be achieved by following specific steps:

[0084] 1) A 50nm P+Si heavily doped active region (as the source / drain of PMOS) is formed on a bulk silicon substrate by in-situ doping epitaxial process.

[0085] 2) Using LPCVD 20nm Si3N4 as the etching hard mask material, the shape and size of the active region are defined by photolithography and anisotropic etching;

[0086] 3) Active regions are formed through anisotropic etching, and shallow trench isolation (STI) of SiO2 is formed according to the disclosed process, such as... Figure 1 As shown;

[0087] 4) A 10nm SiO2 and a 20nm Si3N4 layer are sequentially deposited using LPCVD to form the bottom gate isolation dielectric and the dummy gate sacrificial layer of the PMOS. The gate isolation dielectric layer defines the length of the extension region between the lower active region and the gate, and the dummy gate thickness defines the gate length of the underlying device. Figure 2 As shown;

[0088] 5) The dummy gate is patterned by photolithography etching to form gate lines, exposing the underlying gate isolation dielectric in areas not protected by the photoresist. Figure 3 As shown;

[0089] 6) 100nm SiO2 is deposited via LPCVD, planarized and thinned to 50nm using CMP. This thickness affects the top source / drain height of the PMOS transistor and the length of the extended region between it and the gate. Figure 4 As shown;

[0090] 7) A local interconnect sacrificial layer is formed by depositing 60nm Si3N4 via LPCVD, such as... Figure 5 As shown;

[0091] 8) The sacrificial layer material for local interconnects is patterned using photolithography etching. Its size and shape define the shared interconnects between the top active region of the lower-layer device and the bottom active region of the upper-layer device, such as... Figure 6 As shown;

[0092] 9) 100nm SiO2 was deposited via LPCVD, planarized and thinned to 50nm using CMP. This thickness affects the bottom source / drain height of the NMOS transistor and the length of the extended region between it and the gate. Figure 7 As shown;

[0093] 10) A 20nm Si3N4 dummy gate sacrificial layer is formed by LPCVD deposition to serve as the dummy gate for the upper-layer device. Its thickness is...

[0094] The degree defines the gate length of the upper-layer device, such as Figure 8 As shown;

[0095] 11) The dummy gate is patterned by photolithography etching to form gate lines, exposing the underlying layer in the unprotected areas of the photoresist.

[0096] Barrier isolation medium, such as Figure 9 As shown;

[0097] 12) 50nm SiO2 was deposited by LPCVD, planarized by CMP and thinned to 10nm to form the top gate of the NMOS.

[0098] Isolation is used to define the length of the extended region between the active region and the gate, such as... Figure 10 As shown;

[0099] 13) Expose the surface of the heavily doped active region at the bottom of the PMOS transistor by photolithography etching deep holes, such as... Figure 11 As shown;

[0100] 14) Through selective epitaxy and in-situ doping, the bottom LDD, channel, top LDD, and heavily doped source / drain of the PMOS are formed sequentially. The top interface should be located within the thickness range of the sacrificial layer material described in step 8), such as... Figure 12 As shown;

[0101] 15) Through selective epitaxy and in-situ doping, the heavily doped source / drain and LDD at the bottom of the NMOS transistor, the channel, and the heavily doped source / drain at the top are formed sequentially, such as... Figure 13 As shown;

[0102] 16) Deposit 100nm SiO2 via LPCVD, then planarize it using CMP. The remaining thickness should be greater than the source / drain epitaxial height described in step 15), such as... Figure 14 As shown;

[0103] 17) The surface of the local interconnect sacrificial layer Si3N4 is exposed by photolithography etching of vias, and the Si3N4 is removed by isotropic etching, such as... Figure 15 As shown;

[0104] 18) ALD deposition of metal W forms local interconnects, ensuring that the voids formed after the removal of the sacrificial layer in step 17) are completely filled, and anisotropic etching is used to remove the top metal of the interlayer dielectric, such as... Figure 16 As shown;

[0105] 19) The dummy gate Si3N4 surface of NMOS and PMOS is exposed by photolithography etching vias, and the Si3N4 is removed by isotropic etching, such as... Figure 17 As shown;

[0106] 20) ALD sequentially deposits gate oxide material HK and metal gate material MG to ensure that the voids formed after the dummy gate removal in step 19) are completely filled. Anisotropic etching is then used to remove the top dielectric metal and gate dielectric material from step 16), forming a common gate structure as shown. Figure 18 As shown;

[0107] 21) 100 nm SiO2 was deposited by PECVD and planarized by CMP;

[0108] 22) Contact holes at each end of the device gate, source, drain, and body are formed by photolithography and anisotropic etching;

[0109] 23) Metal 0 is filled into each contact hole by sputtering;

[0110] 24) By performing CMP on the metal 0, the conductive layers between devices can be separated, achieving device isolation. Figure 19 As shown;

[0111] 25) The device integration will be completed according to the publicly available back-end process.

[0112] The embodiments of this invention are not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this invention, or modify them into equivalent embodiments, without departing from the scope of the invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this invention, without departing from the scope of the invention, shall still fall within the protection scope of this invention.

Claims

1. A method for integrating vertical-channel complementary field-effect transistors, characterized in that, Includes the following steps: A. Epitaxially form a heavily doped lower active region on the substrate to serve as the bottom source / drain of the lower vertical channel device and form inter-device isolation; B. Deposit the dummy gate stack of the underlying device; C. Deposit a sacrificial layer material, and pattern the sacrificial layer by photolithography and anisotropic etching. Its size and shape define the common interconnect of the top active region of the lower device and the bottom active region of the upper device. D. Deposit a dummy gate stack for the upper-layer device; E. Etch deep holes to expose the active region surface described in step A; F. The lower device channel, the top active region of the lower device, the bottom active region of the upper device, the upper device channel, and the top source region of the upper device are formed sequentially through selective epitaxy. G. Form interlayer isolation, remove local interconnect sacrificial layers, and fill with interconnect metal; H. Remove the dummy gate sacrificial layer and fill with HK and MG materials; I. Forming metal contacts at each end of the device; J. Integrate vertical channel complementary field-effect transistors in the vertical direction using existing back-end processes.

2. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step A specifically includes: A1. Epitaxially grow a heavily doped semiconductor layer on a semiconductor substrate, wherein the doping is formed by in-situ epitaxy or by ion implantation; A2. Deposit a hard mask on the active region and pattern it using photolithography; the area of ​​the mask defines the area of ​​the active region. A3. The bottom active region of the underlying device is formed by etching with a hard mask pattern.

3. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step B specifically includes: B1. Deposit a dielectric layer as the gate isolation material for the underlying device to define the length of the extended region between the lower active region and the gate; B2. Deposit a sacrificial layer material as a dummy gate for the underlying device, the thickness of which defines the gate length of the underlying device; B3. The dummy gate layer is patterned using photolithography and anisotropic etching to form gate lines; B4. Deposit a dielectric layer as the gate isolation material for the underlying device and planarize it using CMP to define the active region thickness and the length of the extended region between it and the gate.

4. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step D specifically includes: D1. Deposit a dielectric layer as the gate isolation material for the upper device and planarize it using CMP to define the thickness of the lower active region and the length of the extended region between it and the gate; D2. Deposit a sacrificial layer material as a dummy gate for the upper-layer device, the thickness of which defines the gate length of the upper-layer device; D3. The dummy gate layer is patterned using photolithography and anisotropic etching to form gate lines; D4. Deposit a dielectric layer as the gate isolation material for the upper-layer device and planarize it using CMP to define the length of the extended region between the active region and the gate.

5. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step F specifically includes: F1. An extended region between the bottom active region and the gate of the lower-level device is formed by selective epitaxy; F2. Lightly doped channels for the underlying device are formed by selective epitaxy; F3. Selectively epitaxially form the extended region between the top active region and the gate of the lower device and the heavily doped source / drain, and its top interface should be within the thickness range of the sacrificial layer material described in step C; F4. Selective epitaxy is used to form heavily doped bottom source / drain regions and extended regions between the active region and the gate of the upper-layer device; F5. Lightly doped channels for upper-layer devices are formed through selective epitaxy; F6. Selective epitaxy is used to form the extended region between the top active region and the gate of the upper-layer device, as well as the heavily doped source / drain.

6. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step G specifically includes: G1. Deposit an interlayer medium and planarize using CMP; G2. The surface of the local interconnect sacrificial layer is exposed by photolithography etching; G3. Remove the sacrificial layer material by isotropic etching; G4. By isotropically growing locally interconnected metallic materials, it is ensured that the voids formed after the removal of the sacrificial layer in G2 are completely filled. G5. Remove the metal material grown on top of the medium in step G1 by anisotropic etching.

7. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, Step H specifically includes: H1. A dummy gate layer for both upper and lower devices is simultaneously exposed by defining a window through photolithography and anisotropic etching; H2. Removal of dummy gate material through isotropic etching; H3. By sequentially filling the gate oxide material HK and the metal gate material MG with isotropic conformal properties, the voids formed after the removal of the dummy gate in step H2 are completely filled. H4. Remove the metal and gate dielectric material grown on top of the dielectric in step H1 by anisotropic etching.

8. The integration method of the vertical channel complementary field-effect transistor as described in claim 1, characterized in that, Step I specifically includes: I1. Deposit a layer of medium for interlayer isolation and achieve planarization through CMP; I2. Contact holes at each end of the device are formed by photolithography and anisotropic etching; I3. Each contact hole is filled with Metal 0; I4. Perform CMP on the metal 0 to separate the conductive layers between devices and achieve device isolation.

9. The integration method of vertical channel complementary field-effect transistors as described in claim 1, characterized in that, The substrate is a bulk silicon substrate, an SOI substrate, a bulk germanium substrate, or a GOI substrate.

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