Power device and method of manufacturing the same

Abstract

This invention provides a power device and its fabrication method. The method includes the following steps: providing a substrate, defining an active region and a termination protection region within the substrate; forming a trench in the active region and a field limiting ring in the termination protection region; forming a field oxide layer covering the field limiting ring and an isolation layer located on the surface of the trench; forming a polysilicon layer filling the trench and extending from the trench surface to the surface of the field oxide layer; forming a photoresist layer and performing photolithography to expose the active region; hard baking the remaining photoresist layer; performing wet etching to partially remove the polysilicon layer located on the surface of the active region; etching back the remaining polysilicon layer on the surface of the active region to form a groove on the surface of the polysilicon layer within the trench; removing the remaining photoresist layer; forming an interlayer dielectric layer and performing an etching back process so that the formed interlayer dielectric layer fills the groove and covers the active region and the termination protection region. This invention helps to improve the breakdown characteristics of the device and reduce the device fabrication cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a power device and its fabrication method. Background Technology

[0002] Invented in 1979, the Insulated Gate Bipolar Transistor (IGBT) is a semiconductor power switching device primarily used for energy conversion, transmission, and control. Its applications include home appliances, electric vehicles, industrial control, high-speed rail, new energy sources, and smart grids. Over the past few decades, IGBT technology has undergone several generations of continuous improvement, playing an increasingly important role in high-voltage, high-current applications.

[0003] IGBT termination structures typically consist of an ion-implanted region, a field plate, and polysilicon covering the field plate. These structures assist in depletion and optimize edge curvature effects, and their termination structure is closely related to the device's breakdown voltage performance. However, after reflow and contact IMP drive-in, the thickness of the passivation layer and the field plate edge is significantly reduced. This weak point is affected by the electric field curvature effect caused by the sharp corners of the polysilicon, resulting in a concentrated electric field distribution. If the breakdown layer thickness is insufficient, it will be the first to break down under high voltage, severely impacting the device's bias voltage (BV) stability.

[0004] IGBTs in different application areas, especially in the high-voltage IGBT field, employ termination voltage-breaking structures such as field oxide (FOX) and localized oxide of silicon (LOCOS). The withstand voltage capability of the IGBT termination directly affects the overall withstand voltage and yield of the device. Improving the termination structure helps optimize the edge electric field distribution, reducing the peak electric field intensity under the same bias voltage, and improving and stabilizing the device's withstand voltage. This represents a development trend in IGBT device performance optimization.

[0005] Patent CN111755503A discloses a variable lateral doping termination structure and its fabrication method. This method is mainly used to address the issue of large leakage current or premature breakdown caused by electric field concentration in the spherical or cylindrical region at the edge of the main PN junction when the power device requires a termination structure to prevent reverse blocking. Typically, voltage-resistant structures such as field limiting rings and / or field plates are used. If a breakdown voltage close to that of a planar PN junction is required, a larger lateral area is needed because the field limiting rings themselves cannot be completely depleted. Furthermore, the oxide layer charge and large electric field formed during the process can easily increase leakage current or decrease breakdown voltage, thus requiring a reduction in ring spacing and an increase in the number of field limiting rings or their combination with field plates.

[0006] Compared to the aforementioned terminal structures, the variable lateral doping (VLD) structure offers higher lateral area utilization and can easily achieve breakdown voltages close to those of a planar PN junction. The VLD structure is characterized by the implantation and diffusion of ions with varying aperture sizes to form a controllable and laterally graded doped morphology. This doping can be completely depleted during reverse blocking, resulting in higher lateral area utilization compared to field-limiting ring structures. However, this technology requires more complex manufacturing processes, leading to increased device costs. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power device and its fabrication method, which solves the problems in the prior art such as the increased lateral area of ​​the device due to the withstand voltage structure, the increased leakage current or decreased breakdown voltage caused by the oxide layer charge and large electric field formed during the process, and / or the increased device cost due to the complexity of the process.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a power device, comprising the following steps:

[0009] A substrate is provided, wherein an active region and a terminal protection zone located outside the active region are defined on the substrate, a trench located within the substrate is formed in the active region, and a field limiting ring located within the substrate is formed in the terminal protection zone.

[0010] A field oxide layer covering the field limiting ring and an isolation layer located on the surface of the trench are formed;

[0011] A polysilicon layer is formed, which fills the trench to form a trench gate, and the polysilicon layer extends from the surface of the trench to the surface of the field oxide layer;

[0012] A photoresist layer is formed on the surface of the polysilicon layer, and the photoresist layer is subjected to photolithography to expose the active region;

[0013] The remaining photoresist layer is then hard-baked.

[0014] Wet etching is performed to partially remove the polysilicon layer located on the surface of the active region;

[0015] The residual polysilicon layer on the surface of the active region is etched back to form a groove on the surface of the polysilicon layer in the trench.

[0016] Remove residual photoresist layer;

[0017] An interlayer dielectric layer is formed and then etched back to fill the groove and cover the active region and the terminal protection region.

[0018] Optionally, the temperature during the hard-baking process is 110-130℃, and the hard-baking time is 1-2 minutes.

[0019] Optionally, the field limiting ring is a P-type ring.

[0020] Optionally, the terminal protection zone is located on one side of the active zone or surrounds the active zone.

[0021] Optionally, the wet etching process includes the step of etching the polycrystalline silicon layer using hydrofluoric acid and nitric acid.

[0022] Optionally, the isolation layer includes a silicon oxide layer, and the method for forming the isolation layer includes thermal oxidation.

[0023] Optionally, the interlayer dielectric layer includes a silicon nitride layer, and the method for forming the interlayer dielectric layer includes chemical vapor deposition.

[0024] Optionally, the method for fabricating the power device further includes the steps of forming a front metal layer on the surface of the interlayer dielectric layer and forming contact holes that electrically connect the field limiting ring and the active region to the front metal layer.

[0025] The present invention also provides a power device, which is prepared by the preparation method described in any of the above embodiments.

[0026] Optionally, the power device includes any one of IGBT devices, D-MOSFET devices, and SiC-MOSFET devices.

[0027] As described above, the power device and its fabrication method provided by this invention have the following beneficial effects: Through an improved process flow and by increasing polysilicon wet etching, the structure at weak points is optimized. Compared with conventional power device manufacturing processes, the electric field concentration effect at the polysilicon edge of the field plate is reduced, and the withstand voltage layer thickness is increased. This stabilizes the overall breakdown voltage of the device without increasing its lateral dimensions, thus helping to improve yield. Furthermore, the method is simple and helps reduce device fabrication costs. Attached Figure Description

[0028] Figure 1 The diagram shown is a flowchart of the fabrication method of the power device provided by the present invention.

[0029] Figure 2 Displayed as Figure 1 The schematic diagram shows the structure obtained after photolithography of the photoresist layer.

[0030] Figure 3 Displayed as Figure 1 The schematic diagram shows the structure obtained after wet etching of the polycrystalline silicon layer according to the preparation method.

[0031] Figure 4 Displayed as Figure 1 The schematic diagram shows the structure obtained after the polycrystalline silicon layer is etched back using the preparation method.

[0032] Figure 5 Displayed as Figure 1 The schematic diagram shows the structure obtained after forming an interlayer dielectric layer and then etching it back, according to the preparation method.

[0033] Component designation explanation

[0034] 11 Substrate

[0035] 12 trenches

[0036] 13 venues with limited capacity

[0037] 14 Field Oxide Layer

[0038] 15 Isolation Layers

[0039] 16 polycrystalline silicon layers

[0040] 17 Photoresist layer

[0041] 18 Grooves

[0042] 19 Interlayer dielectric layer Detailed Implementation

[0043] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. For ease of explanation, when detailing the embodiments of the present invention, the cross-sectional views showing the device structure are partially enlarged, not according to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual fabrication, three-dimensional spatial dimensions of length, width, and depth should be included.

[0044] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0045] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0046] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components related to the present invention and are not drawn according to the actual number, shape, and size of the components in the actual implementation. In the actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. To keep the illustrations as concise as possible, not all structures are shown in the figures.

[0047] Please see Figures 1 to 5 .

[0048] like Figure 1 As shown, the present invention provides a method for fabricating a power device, comprising the following steps:

[0049] S01: A substrate 11 is provided, on which an active region A and a termination protection zone B located outside the active region are defined. The termination protection zone B can be located on one side of the active region A or can be disposed around the periphery of the active region A. A trench 12 is formed within the active region A and a field limiting ring 13 is formed within the termination protection zone B. Specifically, the material of the substrate 11 depends on the specific type of power device to be fabricated. For example, when the power device is a silicon power device, the substrate 11 is a silicon substrate; when the power device is a silicon carbide power device, the substrate 11 is a silicon substrate. The substrate 11 is a silicon carbide substrate, but it can also be made of other materials, which are not strictly limited. The active region of the substrate is usually used to fabricate the core circuit of the device. In addition to the trench 12, it also has, for example, well regions (not shown) located on both sides of the trench 12 and source regions located in the well regions. The termination protection region is usually used to fabricate peripheral circuits, including the field limiting ring 13, to block the lateral breakdown voltage of the device and improve the device performance. The field limiting ring 13 can be single or multiple. When there are multiple field limiting rings 13, they are spaced apart. The field limiting ring 13 is usually formed by ion implantation process.

[0050] S02: Form a field oxide layer 14 covering the field limiting ring 13 and an isolation layer 15 located on the surface of the trench 12. The upper surface of the field oxide layer 14 is generally higher than the upper surface of the isolation layer 15. The field oxide layer 14 is generally a silicon oxide layer and can be formed by thermal oxidation or chemical vapor deposition. The isolation layer 15 includes, but is not limited to, a silicon oxide layer, preferably but not limited to being formed by thermal oxidation. The thickness of the isolation layer 15 is preferably 100 angstroms to 200 angstroms. The isolation layer 15 also extends from the surface of the trench 12 to the entire surface of the active region and is adjacent to the field oxide layer 14.

[0051] S03: A polysilicon layer 16 is formed using a process including but not limited to vapor deposition. The polysilicon layer 16 fills the trench 12 to form the trench 12 gate, and the polysilicon layer 16 extends from the surface of the trench 12 to the surface of the field oxide layer 14. Since the height of the field oxide layer 14 is higher than the height of the isolation layer 15, after the polysilicon layer 16 is formed by conformal deposition, the upper surface of the polysilicon layer 16 on the field oxide layer 14 is higher than the upper surface of the polysilicon layer 16 on the active region, thus forming a height difference between the active region and the terminal protection zone. Therefore, the polysilicon layer 16 connecting the terminal protection zone and the active region forms a slope (see reference). Figure 2 (as shown);

[0052] S04: A photoresist layer 17 is formed on the surface of the polysilicon layer 16 using processes including but not limited to spin coating. The photoresist layer 17 is then subjected to photolithography to expose the active region, resulting in the structure shown below. Figure 2 As shown;

[0053] S05: Hard bake the remaining photoresist layer 17; by hard baking, not only can the solvent in the photoresist be completely evaporated, but the photoresist can also be hardened, enhancing the adhesion of the photoresist layer 17 to other structural layers, and preventing the photoresist layer 17 from peeling or even detaching in the subsequent wet etching process.

[0054] S06: Perform wet etching to partially remove the polysilicon layer 16 located on the surface of the active region. After wet etching, a portion of the polysilicon layer 16 remains on the surface of the active region, while the polysilicon layer 16 on the field oxide layer 14 becomes the terminal field plate. Due to the isotropic etching rate characteristic of wet etching, the etching extends a certain length from the edge of the terminal field plate towards the lower end of the photoresist layer 17, thus removing the sharp corners at the edge of the polysilicon field plate and leaving a relatively gentle slope. The structure obtained after this step is as follows: Figure 3 As shown;

[0055] S07: The remaining polysilicon layer 16 on the surface of the active region is etched back to form a groove 18 on the surface of the polysilicon layer 16 within the trench 12. During this process, the polysilicon layers 16 on other surfaces of the active region are also removed. The structure obtained after this step is as follows: Figure 4 As shown;

[0056] S08: Remove the residual photoresist layer 17 using processes including but not limited to stripping.

[0057] S09: An interlayer dielectric layer 19 (ILD) is formed using a process including but not limited to vapor deposition, and then etched back to ensure that the formed interlayer dielectric layer 19 fills the groove 18 and covers the active region and the terminal protection region, resulting in the desired effect. Figure 5 The structure shown; due to the initial wet etching and the re-etching of the polysilicon, the edge of the polysilicon in the field plate changes from a traditional right angle to a rounded corner or a relatively gentle slope, and the groove 18 is formed. Therefore, a thicker interlayer dielectric material is retained at the upper edge of the polysilicon in the field plate (see reference). Figure 5 (at the coil marking), which can improve the breakdown performance of the device.

[0058] This invention, through an improved process flow and by adding polysilicon wet etching, optimizes the structure at weak points. Compared with conventional power device manufacturing processes, the electric field concentration effect at the polysilicon edge of the field plate is reduced, and the withstand voltage layer thickness is increased. This stabilizes the overall breakdown voltage of the device without increasing its lateral dimensions, thus improving yield. Furthermore, the method is simple and helps reduce device fabrication costs.

[0059] In a preferred example, the temperature during the hard-bake process is 110-130°C, and the hard-bake time is 1-2 minutes.

[0060] In one example, the field limiting ring 13 is a P-type ring. In this case, the aforementioned well region is typically a P-type well and the source region is an N-type active region.

[0061] In a preferred example, the wet etching process includes etching the polysilicon layer 16 with hydrofluoric acid and nitric acid, followed by cleaning the etched structure with deionized water.

[0062] As an example, the interlayer dielectric layer 19 includes, but is not limited to, a silicon nitride layer, and may also be a silicon oxynitride layer or other high-k dielectric material layer.

[0063] Depending on the device type, the fabrication method of the power device further includes the steps of forming a front metal layer on the surface of the interlayer dielectric layer 19 and forming contact holes that electrically connect the field limiting ring 13 and the active region to the front metal layer. A back metal layer can also be fabricated on the back side of the substrate 11. The fabrication method of this invention is not only applicable to the fabrication of silicon insulated gate bipolar transistors (IGBTs) and silicon carbide insulated gate bipolar transistors (SiC-IGBTs), but can also be used to fabricate D-MOSFET (double-diffused MOSFET) devices and silicon carbide MOSFET (SiC-MOSFET) devices.

[0064] This invention also provides a power device, which is fabricated using the methods described in any of the above-mentioned schemes. Therefore, the foregoing content can be referenced hereafter, and will not be repeated for the sake of brevity. The power device includes, but is not limited to, any one of IGBT devices, D-MOSFET devices, and SiC-MOSFET devices. Because it is fabricated using the aforementioned methods, the power device provided by this invention has advantages such as superior breakdown performance.

[0065] In summary, the present invention provides a power device and a method for fabricating the same. The fabrication method includes the following steps: providing a substrate, wherein an active region and a termination protection zone are defined on the substrate; forming a trench within the active region and a field limiting ring within the termination protection zone; forming a field oxide layer covering the field limiting ring and an isolation layer on the surface of the trench; forming a polysilicon layer that fills the trench to form a trench gate, and the polysilicon layer extending from the surface of the trench to the surface of the field oxide layer; forming a photoresist layer on the surface of the polysilicon layer; performing photolithography on the photoresist layer to expose the active region; performing hard baking on the remaining photoresist layer; performing wet etching to partially remove the polysilicon layer on the surface of the active region; etching back the remaining polysilicon layer on the surface of the active region to form a groove on the surface of the polysilicon layer in the trench; removing the remaining photoresist layer; forming an interlayer dielectric layer and performing an etching back process so that the formed interlayer dielectric layer fills the groove and covers the active region and the termination protection zone. This invention, through an improved process flow and by adding polysilicon wet etching, optimizes the structure at weak points. Compared to conventional power device manufacturing processes, the electric field concentration effect at the polysilicon edge of the field plate is reduced, and the withstand voltage layer thickness is increased. This stabilizes the overall breakdown voltage of the device without increasing its lateral dimensions, thus improving yield. Furthermore, the method is simple and helps reduce device fabrication costs. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a power device, characterized in that, Including the following steps: A substrate is provided, wherein an active region and a terminal protection zone located outside the active region are defined on the substrate, a trench located within the substrate is formed in the active region, and a field limiting ring located within the substrate is formed in the terminal protection zone. A field oxide layer covering the field limiting ring and an isolation layer located on the surface of the trench are formed; A polysilicon layer is formed, which fills the trench to form a trench gate, and the polysilicon layer extends from the surface of the trench to the surface of the field oxide layer; A photoresist layer is formed on the surface of the polysilicon layer, and the photoresist layer is subjected to photolithography to expose the active region; The remaining photoresist layer is then hard-baked. Wet etching is performed to partially remove the polysilicon layer located on the surface of the active region. After wet etching, a portion of the polysilicon layer still covers the surface of the active region. The polysilicon layer located on the field oxide layer becomes the terminal field plate, and the sharp corners at the polysilicon edge of the terminal field plate are etched away. The residual polysilicon layer on the surface of the active region is etched back to form a groove on the surface of the polysilicon layer in the trench, and the polysilicon layer located on the surface of the active region and outside the trench is removed. Remove residual photoresist layer; An interlayer dielectric layer is formed and then etched back to fill the groove and cover the active region and the terminal protection region.

2. The method for fabricating the power device according to claim 1, characterized in that, The temperature during the hard baking process is 110-130℃, and the hard baking time is 1-2 minutes.

3. The method for fabricating a power device according to claim 1, characterized in that, The field limiting ring is a P-type ring.

4. The method for fabricating a power device according to claim 1, characterized in that, The terminal protection zone is located on one side of the active zone or around the periphery of the active zone.

5. The method for fabricating a power device according to claim 1, characterized in that, The wet etching process includes the steps of etching the polycrystalline silicon layer using hydrofluoric acid and nitric acid.

6. The method for fabricating a power device according to claim 1, characterized in that, The isolation layer includes a silicon oxide layer, and the method for forming the isolation layer includes thermal oxidation.

7. The method for fabricating a power device according to claim 1, characterized in that, The interlayer dielectric layer includes a silicon nitride layer, and the method for forming the interlayer dielectric layer includes chemical vapor deposition.

8. The method for fabricating a power device according to claim 1, characterized in that, The method for fabricating the power device further includes the steps of forming a front metal layer on the surface of the interlayer dielectric layer and forming contact holes that electrically connect the field limiting ring and the active region to the front metal layer.

9. A power device, characterized in that, The power device is prepared using the preparation method described in any one of claims 1-8.

10. The power device according to claim 9, characterized in that, The power device includes any one of IGBT devices, D-MOSFET devices, and SiC-MOSFET devices.

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