High electron mobility transistor and its fabrication method

Abstract

This invention discloses a high electron mobility transistor and its fabrication method. The high electron mobility transistor includes a substrate, a channel layer, a barrier layer, and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, wherein the metal layer includes a metal material and a first additive doped in the metal material. The weight percentage concentration of the first additive in the metal layer is between 0% and 2%.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high electron mobility transistor (HEMT) structure and its fabrication method. Background Technology

[0002] High electron mobility transistors (HEMTs) are an emerging type of field-effect transistor. They primarily consist of a heterostructure composed of multiple layers of different semiconductor materials. By selecting appropriate semiconductor materials, a two-dimensional electron gas (2DEG) layer can be formed near the heterojunction to serve as the current channel region, resulting in high switching speeds and response frequencies. This makes them particularly suitable for applications in power converters, low-noise amplifiers, radio frequency (RF) and millimeter-wave (MMW) technologies. To meet the demands of high-voltage, high-frequency, and lower-power applications, further reducing the contact resistance of HEMTs to improve output power is a key research area in this field. Summary of the Invention

[0003] To achieve the above objectives, the present invention provides a high electron mobility transistor and a method for manufacturing the same, wherein at least one additive is doped into the metal layer forming the contact structure, wherein the additive can react with at least a portion of the substrate to form a metal compound layer, thereby avoiding the reaction between the substrate and the metal layer material that would cause an increase in resistance.

[0004] A high electron mobility transistor according to an embodiment of the present invention includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, a passivation layer disposed on the barrier layer, and a contact structure disposed on the passivation layer and extending through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a substrate and a metal layer located on the substrate. The metal layer includes a metallic material and a first additive doped in the metallic material. The weight percentage concentration of the first additive in the metal layer is between 0% and 2%.

[0005] A method for fabricating a high electron mobility transistor according to an embodiment of the present invention includes the following steps: First, a channel layer is formed on a substrate; then, a barrier layer is formed on the channel layer; next, a passivation layer is formed on the barrier layer; and then, an opening is formed that penetrates the passivation layer and the barrier layer, exposing a portion of the channel layer. Next, a liner is formed along the bottom surface and sidewalls of the opening; and then, a metal layer is formed on the liner, wherein the metal layer comprises a metallic material and a first additive doped in the metallic material, the first additive having a weight percentage concentration between 0% and 2% in the metal layer. Attached Figure Description

[0006] Figures 1 to 4 This is a cross-sectional schematic diagram of a method for fabricating a high electron mobility transistor according to an embodiment of the present invention;

[0007] Figures 5 to 8 This is a cross-sectional schematic diagram of a method for fabricating a high electron mobility transistor according to another embodiment of the present invention;

[0008] Figures 9 to 12 This is a cross-sectional schematic diagram of a method for fabricating a high electron mobility transistor according to another embodiment of the present invention.

[0009] Explanation of main component symbols

[0010] 10 base

[0011] 12 Buffer Layer

[0012] 14. Channel layer

[0013] 16 Barrier Layer

[0014] 18 gate structure

[0015] 20 passivation layers

[0016] 21 Passivation layer

[0017] 22 Passivation layer

[0018] 32 Lining

[0019] 34 Metal Layer

[0020] 36 cap layer

[0021] 42 Contact Structure

[0022] 43 Contact Structure

[0023] 48 Contact Structure

[0024] 18a Semiconductor Gate Layer

[0025] 18b metal gate layer

[0026] 32' Metal compound layer

[0027] 34a Metallic Materials

[0028] 34b First Additive

[0029] 34c Second Additive

[0030] OP1 opening

[0031] OP2 opening

[0032] OP3 opening

[0033] OP4 opening

[0034] OP5 opening

[0035] OP6 opening

[0036] OP7 Opening

[0037] P1 Tempering process Detailed Implementation

[0038] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below, along with the accompanying drawings, to explain in detail the composition and desired effects of the invention. It should be understood that the following embodiments can be modified by substituting, recombining, or mixing features from several different embodiments without departing from the spirit of this disclosure to achieve other embodiments.

[0039] The high electron mobility transistor of the present invention can be a depletion mode / normally-on or enhancement mode / normally-off high electron mobility transistor, and can be applied in the fields of power converters, low noise amplifiers, radio frequency (RF) or millimeter wave (MMW) technologies.

[0040] The types and shapes of the gate, source, and drain structures of the high electron mobility transistors described in the embodiments of this invention are merely examples for the purpose of illustration and explanation, and are not intended to limit the invention. The following description uses a high electron mobility transistor including a metal-semiconductor gate structure as an example; it should be understood that in other embodiments, the high electron mobility transistor may include a metal gate structure.

[0041] Please refer to Figures 1 to 4The diagram shown is a cross-sectional schematic of a method for fabricating a high electron mobility transistor according to an embodiment of the present invention. Figure 1 As shown, a substrate 10 is first provided, on which a stacked structure is disposed. The stacked structure may, from bottom to top, include a buffer layer 12, a channel layer 14, a barrier layer 16, a gate structure 18, and a passivation layer 20. In this embodiment, the gate structure 18 is a metal-semiconductor gate structure, including a semiconductor gate layer 18a and a metal gate layer 18b. According to an embodiment of the present invention, the method for fabricating the stacked structure may include performing a deposition process to sequentially form a buffer layer 12, a channel layer 14, a barrier layer 16, a semiconductor gate layer 18a, and a metal gate layer 18b on the substrate 10, then etching away excess portions of the semiconductor gate layer 18a and the metal gate layer 18b to obtain the gate structure 18, and then performing another deposition process to form a passivation layer 20 covering the barrier layer 16 and the gate structure 18. Applicable deposition processes may include, but are not limited to, molecular beam epitaxy, hydride vapor phase epitaxy, organometallic vapor phase deposition, chemical vapor phase deposition, atomic layer deposition, physical vapor phase deposition, molecular beam deposition, and plasma-enhanced chemical vapor deposition.

[0042] The substrate 10 may include a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride substrate, an aluminum nitride substrate, or a substrate formed of other suitable materials. The buffer layer 12, the channel layer 14, and the barrier layer 16 may each have a single-layer or multi-layer structure, and may each include a III-V group semiconductor compound material, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), graded aluminum gallium nitride (Graded AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), doped gallium nitride (GaN), aluminum nitride (AlN), or combinations thereof, but are not limited thereto. According to one embodiment of the present invention, the material of the buffer layer 12 may include aluminum gallium nitride (AlGaN), the material of the channel layer 14 may include gallium nitride (GaN), and the material of the barrier layer 16 may include aluminum gallium nitride (AlGaN). A two-dimensional electron gas layer may be included near the junction of the barrier layer 16 and the channel layer 14, which can be used as a planar current channel for a high electron mobility transistor.

[0043] The gate structure 18 is used to control the conduction and cutoff of the two-dimensional electron gas layer. The semiconductor gate layer 18a may include, but is not limited to, N-type doped Group III-V semiconductor materials, N-type doped Group II-VI semiconductor materials, undoped Group III-V semiconductor materials, undoped Group II-VI semiconductor materials, P-type doped Group III-V semiconductor materials, or P-type doped Group II-VI semiconductor materials. According to one embodiment of the present invention, the semiconductor gate layer 18a includes p-type gallium nitride (p-GaN) doped with magnesium (Mg), iron (Fe), or other suitable materials. The metal gate layer 18b may include metals such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), or compounds (e.g., nitrides, silicides, or oxides), composite layers, or alloys of the aforementioned metals, but is not limited to these. According to one embodiment of the present invention, the metal gate layer 18b may include titanium nitride (TiN). A Schottky contact can be formed between the semiconductor gate layer 18a and the metal gate layer 18b, enabling the gate structure 18 to also have a rectification function. The passivation layer 20 may include insulating materials such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), zirconium oxide (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), dinobinium oxide (Lu2O3), lanthanum dinobinium oxide (LaLuO3), high-k dielectric materials, polyimide (PI), benzocyclobutene (BCB), and polybenzoxazole (PBO), but is not limited thereto. According to one embodiment of the present invention, the passivation layer 20 may include silicon nitride (Si3N4).

[0044] like Figure 2As shown, the stacked structure can then be etched to form openings OP1 on both sides of the gate structure 18, penetrating the passivation layer 20 and barrier layer 16 and exposing a portion of the channel layer 14, and opening OP2 penetrating the passivation layer 20 directly above the gate structure 18 and exposing a portion of the metal gate layer 18b. Next, a suitable deposition or coating process can be used to sequentially form a liner 32, a metal layer 34, and a capping layer 36 on the passivation layer 20. The liner 32 conformally covers the surface of the passivation layer 20 and the sidewalls and bottom surfaces of openings OP1 and OP2, and the portion of the liner 32 within opening OP1 can directly contact the barrier layer 16 and the channel layer 14. The portion of the liner 32 within opening OP2 can directly contact the metal gate layer 18b of the gate structure 18. The substrate 32, metal layer 34, and capping layer 36 may each comprise a metallic material, such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers, or alloys of the above metals, but are not limited thereto. It is noteworthy that the substrate 32 and metal layer 34 must be selected from materials capable of forming an ohmic contact with the channel layer 14. For example, when the channel layer 14 comprises gallium nitride (GaN), the substrate 32 preferably comprises primarily titanium (Ti), and the metal layer 34 preferably comprises primarily aluminum (Al). Furthermore, the metal layer 34 may preferably include at least one additive to further improve the quality of the ohmic contact and enhance the conductivity and reliability (e.g., anti-electromigration properties) of the metal layer 34. According to one embodiment of the present invention, the metal layer 34 may comprise aluminum-silicon copper (AlSiCu), aluminum-germanium copper (AlGeCu), or aluminum-carbon copper (AlCCu). Figure 2As shown, the metal material 34a of the main body of the metal layer 34 is aluminum (Al). The material of the first additive 34b doped in the metal material 34a may include at least one of silicon (Si), germanium (Ge), and carbon (C). The material of the second additive 34c doped in the metal material 34a may include copper (Cu). The metal layer 34 can be fabricated by a deposition process (e.g., electron beam evaporation or sputtering), wherein a target material of the metal material 34a with an appropriate concentration of doping (e.g., an aluminum target material including appropriate concentrations of silicon, germanium, carbon, and / or copper) can be used to fabricate the metal layer 34, or other suitable methods can be used to dope the metal material 34a with additives. The weight percentage concentration of the first additive 34b (material may be silicon, germanium, or carbon) in the metal layer 34 may be between 0% and 2%, and the weight percentage concentration of the second additive 34c (material may be copper) in the metal layer 34 may be between 0% and 1%. The capping layer 36 can be used to protect the metal layer 34, for example, by preventing the material of the metal layer 34 from being oxidized or reacting with the materials of other layers. According to one embodiment of the invention, the capping layer 36 may include titanium nitride (TiN). The thicknesses of the liner 32, the metal layer 34, and the capping layer 36 can be adjusted as needed. According to one embodiment of the invention, the thickness of the liner 32 may be between 10 angstroms and 200 angstroms, the thickness of the metal layer 34 may be between 1000 angstroms and 3000 angstroms, and the thickness of the capping layer 36 may be between 250 angstroms and 350 angstroms, but is not limited thereto.

[0045] like Figure 3As shown, a tempering process P1 can then be performed to promote the material reaction between the substrate 32 and the channel layer 14, thereby forming an ohmic contact between the metal layer 34 and the channel layer 14 below the opening OP1, and transforming the substrate 32 into a metal compound layer 32'. According to one embodiment of the present invention, the temperature of the tempering process P1 can be between 450 degrees Celsius and 900 degrees Celsius, and the time can be between 5 minutes and 60 minutes, but is not limited thereto. According to one embodiment of the present invention, when the channel layer 14 includes gallium nitride (GaN), selecting titanium (Ti) as the main material of the substrate 32, and using aluminum (Al) doped with silicon (Si), germanium (Ge) and / or carbon (C) as the main material of the metal layer 34, better ohmic contact can be obtained, partly because the titanium in the substrate 32 will bind nitrogen in the channel layer 14 during the tempering process P1 to form titanium nitride (TiN), while creating a large number of nitrogen vacancies in the channel layer 14. The low work function (3.7 eV) of titanium nitride, combined with the effect of nitrogen vacancies in gallium nitride (GaN) resulting in n-type heavy doping, is beneficial for forming low-resistance ohmic contacts. On the other hand, during the tempering process P1, dopants such as silicon (Si), germanium (Ge), and / or carbon (C) diffuse to the interface between metal layer 34 and substrate 32 and react with the titanium (Ti) in substrate 32, thereby transforming substrate 32 into a metal compound layer 32' comprising titanium silicide (TiSi), titanium germanide (TiGe), and / or titanium carbide (TiC). Titanium silicide (TiSi), titanium germanide (TiGe), and titanium carbide (TiC) are all low work function materials, which is beneficial for forming ohmic contacts with gallium nitride channel layer 14. The composition of the metal compound layer 32' includes the material of the liner 32 and the first additive 34b, which may include at least one of titanium silicide (TiSi), titanium germanide (TiGe), and titanium carbide (TiC) (depending on the materials of the liner 32 and the first additive 34b). Notably, the portion of the metal compound layer 32' located at the bottom of the opening OP1 may also include titanium nitride (TiN) formed by the reaction of the liner 32 with the channel layer 14.

[0046] like Figure 4 As shown, excess portions of the capping layer 36, metal layer 34, and metal compound layer 32' can then be etched away to obtain contact structure 42 and contact structure 43. Contact structure 42 (source / drain contacts) is located on both sides of the gate structure 18, passing through the passivation layer 20 and barrier layer 16 to directly contact the channel layer 14. Contact structure 43 (gate contact) is located directly above the gate structure 18 and directly contacts the metal gate layer 18b of the gate structure 18.

[0047] In a preferred embodiment of the present invention, aluminum-silicon copper (AlSiCu), aluminum-germanium copper (AlGeCu), or aluminum-carbon copper (AlCCu) is used as the metal layer 34. This reduces the formation of titanium aluminide (TiAl3) due to the reaction between titanium (Ti) in the substrate 32 and aluminum (Al) in the metal layer 34, thus effectively improving the high resistance problem caused by titanium aluminide (TiAl3). Furthermore, the metal compound layer 32' can also serve as a diffusion barrier layer, reducing gallium vacancy defects caused by the diffusion of gallium (Ga) from the channel layer 14 into the metal layer 34. In summary, the present invention effectively reduces the resistance of contact structures 42 and 43 and provides better contact quality.

[0048] The following description will focus on different embodiments of the present invention. For simplicity, the description will primarily focus on the differences between the embodiments, without repeating the similarities. Identical elements in each embodiment are designated with the same reference numerals to facilitate comparison between embodiments.

[0049] Please refer to Figures 5 to 8 The diagram shown is a cross-sectional schematic of a method for fabricating a high electron mobility transistor according to another embodiment of the present invention. This embodiment is similar to... Figures 1 to 4 The main difference in the illustrated embodiment is that, in this embodiment, the source / drain contact is formed first, followed by the gate contact. Specifically, as follows... Figure 5 As shown, openings OP1 can be etched only in the stacked structure on both sides of the gate structure 18, without forming any openings in the passivation layer 20 on the gate structure 18. Then, a liner 32, a metal layer 34, and a capping layer 36 are formed on the stacked structure to fill the openings OP1. Then, as... Figure 6 As shown, a tempering process P1 is performed to promote the material reaction between the liner 32 and the channel layer 14, thereby forming an ohmic contact between the metal layer 34 and the channel layer 14 below the opening OP1, and transforming the liner 32 into a metal compound layer 32'. Then, as... Figure 7 As shown, etching removes excess portions of the capping layer 36, metal layer 34, and metal compound layer 32', obtaining contact structures 42 (source / drain contacts) located on both sides of the gate structure 18 and in direct contact with the channel layer 14. Then, as... Figure 8As shown, another passivation layer 22 is formed to cover the passivation layer 20 and the contact structure 42. An opening OP3 is then etched into the passivation layer 22 directly above the contact structure 42, and an opening OP4 is etched into the passivation layer 22 and the passivation layer 20 directly above the gate structure 18. A metal layer (not shown) is then formed on the passivation layer 22 and patterned to obtain contact structures 44 and 46 (gate contacts) that directly contact the contact structure 42 and the gate structure 18, respectively. The material of the passivation layer 22 can be referenced from the materials suitable for the passivation layer 20, and will not be repeated here. According to one embodiment of the present invention, the passivation layer 22 and the passivation layer 20 may include the same material, such as silicon nitride (Si3N4). Contact structures 44 and 46 may include metals such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds, composite layers or alloys of the above metals, but are not limited thereto.

[0050] Please refer to Figures 9 to 12 The diagram shown is a cross-sectional schematic of a method for fabricating a high electron mobility transistor according to another embodiment of the present invention. This embodiment is similar to... Figures 1 to 4 The main difference in the illustrated embodiment is that, in this embodiment, the gate contact is formed first, followed by the source / drain contact. Specifically, as follows... Figure 9 As shown, after forming the passivation layer 20, an opening OP5 can be etched only in the passivation layer 20 directly above the gate structure 18. Then, a metal layer (not shown) is formed on the passivation layer 20 and patterned to obtain a contact structure 46 (gate contact) that directly contacts the gate structure 18. Then, as... Figure 10 As shown, another passivation layer 21 is formed to cover the passivation layer 20 and the contact structure 46. Then, an opening OP6 is etched on both sides of the gate structure 18, extending through the passivation layer 21, passivation layer 20, and barrier layer 16 until a portion of the channel layer 14 is exposed, and an opening OP7 extends through the passivation layer 21 directly above the contact structure 46 to expose a portion of the contact structure 46. Then, using a suitable deposition or coating process, a liner 32, a metal layer 34, and a capping layer 36 are formed on the passivation layer 21, filling the openings OP6 and OP7. The material of the passivation layer 21 can be referenced to the materials suitable for the passivation layer 20, and will not be repeated here. According to one embodiment of the present invention, the passivation layer 21 and the passivation layer 20 may comprise the same material, such as silicon nitride (Si3N4). Next, as... Figure 11 As shown, a tempering process P1 is performed to promote the material reaction between the liner 32 and the channel layer 14, thereby forming an ohmic contact between the metal layer 34 and the channel layer 14 below the opening OP6, and transforming the liner 32 into a metal compound layer 32'. Further details are as follows... Figure 12As shown, etching removes excess portions of the capping layer 36, metal layer 34, and metal compound layer 32', resulting in contact structures 42 (source / drain contacts) located on both sides of the gate structure 18 and in direct contact with the channel layer 14, and contact structure 48 located directly above and in direct contact with the contact structure 46.

[0051] In summary, the high electron mobility transistor of the present invention uses a substrate in conjunction with a metal layer comprising at least one additive, which enables the achievement of ohmic contacts with low resistance after a tempering process. The metal compound layer obtained by the reaction of the substrate material and the additive material can also serve as a diffusion barrier layer, reducing gallium (Ga) vacancy defects caused by the diffusion of gallium (Ga) from the channel layer into the metal layer.

[0052] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A high electron mobility transistor, comprising: The channel layer is set on the substrate; A barrier layer is disposed on the channel layer; A passivation layer is disposed on the barrier layer; as well as A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer, wherein the contact structure includes: Metal compound layer; as well as A metal layer is located on the metal compound layer, wherein the metal layer comprises a metal material and a first additive doped in the metal material, wherein the metal material comprises aluminum (Al), the first additive comprises at least one of silicon (Si), germanium (Ge) and carbon (C) and the weight percentage concentration of the first additive in the metal layer is between 0% and 2%, and the metal compound layer comprises a metal compound of titanium (Ti) and the first additive.

2. The high electron mobility transistor of claim 1, wherein the metal compound layer is in direct contact with the channel layer, the barrier layer and the passivation layer.

3. The high electron mobility transistor of claim 1, wherein the metal layer further comprises a second additive doped in the metal material, wherein the weight percentage concentration of the second additive in the metal layer is between 0% and 1%.

4. The high electron mobility transistor of claim 3, wherein the second additive comprises copper (Cu).

5. The high electron mobility transistor of claim 1, wherein the metal layer is separated from the passivation layer, the barrier layer and the channel layer by the metal compound layer and do not directly contact each other.

6. The high electron mobility transistor of claim 1, wherein the metal compound layer further comprises titanium nitride (TiN).

7. The high electron mobility transistor of claim 1, wherein the channel layer comprises gallium nitride (GaN), the barrier layer comprises aluminum gallium nitride (AlGaN), and the passivation layer comprises silicon nitride (SiN).

8. A method for fabricating a high electron mobility transistor, comprising: A channel layer is formed on the substrate; A barrier layer is formed on the channel layer; A passivation layer is formed on this barrier layer; An opening is formed that penetrates the passivation layer and the barrier layer and exposes part of the channel layer; A liner is formed along the bottom surface and sidewalls of the opening, wherein the liner comprises titanium (Ti); A metal layer is formed on the substrate, wherein the metal layer comprises a metallic material and a first additive doped in the metallic material, wherein the metallic material comprises aluminum (Al), and the first additive comprises at least one of silicon (Si), germanium (Ge), and carbon (C), and the weight percentage concentration of the first additive in the metal layer is between 0% and 2%; and A tempering process is performed, wherein the liner and the first additive react in the tempering process to form a metal compound layer.

9. The method for fabricating a high electron mobility transistor as described in claim 8, wherein the metal compound layer further comprises titanium nitride (TiN).

10. The method for fabricating a high electron mobility transistor as described in claim 8, wherein the temperature of the tempering process is between 450 degrees Celsius and 900 degrees Celsius.

11. The method for fabricating a high electron mobility transistor as claimed in claim 8, wherein the metal layer further comprises a second additive doped in the metal material, wherein the weight percentage concentration of the second additive in the metal layer is between 0% and 1%.

12. The method for fabricating a high electron mobility transistor as claimed in claim 11, wherein the second additive comprises copper (Cu).

13. The method for fabricating a high electron mobility transistor as described in claim 8, wherein the substrate directly contacts the channel layer, the barrier layer, and the passivation layer.

14. The method for fabricating a high electron mobility transistor as claimed in claim 8, wherein the channel layer comprises gallium nitride (GaN), the barrier layer comprises aluminum gallium nitride (AlGaN), and the passivation layer comprises silicon nitride (SiN).

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