Light emitting diode epitaxial wafer and preparation method thereof, and light emitting diode

Abstract

The application discloses a light emitting diode epitaxial wafer and a preparation method thereof. The light emitting diode epitaxial wafer comprises a substrate, a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a first insertion layer, a multi-quantum well layer, a second insertion layer, an electron blocking layer and a P-type semiconductor layer which are sequentially stacked on the substrate; the first insertion layer is a Sc-doped GaN layer, and the second insertion layer is a Lu-doped GaN layer. The application can reduce the piezoelectric polarization of the multi-quantum well layer, balance the electrons and holes in the multi-quantum well layer, and improve the light emitting efficiency of the light emitting diode.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a light-emitting diode epitaxial wafer and its fabrication method, and a light-emitting diode. Background Technology

[0002] Currently, GaN-based light-emitting diodes are widely used in backlights, lighting, landscape lighting, and other fields, attracting increasing attention.

[0003] In light-emitting diodes (LEDs), the multiple quantum well layer, as the active region, is a very important structure for epitaxial growth. The multiple quantum well layer is generally a periodic structure composed of repeated stacks of InGaN quantum well layers and GaN quantum barrier layers. However, due to the large size of In atoms, the multiple quantum wells are subjected to compressive stress, resulting in severe piezoelectric polarization. This leads to the tilting of the multiple quantum well band, causing severe spatial separation when electrons and holes pass through the quantum well region, which reduces the luminous efficiency of the LED. Furthermore, due to the large size of In atoms, the number of In atoms that can be effectively incorporated into the GaN lattice is limited, which also affects the luminous efficiency of the LED.

[0004] Furthermore, due to the difficulty in activating Mg, the hole concentration is low, and the hole mobility itself is slower than that of electrons. Therefore, in multi-quantum-well layers, the imbalance between electrons and holes is also one of the key reasons limiting the improvement of the luminous efficiency of light-emitting diodes. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer that reduces piezoelectric polarization of the multi-quantum-well layer, balances electrons and holes in the multi-quantum-well layer, and improves the luminous efficiency of the light-emitting diode epitaxial wafer.

[0006] The technical problem to be solved by the present invention is to provide a method for preparing an epitaxial wafer of a light-emitting diode, which is simple in process and produces an epitaxial wafer of a light-emitting diode with high luminous efficiency.

[0007] To achieve the above-mentioned technical effects, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0008] The first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.

[0009] As an improvement to the above technical solution, the thickness of the first insertion layer is 20-200 nm; the thickness of the second insertion layer is 20-200 nm.

[0010] As an improvement to the above technical solution, the thickness ratio of the first insertion layer to the second insertion layer is 1:(1-2).

[0011] As an improvement to the above technical solution, the doping concentration of Sc in the first insertion layer is 1×10⁻⁶. 3 -1×10 6 cm -3 The doping concentration of Lu in the second insertion layer is 1×10⁻⁶. 3 -1×10 6 cm -3 .

[0012] As an improvement to the above technical solution, the doping concentration of Sc in the first insertion layer is 5×10⁻⁶. 4 -5×10 5 cm -3 The Si doping concentration in the N-type GaN layer is 5 × 10⁻⁶. 17 -1×10 18 cm -3 .

[0013] As an improvement to the above technical solution, the doping concentration of Lu in the second insertion layer is 1×10⁻⁶. 5 -1×10 6 cm -3 ;

[0014] The electron blocking layer is Al. a Ga 1-a The N-layer has a density of 0.2-0.4; the electron blocking layer has a thickness of 30-50 nm.

[0015] Accordingly, the present invention also discloses a method for preparing a light-emitting diode epitaxial wafer, for preparing the above-mentioned light-emitting diode epitaxial wafer, comprising:

[0016] A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer, and a P-type GaN layer are sequentially grown.

[0017] Wherein, the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.

[0018] As an improvement to the above technical solution, the growth temperature of the first insertion layer is 900-1100℃, and the growth pressure is 100-300 Torr;

[0019] The growth temperature of the second insertion layer is 850-950℃, and the growth pressure is 100-300 Torr.

[0020] As an improvement to the above technical solution, the growth temperature of the N-type GaN layer is 1100-1150℃, and the growth pressure is 100-500 Torr;

[0021] The electron blocking layer is grown at a temperature of 900-1100℃ and a growth pressure of 100-500 Torr.

[0022] Accordingly, the present invention also discloses a light-emitting diode, including the above-mentioned light-emitting diode epitaxial wafer.

[0023] Implementing the embodiments of the present invention has the following beneficial effects:

[0024] 1. In this application, a first insertion layer and a second insertion layer are grown before and after the multi-quantum well layer, respectively. Both Lu and Sc doping increase the lattice constant of the supercell, thus providing tensile stress to the multi-quantum well layer. Under the influence of tensile stress, more In atoms can be incorporated into the multi-quantum well layer, improving its lattice quality. Correspondingly, the compressive stress of the multi-quantum well layer decreases, weakening the piezoelectric polarization effect and increasing the overlap of electron and hole wave functions. The first and second insertion layers are beneficial for improving the luminous efficiency of the light-emitting diode. Furthermore, Lu and Sc doping increases the static dielectric constant of GaN, enhancing the high-voltage withstand capability of the system, thereby improving the antistatic capability of the light-emitting diode.

[0025] 2. The first insertion layer of this application has a higher degree of lattice matching with the N-type GaN layer, which can reduce the Si doping concentration in the N-type GaN layer, thereby improving the lattice quality and increasing the luminous efficiency.

[0026] 3. The second insertion layer of this application also has a certain electron blocking effect, which can reduce the thickness of the electron blocking layer and the Al composition in the electron blocking layer. Correspondingly, it reduces the barrier peak caused by the electron blocking layer, further increases the probability of holes entering the multi-quantum well layer, and improves the luminescence efficiency. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided in an embodiment of the present invention;

[0028] Figure 2 This is a flowchart of the method for fabricating a light-emitting diode epitaxial wafer provided in an embodiment of the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0030] like Figure 1As shown, an embodiment of the present invention provides a light-emitting diode epitaxial wafer, including a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a first insertion layer 5, a multiple quantum well layer 6, a second insertion layer 7, an electron blocking layer 8, and a P-type GaN layer 9 sequentially stacked on the substrate 1.

[0031] The first insertion layer 5 is a GaN layer doped with Sc; the second insertion layer 7 is a GaN layer doped with Lu.

[0032] Since the atomic radii of Lu and Sc are larger than those of Ga, Lu and Sc doping increases the supercell lattice constant, providing tensile stress for the multiple quantum wells. Under the action of tensile stress, more In atoms can be incorporated into the multiple quantum well layer, greatly increasing the incorporation of In components in the multiple quantum well layer, thereby increasing the luminous efficiency. Furthermore, the reduction of the compressive stress in the multiple quantum wells due to the addition of Lu and Sc elements weakens the piezoelectric polarization of the multiple quantum wells, thereby increasing the overlap of electron and hole wave functions in the multiple quantum well layer and improving the luminous efficiency. The static dielectric constant of GaN is improved after Lu and Sc doping. Lu-doped and Sc-doped GaN layers can also improve the high voltage resistance of the system, thereby improving the antistatic capability of the light-emitting diode.

[0033] Among them, the first insertion layer 5 is grown on the N-type semiconductor layer 4. The doping of Sc element will lead to the increase of the band gap, thereby forming a high-energy electronic "barrier" in front of the quantum well, which will slow down the electron migration rate, which is conducive to the balance of electron-hole pairs in multiple quantum wells and increases the luminous efficiency.

[0034] The thickness of the first insertion layer 5 is 20-200 nm. If the growth thickness is <20 nm, the effect of the first insertion layer 5 is small; if the growth thickness is >200 nm, it will cause a waste of resources. For example, the thickness of the first insertion layer 5 is 20 nm, 25 nm, 50 nm, 75 nm, 100 nm, 150 nm or 200 nm, but is not limited to these.

[0035] The doping concentration of Sc is 1×10 3 -1×10 6 cm -3 If the doping concentration is <1×10 3 cm -3 It cannot slow down electron mobility if the doping concentration is >1×10 6 cm -3 This would reduce the lattice quality. For example, the Sc doping concentration of the first insertion layer 5 is 1 × 10⁻⁶. 3 cm -3 1×10 4 cm -3 1×10 5 cm -3Or 1×10 6 cm -3 However, it is not limited to this.

[0036] A second insertion layer 7 is grown on the multi-quantum well layer 6. After Lu element doping, shallow energy level impurities are induced, causing the conduction band to shift to the lower energy direction and the valence band to shift upward, which is conducive to hole injection, alleviates the problem of insufficient holes in the multi-quantum well, and increases luminous efficiency.

[0037] The thickness of the second insertion layer 7 is 20-200 nm. If the growth thickness is <20 nm, the effect of the second insertion layer 7 is minimal; if the growth thickness is >200 nm, it will result in a waste of resources. For example, the thickness of the second insertion layer 7 is 20 nm, 25 nm, 50 nm, 75 nm, 100 nm, 150 nm, or 200 nm, but it is not limited to these.

[0038] The doping concentration of Lu is 1×10 3 -1×10 6 cm -3 If the doping concentration is <1×10 3 cm -3 This is not conducive to hole injection into multi-quantum-well layers; if the doping concentration is >1×10⁻⁶, it will hinder hole injection into the multi-quantum-well layer. 6 cm -3 This would reduce the lattice quality. For example, the Lu doping concentration of the second insertion layer 7 is 1 × 10⁻⁶. 3 cm -3 1×10 4 cm -3 1×10 5 cm -3 Or 1×10 6 cm -3 However, it is not limited to this.

[0039] Preferably, the thickness ratio of the first insertion layer 5 to the second insertion layer 7 is 1:(1-2). Controlling the thickness ratio of the first insertion layer 5 and the second insertion layer 7 within this range allows the blocking of electrons by the first insertion layer 5 and the injection of holes by the second insertion layer 7 to work together, which is beneficial to the balance of electrons and holes in the multi-quantum well layer and further improves the luminous efficiency. For example, the thickness ratio of the first insertion layer 5 to the second insertion layer 7 is 1:1, 1:1.4, 1:1.5, 1:1.8 or 1:2, but is not limited to these.

[0040] Furthermore, the doping concentration of Sc in the first insertion layer 5 is 5 × 10⁻⁶. 4 -5×10 5 cm -3 The Si doping concentration in the N-type GaN layer 4 is 5 × 10⁻⁶. 17- 1×10 18 cm -3At this Sc doping concentration, the lattice matching between the N-type GaN layer 4 and the first insertion layer 5 is higher, thus allowing for a further reduction in the Si doping concentration in the N-type GaN layer.

[0041] The Lu doping concentration in the second insertion layer is 1×10⁻⁶. 5 -1×10 6 cm -3 The electron blocking layer is Al a Ga 1-a The N-layer has a density of 0.2-0.4; the electron blocking layer has a thickness of 30-50 nm. The second insertion layer 7 of this application also provides electron blocking, thus simplifying the structure of the electron blocking layer 8, reducing the Al composition in the electron blocking layer 8, and decreasing the thickness of the electron blocking layer 8. Correspondingly, this reduces the barrier spike caused by the electron blocking layer 8, further optimizing the probability of holes entering the multi-quantum-well layer and further improving luminous efficiency.

[0042] Furthermore, the thickness of the nucleation layer 2 is 20-100 nm;

[0043] The thickness of the intrinsic GaN layer 3 is 0.3-2 μm;

[0044] The thickness of the N-type GaN layer 4 is 1-3 μm;

[0045] The multi-quantum well layer 6 includes periodically stacked quantum well layers and quantum barrier layers, with a stacking period of 3-15. The thickness of the quantum well layer is 2-5 nm, and the thickness of the quantum barrier layer is 8-12 nm.

[0046] The thickness of the p-type GaN layer 9 is 200-300 nm, and the doping concentration of the p-type GaN layer 9 is 5 × 10⁻⁶. 17 -1×10 20 cm -3 .

[0047] Correspondingly, such as Figure 2 As shown, the present invention also provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:

[0048] S101 provides a substrate

[0049] A sapphire substrate is selected, and the reaction chamber temperature is controlled at 1000-1200℃ and the pressure at 200-600 Torr. The sapphire substrate is subjected to high-temperature annealing for 5-8 minutes in an H2 atmosphere to clean the particles and oxides on the surface of the sapphire substrate.

[0050] S102 nucleation layer

[0051] The nucleation layer can be made of AlGaN or AlN.

[0052] The reaction chamber temperature is controlled at 500-700℃ and the pressure at 200-400 Torr. NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, TMGa is introduced as the Ga source, and TMAl is introduced as the Al source.

[0053] S103 grows intrinsic GaN layers

[0054] The reaction chamber temperature is controlled at 1100-1150℃, the pressure at 100-500 Torr, NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, and TMGa is introduced as the Ga source.

[0055] S104 grows N-type GaN layer

[0056] The reaction chamber temperature is controlled at 1100-1150℃, the pressure at 100-500 Torr, NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, TMGa is introduced as the Ga source, and SiH4 is introduced as the doping source.

[0057] S105 grows the first insertion layer

[0058] The reaction chamber temperature is controlled at 900-1100℃ and the pressure at 100-300 Torr. NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, and the volume ratio of N2 to H2 is 1:(1-5). TMGa is introduced as the Ga source and Sc(TMHD)3 is introduced as the doping source.

[0059] S106 grows multiple quantum well layers

[0060] The reaction chamber temperature was controlled at 700-800℃ and the pressure at 100-500 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow a quantum well layer.

[0061] The reaction chamber temperature was controlled at 800-900℃, the pressure was kept constant, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TEGa was introduced as the Ga source to grow a quantum barrier layer.

[0062] Quantum well layers and quantum barrier layers are repeatedly stacked and periodically grown.

[0063] S107 grows the second insertion layer

[0064] The reaction chamber temperature is controlled at 850-950℃ and the pressure at 100-300 Torr. NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, and the volume ratio of N2 to H2 is 1:(1-5). TMGa is introduced as the Ga source and Lu(TMHD)3 is introduced as the doping source.

[0065] S108 growth electron blocking layer

[0066] The reaction chamber temperature is controlled at 900-1100℃, the pressure at 100-500 Torr, NH3 is introduced as the N source, N2 and H2 are introduced as the carrier gas, TMGa is introduced as the Ga source, and TMAl is introduced as the Al source.

[0067] S109 grows P-type GaN layer

[0068] The reaction chamber temperature is controlled at 800-1000℃, the pressure at 100-300 Torr, NH3 is introduced as the N source, TMGa is introduced as the Ga source, and CP2Mg is introduced as the doping source.

[0069] The present invention will be further illustrated below with specific embodiments.

[0070] In embodiments of the present invention, epitaxial wafers are grown using a Veeco C4 MOCVD (Metal Organic Chemical Vapor Deposition) system. High-purity H2 and / or high-purity N2 are used as the carrier gas, high-purity NH3 as the N source, TMGa (trimethylgallium) and / or TEGa (triethylgallium) as the gallium source, TMAl (trimethylaluminum) as the aluminum source, TMIn (trimethylindium) as the indium source, SiH4 (silane) as the N-type dopant, CP2Mg (magnesium dicerone) as the P-type dopant, Sc(TMHD)3 as the Sc dopant source, and Lu(TMHD)3 as the Lu dopant source. These selections are illustrative and not limited to the above examples.

[0071] Example 1

[0072] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0073] The substrate is a sapphire substrate;

[0074] The nucleation layer is an AlGaN layer with a thickness of 30 nm;

[0075] The thickness of the intrinsic GaN layer is 600 nm;

[0076] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 18 cm -3 The thickness is 2μm;

[0077] The multiple quantum well layer consists of alternating layers of quantum well layers and quantum barrier layers. The quantum well layer is an InGaN layer with a thickness of 3 nm, and the quantum barrier layer is a GaN layer with a thickness of 10 nm. The number of stacking periods is 10.

[0078] The first insertion layer is a GaN layer doped with Sc, and the Sc doping concentration is 1×10⁻⁶. 4 cm -3 The thickness is 80nm;

[0079] The second insertion layer is a Lu-doped GaN layer with a Lu doping concentration of 1×10⁻⁶. 4 cm -3 The thickness is 50nm;

[0080] The electron blocking layer is Al 0.45 Ga 0.55 N layers, with a thickness of 100nm;

[0081] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 4nm.

[0082] The above-mentioned method for fabricating an epitaxial wafer of a light-emitting diode includes the following steps:

[0083] S101 provides a substrate

[0084] A sapphire substrate was selected, and the reaction chamber temperature was controlled at 1000℃ and the pressure at 400 Torr. The sapphire substrate was subjected to high-temperature annealing for 6 minutes in an H2 atmosphere.

[0085] S102 nucleation layer

[0086] The reaction chamber temperature was controlled at 500℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, and TMAl was introduced as the Al source.

[0087] S103 grows intrinsic GaN layers

[0088] The reaction chamber temperature was controlled at 1100℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TMGa was introduced as the Ga source.

[0089] S104 grows N-type semiconductor layer

[0090] The reaction chamber temperature was controlled at 1150℃ and the pressure at 300 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, and SiH4 was introduced as the doping source.

[0091] S105 grows the first insertion layer

[0092] The reaction chamber temperature was controlled at 1000℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, the volume ratio of N2 and H2 was 1:2, TMGa was introduced as the Ga source, and Sc(TMHD)3 was introduced as the doping source.

[0093] S106 grows multiple quantum well layers

[0094] The reaction chamber temperature was controlled at 700℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 as the carrier gas, TEGa as the Ga source, and TMIn as the In source to grow a quantum well layer.

[0095] The reaction chamber temperature was controlled at 800℃, the pressure was kept constant, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, and TEGa was introduced as the Ga source to grow a quantum barrier layer.

[0096] Quantum well layers and quantum barrier layers are repeatedly stacked and periodically grown.

[0097] S107 grows the second insertion layer

[0098] The reaction chamber temperature was controlled at 900℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, the volume ratio of N2 and H2 was 1:2, TMGa was introduced as the Ga source, and Lu(TMHD)3 was introduced as the doping source.

[0099] S108 growth electron blocking layer

[0100] The reaction chamber temperature was controlled at 1000℃ and the pressure at 200 Torr. NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, and TMAl was introduced as the Al source.

[0101] S109 grows P-type GaN layer

[0102] The reaction chamber temperature was controlled at 1000℃ and the pressure at 200 Torr. NH3 was introduced as the N source, TMGa was introduced as the Ga source, and CP2Mg was introduced as the doping source.

[0103] Example 2

[0104] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0105] The substrate is a sapphire substrate;

[0106] The nucleation layer is an AlGaN layer with a thickness of 30 nm;

[0107] The thickness of the intrinsic GaN layer is 600 nm;

[0108] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 18 cm -3 The thickness is 2μm;

[0109] The multiple quantum well layer consists of alternating layers of quantum well layers and quantum barrier layers. The quantum well layer is an InGaN layer with a thickness of 3 nm, and the quantum barrier layer is a GaN layer with a thickness of 10 nm. The number of stacking periods is 10.

[0110] The first insertion layer is a GaN layer doped with Sc, and the Sc doping concentration is 1×10⁻⁶. 4 cm -3 The thickness is 50nm;

[0111] The second insertion layer is a Lu-doped GaN layer with a Lu doping concentration of 1×10⁻⁶. 4 cm -3 The thickness is 50nm;

[0112] The electron blocking layer is Al 0.45 Ga 0.55 N layers, with a thickness of 100nm;

[0113] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 4nm.

[0114] The fabrication method of the above-mentioned light-emitting diode epitaxial wafer is the same as that in Example 1.

[0115] Example 3

[0116] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0117] The substrate is a sapphire substrate;

[0118] The nucleation layer is an AlGaN layer with a thickness of 30 nm;

[0119] The thickness of the intrinsic GaN layer is 600 nm;

[0120] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 17 cm -3 The thickness is 2μm;

[0121] The multiple quantum well layer consists of alternating layers of quantum well layers and quantum barrier layers. The quantum well layer is an InGaN layer with a thickness of 3 nm, and the quantum barrier layer is a GaN layer with a thickness of 10 nm. The number of stacking periods is 10.

[0122] The first insertion layer is a GaN layer doped with Sc, and the Sc doping concentration is 1×10⁻⁶. 5 cm -3 The thickness is 50nm;

[0123] The second insertion layer is a Lu-doped GaN layer with a Lu doping concentration of 1×10⁻⁶. 4 cm -3 The thickness is 50nm;

[0124] The electron blocking layer is Al 0.45 Ga 0.55 N layers, with a thickness of 100nm;

[0125] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 4nm.

[0126] The fabrication method of the above-mentioned light-emitting diode epitaxial wafer is the same as that in Example 1.

[0127] Example 4

[0128] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0129] The substrate is a sapphire substrate;

[0130] The nucleation layer is an AlGaN layer with a thickness of 30 nm;

[0131] The thickness of the intrinsic GaN layer is 600 nm;

[0132] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 18 cm -3 The thickness is 2μm;

[0133] The multiple quantum well layer consists of alternating layers of quantum well layers and quantum barrier layers. The quantum well layer is an InGaN layer with a thickness of 3 nm, and the quantum barrier layer is a GaN layer with a thickness of 10 nm. The number of stacking periods is 10.

[0134] The first insertion layer is a GaN layer doped with Sc, and the Sc doping concentration is 1×10⁻⁶. 4 cm -3 The thickness is 50nm;

[0135] The second insertion layer is a Lu-doped GaN layer with a Lu doping concentration of 5 × 10⁻⁶. 5 cm -3 The thickness is 50nm;

[0136] The electron blocking layer is Al 0.3 Ga 0.7 N layers, 40nm thick;

[0137] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 4nm.

[0138] The fabrication method of the above-mentioned light-emitting diode epitaxial wafer is the same as that in Example 1.

[0139] Example 5

[0140] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer and a P-type GaN layer sequentially stacked on the substrate;

[0141] The substrate is a sapphire substrate;

[0142] The nucleation layer is an AlGaN layer with a thickness of 30 nm;

[0143] The thickness of the intrinsic GaN layer is 600 nm;

[0144] The Si doping concentration in the N-type GaN layer is 7 × 10⁻⁶. 17 cm -3 The thickness is 2μm;

[0145] The multiple quantum well layer consists of alternating layers of quantum well layers and quantum barrier layers. The quantum well layer is an InGaN layer with a thickness of 3 nm, and the quantum barrier layer is a GaN layer with a thickness of 10 nm. The number of stacking periods is 10.

[0146] The first insertion layer is a GaN layer doped with Sc, and the Sc doping concentration is 1×10⁻⁶. 5 cm -3 The thickness is 50nm;

[0147] The second insertion layer is a Lu-doped GaN layer with a Lu doping concentration of 5 × 10⁻⁶. 5 cm -3 The thickness is 50nm;

[0148] The electron blocking layer is Al 0.3 Ga 0.7 N layers, 40nm thick;

[0149] The Mg doping concentration in the p-type GaN layer is 5 × 10⁻⁶. 18 cm -3 The thickness is 4nm.

[0150] The fabrication method of the above-mentioned light-emitting diode epitaxial wafer is the same as that in Example 1.

[0151] Comparative Example 1

[0152] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not include the first and second insertion layers. Correspondingly, the fabrication method also excludes the fabrication steps of these two layers; all other aspects are the same as in Example 1.

[0153] Comparative Example 2

[0154] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not include a first insertion layer. Correspondingly, the fabrication method also excludes the step of fabricating the first insertion layer; all other steps are the same as in Example 1.

[0155] Comparative Example 3

[0156] This comparative example provides a light-emitting diode epitaxial wafer, which differs from Example 1 in that it does not include a second insertion layer. Correspondingly, the fabrication method also excludes the step of fabricating the second insertion layer; all other aspects are the same as in Example 1.

[0157] Performance testing:

[0158] The light-emitting diode epitaxial wafers obtained in Examples 1-5 and Comparative Examples 1-3 were fabricated into 10mil × 24mil chips for photoelectric performance testing.

[0159] (1) Brightness: The brightness was tested on the same LED spot tester under a driving current of 200mA;

[0160] (2) Antistatic ability: The antistatic ability of the sample was tested using an 8KV pulse on the same LED spot tester.

[0161] The test results are shown in Table 1.

[0162] Table 1. Photoelectric performance test results of LED epitaxial wafers

[0163] Example 1 197.3 97.2 Example 2 197.4 97.4 Example 3 197.9 98.4 Example 4 198.0 98.6 Example 5 198.3 99.2 Comparative Example 1 190.7 90.2 Comparative Example 2 193.2 92.1 Comparative Example 3 192.9 91.6

[0164] As shown in Table 1, the chip fabricated from the LED epitaxial wafer provided in Example 1 of this invention exhibits improved brightness and antistatic properties compared to the chip fabricated in the comparative example. A comparison between Example 2 and Example 1 reveals that optimizing the thickness ratio of the first and second insertion layers further enhances the chip's photoelectric performance. Example 3, by optimizing the Sc doping concentration in the first insertion layer, reduces the Si doping concentration in the N-type GaN layer, thereby improving the lattice matching between the first insertion layer and the N-type GaN layer and increasing luminous efficiency. Example 4, by optimizing the Lu doping concentration in the second insertion layer, reduces the thickness of the electron blocking layer and the Al composition, allowing for more hole injection into the multi-quantum well layer and improving luminous efficiency. In summary, this invention improves the brightness and antistatic properties of the chip by growing the first and second insertion layers before and after the multi-quantum well layer.

[0165] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate and a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate; The first insertion layer is a Sc-doped GaN layer, and the second insertion layer is a Lu-doped GaN layer; The thickness of the first insertion layer is 20-200 nm; the thickness of the second insertion layer is 20-200 nm.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The thickness ratio of the first insertion layer to the second insertion layer is 1:(1-2).

3. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The doping concentration of Sc in the first insertion layer is 1×10⁻⁶. 3 -1×10 6 cm -3 The doping concentration of Lu in the second insertion layer is 1×10⁻⁶. 3 -1×10 6 cm -3 .

4. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The doping concentration of Sc in the first insertion layer is 5 × 10⁻⁶. 4 -5×10 5 cm -3 The Si doping concentration in the N-type GaN layer is 5 × 10⁻⁶. 17 -1×10 18 cm -3 .

5. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The doping concentration of Lu in the second insertion layer is 1×10⁻⁶. 5 -1×10 6 cm -3 ; The electron blocking layer is Al. a Ga 1-a The N-layer has a density of 0.2-0.4; the electron blocking layer has a thickness of 30-50 nm.

6. A method for preparing a light-emitting diode epitaxial wafer, used to prepare a light-emitting diode epitaxial wafer as described in any one of claims 1-5, characterized in that, include: A substrate is provided on which a nucleation layer, an intrinsic GaN layer, an N-type GaN layer, a first insertion layer, a multiple quantum well layer, a second insertion layer, an electron blocking layer, and a P-type GaN layer are sequentially grown. Wherein, the first insertion layer is a GaN layer doped with Sc, and the second insertion layer is a GaN layer doped with Lu.

7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 6, characterized in that, The growth temperature of the first insertion layer is 900-1100℃, and the growth pressure is 100-300 Torr; The growth temperature of the second insertion layer is 850-950℃, and the growth pressure is 100-300 Torr.

8. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 6, characterized in that, The growth temperature of the N-type GaN layer is 1100-1150℃, and the growth pressure is 100-500 Torr. The electron blocking layer is grown at a temperature of 900-1100℃ and a growth pressure of 100-500 Torr.

9. A light-emitting diode, characterized in that, The light-emitting diode includes a light-emitting diode epitaxial wafer as described in any one of claims 1-5.

Images