Dual-band dual-mode power amplifier

Abstract

The application provides a simultaneous dual-frequency dual-mode power amplifier, which comprises an input matching circuit, a stabilizing circuit, a power amplifier transistor, a direct current bias circuit and an output matching circuit, the direct current bias circuit comprises a gate direct current bias circuit and a drain direct current bias circuit, one end of the input matching circuit is connected to ground through an input direct current isolation capacitor C1, an input feeder and an input load in series, the other end of the input matching circuit is connected to the gate of the power amplifier transistor through the stabilizing circuit and a gate microstrip line, and the gate of the power amplifier transistor is also connected to the gate direct current bias circuit through the gate microstrip line; the application can realize F-class and inverse F-class power amplifiers at dual operating frequency points, has the advantages of simple structure, easy processing, high efficiency and low cost, and has the advantages of dual frequency bands and high efficiency.

Description

Technical Field

[0001] This invention relates to a simultaneous dual-frequency dual-mode power amplifier, belonging to the field of wireless communication power amplifier technology. Background Technology

[0002] With the continuous development of communication technology, from 1G to 5G, higher requirements have been placed on signal transmission rates, power, and frequency bandwidth. Today's 5G communication technology is characterized by high efficiency, low latency, and low power consumption. Since it also needs to include the frequency bands of previous generations of communication technologies, multi-band, multi-standard communication schemes have been proposed to prevent the waste of frequency resources. To fully utilize these frequency bands, the transceiver equipment of mobile communication systems needs to be able to simultaneously transmit and receive signals from different frequency bands. This also requires the power amplifiers in the equipment to be able to transmit signals from different frequency bands simultaneously. Therefore, research on dual-band and multi-band power amplifiers has significant practical implications.

[0003] Traditional power amplifiers are mainly classified into Class A, Class B, Class AB, and Class C. Class A amplifiers have excellent linearity but high losses and low efficiency. Class B amplifiers have slightly worse linearity than Class A, but significantly higher efficiency, theoretically reaching 78.5%. Class AB amplifiers offer a balance between efficiency and linearity compared to the first two. Class C amplifiers have very high overall efficiency, theoretically reaching 90%, due to the short overlap time between current and voltage on the transistors; however, the output signal is highly susceptible to distortion and typically requires specific frequency selection equipment for pairing.

[0004] The key to improving the efficiency of Class F amplifiers lies in harmonic control. By disconnecting odd harmonics and short-circuiting even harmonics at the operating frequency, the waveforms of the operating voltage and current no longer overlap, theoretically achieving 100% efficiency. The same method applies to inverse Class F amplifiers, except that odd harmonics are short-circuited while even harmonics are open-circuited. In practical circuits, controlling all harmonics is impossible, and controlling the 5th harmonic and higher harmonics does not significantly improve efficiency, while increasing circuit complexity and cost. Therefore, typically only the first three harmonics are controlled. Class F and inverse Class F are among the most important methods for improving efficiency.

[0005] The existing dual-frequency power amplifiers have many shortcomings: 1. The structural design of the existing dual-frequency power amplifiers is relatively complex, and the microstrip network design with too many parameters makes parameter tuning relatively time-consuming; 2. The existing dual-frequency power amplifiers do not have both Class F and inverse Class F power amplifier modes at the dual operating frequency points.

[0006] For example, a dual-stage dual-band high-efficiency power amplifier disclosed in Chinese invention patent CN107547050A also suffers from complex structure and dual operating frequency points that are neither Class F nor inverse Class F.

[0007] The above-mentioned issues should be considered and resolved during the design of a dual-frequency dual-mode power amplifier. Summary of the Invention

[0008] The purpose of this invention is to provide a dual-frequency dual-mode power amplifier to solve the problems of existing technologies with dual operating frequency Class F and inverse Class F, complex structure, and inefficiency.

[0009] The technical solution of this invention is:

[0010] A simultaneous dual-frequency dual-mode power amplifier includes an input matching circuit, a stabilizing circuit, a power amplifying transistor, a DC bias circuit, and an output matching circuit. The DC bias circuit includes a gate DC bias circuit and a drain DC bias circuit. One end of the input matching circuit is grounded through a series-connected input DC blocking capacitor C1, an input feed line, and an input load. The other end of the input matching circuit is connected to the gate of the power amplifying transistor through the stabilizing circuit and a gate microstrip line. The gate of the power amplifying transistor is also connected to the gate DC bias circuit through the gate microstrip line. The source of the power amplifying transistor is grounded. The drain of the power amplifying transistor is grounded through a series-connected output matching circuit, an output DC blocking capacitor C2, an output feed line, and an output load through a drain microstrip line. The drain of the power amplifying transistor is also connected to the drain DC bias circuit through a drain microstrip line.

[0011] Furthermore, the gate DC bias circuit includes a first microstrip line, a second microstrip line, capacitor C3, and capacitor C4. One end of the first microstrip line is grounded through capacitor C3, and the other end of the first microstrip line is grounded through capacitor C4. The other end of the first microstrip line is connected to the gate of the power amplifier transistor through the second microstrip line.

[0012] Furthermore, the connection point between the first microstrip line and capacitor C3 is connected to an external DC power supply, and the connection point between the first microstrip line and capacitor C3 is also grounded through gate bypass capacitor C8 and gate bypass capacitor C9, respectively.

[0013] Furthermore, the drain DC bias circuit includes a third microstrip line, a fourth microstrip line, capacitor C5, and capacitor C6. One end of the third microstrip line is grounded through capacitor C5, and the other end of the third microstrip line is grounded through capacitor C6. The other end of the third microstrip line is connected to the drain of the power amplifier transistor through the fourth microstrip line.

[0014] Furthermore, the connection point between the third microstrip line and capacitor C5 is connected to an external DC power supply, and the connection point between the third microstrip line and capacitor C5 is also grounded through drain bypass capacitor C10 and drain bypass capacitor C11, respectively.

[0015] Furthermore, the first, second, third, and fourth microstrip lines are all quarter-wavelength microstrip lines.

[0016] Furthermore, the input matching circuit adopts a T-type stub matching circuit, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a π-type stub matching circuit, or a matching circuit composed of two series microstrip lines connected in series.

[0017] Furthermore, the output matching circuit adopts a progressive matching circuit with three microstrip lines connected in series, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a T-type stub matching circuit, or a π-type stub matching circuit.

[0018] Furthermore, the input matching circuit, stabilization circuit, power amplifier transistor, DC bias circuit, and output matching circuit are disposed on the upper surface of the dielectric substrate, and a metal ground is disposed on the lower surface of the dielectric substrate.

[0019] Furthermore, the DC bias circuit, acting as a harmonic control circuit, achieves a second harmonic short circuit and a third harmonic open circuit at a frequency of 2.4 GHz, satisfying the conditions for a Class F power amplifier; at another frequency of 5 GHz, the second harmonic is open and the third harmonic is short-circuited, satisfying the conditions for an inverse Class F power amplifier. At the same time, the DC bias circuit fulfills the function of isolating DC signals, thus obtaining a dual-frequency, dual-mode power amplifier that simultaneously achieves Class F and inverse Class F at two frequency points.

[0020] The beneficial effects of this invention are as follows: This simultaneous dual-frequency dual-mode power amplifier can control the harmonic impedance at both 2.4GHz and 5GHz frequencies, and can accurately match the fundamental and harmonic impedances, thereby improving the efficiency of the dual-frequency power amplifier and achieving a dual-frequency high-efficiency power amplifier with good performance consistency across the two frequency bands. This simultaneous dual-frequency dual-mode power amplifier can function as both a Class F and inverse Class F power amplifier at both operating frequencies. It features a simple structure, ease of fabrication, high efficiency, and low cost, offering the advantages of dual-band operation and high efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of the dual-frequency dual-mode power amplifier according to an embodiment of the present invention;

[0022] Figure 2 This is a schematic diagram of the scattering parameter characteristics of the simultaneous dual-frequency dual-mode power amplifier of the embodiment, wherein (a) is a schematic diagram of the input reflection coefficient S101 of the simultaneous dual-frequency dual-mode power amplifier of the embodiment, and (b) is a schematic diagram of the small signal gain S21 of the simultaneous dual-frequency dual-mode power amplifier of the embodiment.

[0023] Figure 3This is a schematic diagram of the output power, gain, and drain efficiency of the simultaneous dual-frequency dual-mode power amplifier of the embodiment, wherein (a) is a schematic diagram of the output power of the simultaneous dual-frequency dual-mode power amplifier of the embodiment, (b) is a schematic diagram of the gain of the simultaneous dual-frequency dual-mode power amplifier of the embodiment, and (c) is a schematic diagram of the drain efficiency of the simultaneous dual-frequency dual-mode power amplifier of the embodiment.

[0024] Figure 4 This is a schematic diagram of the drain current and voltage waveforms of the dual-frequency dual-mode power amplifier at two frequency points, 2.4 GHz and 5 GHz, wherein (a) is a schematic diagram of the drain current and voltage waveforms at the 2.4 GHz frequency point, and (b) is a schematic diagram of the drain current and voltage waveforms at the 5 GHz frequency point.

[0025] Wherein: 1-Input matching circuit, 2-Stabilizing circuit, 3-Gate DC bias circuit, 4-Power amplifier transistor, 5-Drain DC bias circuit, 6-Output matching circuit, 7-Input feed line, 8-Output feed line, 9-Gate microstrip line, 10-Drain microstrip line, 11-Input load, 12-Output load;

[0026] 101 - First input microstrip line, 102 - Second input microstrip line, 103 - Open circuit stub;

[0027] 31 - First microstrip line, 32 - Second microstrip line;

[0028] 51 - Third microstrip line, 52 - Fourth microstrip line. Detailed Implementation

[0029] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] Example

[0031] A simultaneous dual-frequency dual-mode power amplifier, such as Figure 1 The circuit includes an input matching circuit 1, a stabilizing circuit 2, a power amplifier transistor 4, a DC bias circuit, and an output matching circuit 6. The DC bias circuit includes a gate DC bias circuit 3 and a drain DC bias circuit 5. One end of the input matching circuit 1 is grounded through a series connection of an input DC blocking capacitor C1, an input feed line 7, and an input load. The other end of the input matching circuit 1 is connected to the gate of the power amplifier transistor 4 through the stabilizing circuit 2 and a gate microstrip line 9. The gate of the power amplifier transistor 4 is also connected to the gate DC bias circuit 3 through the gate microstrip line 9. The source of the power amplifier transistor 4 is grounded. The drain of the power amplifier transistor 4 is grounded through a series connection of a drain microstrip line 10, an output matching circuit 6, an output DC blocking capacitor C2, an output feed line 8, and an output load. The drain of the power amplifier transistor 4 is also connected to the drain DC bias circuit 5 through the drain microstrip line 10.

[0032] This type of simultaneous dual-frequency dual-mode power amplifier can control the harmonic impedance at both 2.4GHz and 5GHz frequencies, and accurately match the fundamental and harmonic impedances, thereby improving the efficiency of the dual-frequency power amplifier and achieving a dual-frequency high-efficiency power amplifier with good performance consistency across both frequency bands. This simultaneous dual-frequency dual-mode power amplifier can function as both a Class F and inverse Class F power amplifier at both operating frequencies. It features a simple structure, ease of fabrication, high efficiency, and low cost, offering the advantages of dual-band operation and high efficiency.

[0033] like Figure 1 The gate DC bias circuit 3 includes a first microstrip line 31, a second microstrip line 32, capacitors C3 and C4. One end of the first microstrip line 31 is grounded through capacitor C3, and the other end of the first microstrip line 31 is grounded through capacitor C4. The other end of the first microstrip line 31 is connected to the gate of the power amplifier transistor 4 through the second microstrip line 32. The connection between the first microstrip line 31 and capacitor C3 is connected to an external DC power supply. The connection between the first microstrip line 31 and capacitor C3 is also grounded through gate bypass capacitors C8 and C9, respectively.

[0034] This type of dual-frequency dual-mode power amplifier has a gate DC bias circuit 3 including a first microstrip line 31, a second microstrip line 32, and capacitors C3 and C4 connected in parallel. It provides voltage to the gate of the power amplifier transistor 4 in order to isolate the DC signal so that the DC signal will not affect the radio frequency signal.

[0035] like Figure 1 The drain DC bias circuit 5 includes a third microstrip line 51, a fourth microstrip line 52, capacitors C5 and C6. One end of the third microstrip line 51 is grounded through capacitor C5, and the other end of the third microstrip line 51 is grounded through capacitor C6. The other end of the third microstrip line 51 is connected to the drain of the power amplifier transistor 4 through the fourth microstrip line 52. The connection between the third microstrip line 51 and capacitor C5 is connected to an external DC power supply. The connection between the third microstrip line 51 and capacitor C5 is also grounded through drain bypass capacitors C10 and C11, respectively.

[0036] This type of dual-frequency dual-mode power amplifier has a drain DC bias circuit 5 including a third microstrip line 51, a fourth microstrip line 52, and capacitors C5 and C6 connected in parallel. It provides voltage to the drain of the power amplifier transistor 4 and aims to isolate DC signals so that DC signals do not affect radio frequency signals.

[0037] In this type of simultaneous dual-frequency dual-mode power amplifier, the first microstrip line 31, the second microstrip line 32, the third microstrip line 51, and the fourth microstrip line 52 all employ quarter-wavelength microstrip lines. The characteristics of quarter-wavelength microstrip lines themselves satisfy the harmonic control requirements of Class F power amplifiers, generating high impedance at the required operating frequency, thus providing excellent isolation between DC and RF signals. These two characteristics make it possible to incorporate harmonic control circuitry into the DC bias circuit.

[0038] The input matching circuit 1 can be a T-type stub matching circuit, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a π-type stub matching circuit, or a matching circuit composed of two series-connected microstrip lines. For example... Figure 1 The input matching circuit 1 employs a T-type microstrip line network. It includes a first input microstrip line, a second input microstrip line, and an open-circuit stub. One end of the first input microstrip line is connected to the input DC blocking capacitor C1, and the other end is connected to the stabilizing circuit 2 via the second input microstrip line. The open-circuit stub is connected at the junction of the first and second input microstrip lines. This ensures that the input of the power amplifier transistor 4 is matched to 50 ohms at both 2.4 GHz and 5 GHz frequencies, achieving matching at 2.4 GHz and 5 GHz.

[0039] like Figure 1 The stabilization circuit 2 includes a resistor R and a capacitor C7. The two ends of the capacitor C7 are connected to the input matching circuit 1 and the gate of the power amplifier transistor 4, respectively. The resistor R and the capacitor C7 are connected in parallel. The purpose of the stabilization circuit 2 is to prevent the power amplifier transistor 4 from oscillating at its operating frequency, thus affecting its normal operation.

[0040] The output matching circuit 6 can employ a progressive matching circuit with three microstrip lines connected in series, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a T-type stub matching circuit, or a π-type stub matching circuit. For example... Figure 1 The output matching circuit 6 consists of a progressive matching network connected by three microstrip lines. The progressive matching to 50 ohms through these three microstrip lines ensures better matching at the 2.4GHz and 5GHz frequencies, resulting in better signal transmission to the output. The power amplifier transistor 4 can be a CG2H40010F transistor. The input matching circuit 1, stabilization circuit 2, power amplifier transistor 4, DC bias circuit, and output matching circuit 6 are located on the upper surface of the dielectric substrate, while the lower surface of the dielectric substrate has a metal ground. The dielectric constant of the dielectric substrate is between 1 and 20.

[0041] This type of dual-frequency dual-mode power amplifier uses a DC bias circuit as a harmonic control circuit to achieve a second harmonic short circuit and a third harmonic open circuit at a frequency of 2.4 GHz, satisfying the conditions for a Class F power amplifier. At another frequency of 5 GHz, the second harmonic is open circuit and the third harmonic is short circuit, satisfying the conditions for an inverse Class F power amplifier. At the same time, the DC bias circuit also serves to isolate DC signals, thus obtaining a dual-frequency dual-mode power amplifier that simultaneously achieves Class F and inverse Class F at two frequencies.

[0042] This type of simultaneous dual-frequency dual-mode power amplifier uses 2.4GHz and 5GHz quarter-wavelength microstrip lines in series in the DC bias circuit. Specifically, the first microstrip line 31 is connected in series with the second microstrip line 32, and the third microstrip line 51 is connected in series with the fourth microstrip line 52. A capacitor is connected in parallel after each microstrip line segment. Simulation results show that this structure allows the 2.4GHz frequency to meet the impedance conditions of a Class F power amplifier, with the second harmonic short-circuited and the third harmonic open-circuited; and the 5GHz frequency to meet the Class F... -1 The impedance conditions of the power amplifier, the second harmonic open circuit, and the third harmonic short circuit were investigated, and the feasibility of the bias design was verified through simulation.

[0043] This type of dual-frequency dual-mode power amplifier simplifies the input matching circuit 1 and the output matching circuit 6 by using the DC bias circuit as the harmonic control circuit. It can achieve Class F and inverse Class F at two frequency points of 2.4GHz and 5GHz respectively, thereby improving the efficiency at both frequency points and achieving high efficiency.

[0044] Compared with the existing cascaded two-stage amplifiers, this type of simultaneous dual-frequency dual-mode power amplifier combines the harmonic control network with the bias circuit through a single-pole amplifier, which can reduce the number of corresponding microstrip lines, greatly simplify the design complexity, and effectively reduce the area of ​​the device.

[0045] This type of simultaneous dual-frequency dual-mode power amplifier connects the input DC blocking capacitor and the output DC blocking capacitor to the external circuit via input feed line 7 and output feed line 8, respectively. By drilling holes in the dielectric substrate, grounding points can be provided for the parallel capacitors used in the gate DC bias circuit 3 and the drain DC bias circuit 5. In practical use, the gate DC bias circuit 3 and the DC drain bias circuit are connected to an external DC power supply.

[0046] This type of dual-frequency dual-mode power amplifier can simultaneously control the second and third harmonic impedances in two frequency bands, and has good fundamental frequency matching effect and good performance consistency in the two frequency bands.

[0047] The experimental simulation verification of this simultaneous dual-frequency dual-mode power amplifier in the embodiment is as follows:

[0048] This type of simultaneous dual-frequency dual-mode power amplifier uses Rogers 5880 dielectric substrate with a dielectric constant of 2.2 and a thickness of 0.508 mm. The surface-mount resistor and capacitor in stabilization circuit 2 are 1 Ω and 0.2 pF, respectively. The characteristics of this simultaneous dual-frequency dual-mode power amplifier obtained through simulation using ADS software are as follows:

[0049] Figure 2 This is a schematic diagram of the scattering parameter characteristics of the dual-frequency dual-mode power amplifier in the embodiment. Figure 2 (a) is a schematic diagram of the input reflection coefficient S101 of the simultaneous dual-frequency dual-mode power amplifier in the embodiment. Figure 2 (b) is a schematic diagram of the small-signal gain S21 of the simultaneous dual-frequency dual-mode power amplifier in the embodiment. Figure 2 This type of dual-frequency dual-mode power amplifier has an input reflection coefficient (S101), i.e., return loss, below -20dB at the 2.4GHz frequency point, and a small-signal gain (S21) above 18dB; at the 5GHz frequency point, the input reflection coefficient (S101) is below -20dB, and the gain is above 102dB.

[0050] Figure 3 This is a schematic diagram of the output power, gain, and drain efficiency of the dual-frequency dual-mode power amplifier in the embodiment. Figure 3 (a) is a schematic diagram of the output power of the simultaneous dual-frequency dual-mode power amplifier in the embodiment. Figure 3 (b) is a schematic diagram of the gain of the dual-frequency dual-mode power amplifier in the embodiment. Figure 3 (c) is a schematic diagram of the drain efficiency of the dual-frequency dual-mode power amplifier in the embodiment. Figure 3 This type of simultaneous dual-frequency dual-mode power amplifier exhibits a power drain efficiency greater than 70%, an output power greater than 40 dBm, and a gain greater than 101 dB in the 2.15-2.45 GHz band; and a power drain efficiency greater than 70%, an output power greater than 39 dBm, and a gain greater than 10 dB in the 4.95-5.05 GHz band. It demonstrates good performance consistency across both operating frequencies.

[0051] Figure 4 This is a schematic diagram of the drain current and voltage waveforms of the dual-frequency dual-mode power amplifier at two frequency points: 2.4GHz and 5GHz. Figure 4 (a) is a schematic diagram of the drain current-voltage waveform at a frequency of 2.4 GHz. Figure 4 (b) Schematic diagram of the drain current-voltage waveform at 25 GHz. Figure 4This dual-frequency dual-mode power amplifier has a drain current and voltage waveform that meets the requirements of a Class F power amplifier at 2.4 GHz and a drain current and voltage waveform that meets the requirements of an inverse Class F power amplifier at 5 GHz.

[0052] This simultaneous dual-frequency high-efficiency power amplifier simplifies the output matching circuit 6 by combining a DC bias circuit with a harmonic control network, enabling it to simultaneously implement both Class F and inverse Class F power amplifier modes at two different frequency points. The high efficiency characteristics of Class F and inverse Class F power amplifiers make this invention a promising candidate for applications in communications.

[0053] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A simultaneous dual-frequency dual-mode power amplifier, comprising an input matching circuit, a stabilizing circuit, a power amplification transistor, a DC bias circuit, and an output matching circuit, wherein the DC bias circuit comprises a gate DC bias circuit and a drain DC bias circuit, characterized in that: One end of the input matching circuit is grounded through a series-connected input DC blocking capacitor C1, the input feed line, and the input load. The other end of the input matching circuit is connected to the gate of the power amplifier transistor through a stabilizing circuit and a gate microstrip line. The gate of the power amplifier transistor is also connected to the gate DC bias circuit through the gate microstrip line. The source of the power amplifier transistor is grounded. The drain of the power amplifier transistor is grounded through a series-connected output matching circuit, output DC blocking capacitor C2, the output feed line, and the output load through a drain microstrip line. The drain of the power amplifier transistor is also connected to the drain DC bias circuit through the drain microstrip line. The gate DC bias circuit includes a first microstrip line, a second microstrip line, capacitor C3 and capacitor C4. One end of the first microstrip line is grounded through capacitor C3, and the other end of the first microstrip line is grounded through capacitor C4. The other end of the first microstrip line is connected to the gate of the power amplifier transistor through the second microstrip line. The connection between the first microstrip line and capacitor C3 is connected to an external DC power supply. The connection between the first microstrip line and capacitor C3 is also grounded through gate bypass capacitor C8 and gate bypass capacitor C9, respectively. The drain DC bias circuit includes a third microstrip line, a fourth microstrip line, capacitor C5 and capacitor C6. One end of the third microstrip line is grounded through capacitor C5, and the other end of the third microstrip line is grounded through capacitor C6. The other end of the third microstrip line is connected to the drain of the power amplifier transistor through the fourth microstrip line. The connection between the third microstrip line and capacitor C5 is connected to an external DC power supply. The connection between the third microstrip line and capacitor C5 is also grounded through drain bypass capacitors C10 and C11 respectively. The first, second, third and fourth microstrip lines are all quarter-wavelength microstrip lines.

2. The simultaneous dual-frequency dual-mode power amplifier as described in claim 1, characterized in that: The input matching circuit adopts a T-type stub matching circuit, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a π-type stub matching circuit, or a matching circuit composed of two series microstrip lines connected in series.

3. The simultaneous dual-frequency dual-mode power amplifier as described in claim 1, characterized in that: The output matching circuit adopts a progressive matching circuit with three microstrip lines connected in series, an L-type stub matching circuit, a cascaded multi-stub matching circuit, a T-type stub matching circuit, or a π-type stub matching circuit.

4. The simultaneous dual-frequency dual-mode power amplifier as described in claim 1, characterized in that: The input matching circuit, stabilization circuit, power amplifier transistor, DC bias circuit, and output matching circuit are located on the upper surface of the dielectric substrate, and a metal ground is provided on the lower surface of the dielectric substrate.

5. The simultaneous dual-frequency dual-mode power amplifier as described in claim 1, characterized in that: The DC bias circuit, acting as a harmonic control circuit, achieves a second harmonic short circuit and a third harmonic open circuit at a frequency of 2.4 GHz, satisfying the conditions for a Class F power amplifier; at another frequency of 5 GHz, the second harmonic is open circuit and the third harmonic is short circuit, satisfying the conditions for an inverse Class F power amplifier. At the same time, the DC bias circuit also serves to isolate DC signals, thus achieving a dual-frequency, dual-mode power amplifier that simultaneously realizes both Class F and inverse Class F at two frequency points.

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