A multi-channel data acquisition photoelectric conversion adapter

Abstract

The application provides a multi-channel data acquisition photoelectric conversion adapter, and belongs to the technical field of monitoring, specifically comprising an FPGA which analyzes external input multi-channel fiber data and Ethernet data, analyzes 1-way HD-SDI video data, 1-way PAL video data and 1-way Ethernet data. The HD-SDI video picture and the PAL video picture are windowed and superimposed by the FPGA to form 1-way HDMI video signal output; the data packets are compressed and packaged, and the Ethernet data packet format is used for data communication with external equipment; and the relay forwarding function of the gated fiber interface channel is also realized. According to the processing scheme, the multi-channel video and network data collected can be output to a display and a ground equipment detector for data acquisition after processing, so that the fiber data analysis, forwarding and video processing functions are realized.

Description

Technical Field

[0001] This application relates to the field of monitoring, and more particularly to a photoelectric conversion adapter that supports multi-channel data acquisition. Background Technology

[0002] During combat exercises, it is necessary to process and forward the received fiber optic signals from 1 to 6 armored vehicles and the network data signal from 1 command vehicle to ground equipment detection instruments for data acquisition and display on monitors for battlefield image display. Existing products only support single-channel data processing and cannot meet the requirements for real-time monitoring of multiple data channels and battlefield information analysis. Summary of the Invention

[0003] In view of this, this application provides a photoelectric conversion adapter that supports multi-channel data acquisition, which solves the problems in the prior art. It can process and output the acquired multi-channel video and network data to a display screen and ground equipment detector for data acquisition according to switching requirements.

[0004] The photoelectric conversion adapter supporting multi-channel data acquisition provided in this application adopts the following technical solution:

[0005] A photoelectric conversion adapter that supports multi-channel data acquisition is used to process fiber optic signals from multiple armored vehicles and network data signals from one command vehicle. The adapter includes an integrated processing board for Ethernet communication, video selection, video decoding, and video encoding. The integrated processing board includes a CPU, an FPGA, and a video processing chip.

[0006] The CPU is equipped with a first gigabit Ethernet interface and a second gigabit Ethernet interface. The first gigabit Ethernet interface is connected to the command vehicle for data transmission, and the second gigabit Ethernet interface is connected to the ground equipment detector for data transmission and reception. The FPGA is equipped with multiple first optoelectronic modules to collect fiber optic signals from multiple external vehicles. The first optoelectronic modules are connected to the GTX interface on the FPGA. The FPGA is connected to the CPU via a PCIe bus. The FPGA is equipped with a video output selection module to realize the output video selection function. The video processing chip is connected to the FPGA via a general-purpose input / output GPIO and is connected to the display screen via an HDMI cable.

[0007] The CPU performs Ethernet communication, BIT information reading and diagnosis, and debugging functions. Based on the instructions sent by the FPGA, it distributes Ethernet data. The FPGA parses the multi-channel fiber optic data input from the outside and sends the parsed video data to the video processing chip via GPIO. The video output selection module selects one or more external fiber optic signals to be output. After receiving the instructions from the video output selection module, the video processing chip completes the windowing, overlay, and selection of the video signals. The FPGA determines the commands in the parsed data and communicates the Ethernet data packets with the external device through a specific Gigabit Ethernet interface.

[0008] Optionally, the FPGA is connected to a portable display controller via a second optoelectronic module. The video output selection module sends one of the fiber optic data streams to the portable display controller via the second optoelectronic module, and simultaneously sends the fiber optic data received by the portable display controller to the data source.

[0009] Optionally, the FPGA is equipped with an indicator light corresponding to each optical fiber signal. The video output selection module selects the optical fiber signal sent to the portable display controller and turns on the corresponding indicator light, while the other indicator lights remain off.

[0010] Optionally, in the HDMI output to the display screen, the upper left corner displays the information of the tank to which the current image belongs, as well as the information of the tank that the current fiber optic signal is forwarded to the portable display controller.

[0011] Optionally, the FPGA is connected to seven fiber optic signals.

[0012] Optionally, the video processing chip is a Hisilicon SOC.

[0013] Optionally, the FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format, and then packages the video data in BT656 format and forwards it to the video processing chip.

[0014] Optionally, the FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format. The FPGA DMAs the network data to different memory addresses according to the input channel. The FPGA generates an interrupt to notify the software to process the data when the DMA is completed or at regular intervals.

[0015] Optionally, the FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format. The FPGA processes the input video data, selects one video output from multiple input video data and input color bars, and outputs the selected video to a portable display through the SRIO interface.

[0016] Optionally, the adapter further includes a power module and a button, wherein the power module supplies power to the adapter and the button controls the video output selection.

[0017] In summary, this application includes the following beneficial technical effects:

[0018] The external 7-channel fiber optic data is converted from optical to electrical by the optoelectronic module, and then parsed by the FPGA for PAL, HD-SDI and Ethernet data. At the same time, the parsed video data is sent to the HI3531 chip via GPIO. According to the button switch on the adapter, the FPGA selects one of the 6 vehicles, selects the fiber optic data sent by it, and sends it to the portable display through the optoelectronic module. The FPGA also performs the relay forwarding function of the fiber optic data of the other fiber optic interface. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the integrated processing module of this application;

[0021] Figure 2 This is a schematic block diagram of the power supply board of this application;

[0022] Figure 3 This is a resource diagram of the XC7K325T-2FFG900 embodiment of this application;

[0023] Figure 4 This is a functional block diagram of the FPGA logic software in an embodiment of this application;

[0024] Figure 5 This is a block diagram of the architecture of embodiment P2010NXE2KHC in this application;

[0025] Figure 6 This is a block diagram of the Hi3531D architecture, as shown in the embodiment of this application.

[0026] Figure 7 This is a software functional block diagram of embodiment P2010 of this application;

[0027] Figure 8 This is a data flow diagram of an embodiment of this application, Hi3531;

[0028] Figure 9 This is a functional block diagram of the Hi3531 software in an embodiment of this application. Detailed Implementation

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0034] This application provides an optoelectronic conversion adapter that supports multi-channel data recording.

[0035] like Figure 1As shown, a photoelectric conversion adapter that supports multi-channel data acquisition is disclosed. The adapter is used to process fiber optic signals from multiple armored vehicles and network data signals from one command vehicle. The adapter includes an integrated processing board for Ethernet communication, video selection, video decoding, and video encoding. The integrated processing board includes a CPU, an FPGA, and a video processing chip.

[0036] The CPU is equipped with a first gigabit Ethernet interface and a second gigabit Ethernet interface. The first gigabit Ethernet interface is connected to the command vehicle for data transmission, and the second gigabit Ethernet interface is connected to the ground equipment detector for data transmission and reception. The FPGA is equipped with multiple first optoelectronic modules to collect fiber optic signals from multiple external vehicles. The first optoelectronic modules are connected to the GTX interface on the FPGA. The FPGA is connected to the CPU via a PCIe bus. The FPGA is equipped with a video output selection module to realize the output video selection function. The video processing chip is connected to the FPGA via a general-purpose input / output GPIO and is connected to the display screen via an HDMI cable.

[0037] The CPU performs Ethernet communication, BIT information reading and diagnosis, and debugging functions. Based on the instructions sent by the FPGA, it distributes Ethernet data. The FPGA parses the multi-channel fiber optic data input from the outside and sends the parsed video data to the video processing chip via GPIO. The video output selection module selects one or more external fiber optic signals to be output. After receiving the instructions from the video output selection module, the video processing chip completes the windowing, overlay, and selection of the video signals. The FPGA determines the commands in the parsed data and communicates the Ethernet data packets with the external device through a specific Gigabit Ethernet interface.

[0038] The FPGA is connected to a portable display controller via a second optoelectronic module. The video output selection module sends fiber optic data from one of the vehicles to the portable display controller via the second optoelectronic module. At the same time, the portable display controller sends the fiber optic data received to the vehicle corresponding to the data source.

[0039] The FPGA is equipped with indicator lights corresponding to each fiber optic signal. The video output selection module illuminates the indicator light corresponding to the fiber optic signal sent to the portable display controller, while the other indicator lights remain off.

[0040] In the HDMI output to the display screen, the upper left corner shows the information of the tank currently in the picture, as well as the information of the tank that the fiber optic signal is currently forwarding to the portable display controller.

[0041] The FPGA connects to seven fiber optic signals. The video processing chip is a Hisilicon SOC. The adapter also includes a power module and buttons; the power module supplies power to the adapter, and the buttons control the video output selection. Figure 2 As shown, the power module adopts a mature DC module. The power board receives the 24V DC working power provided by the vehicle power system and converts it into the working power of each SRU in the display. It mainly consists of protection circuit, power filtering circuit, front-end voltage regulation circuit, DC / DC conversion circuit and power button control circuit, etc., and outputs 24V DC 1.3A DC power, which can meet the power requirements of the photoelectric conversion adapter.

[0042] Employing a CPU+FPGA+HiSilicon SOC architecture, its main function is to parse multiple externally input fiber optic and Ethernet data streams, producing one HD-SDI video stream, one PAL video stream, and one Ethernet stream. The HD-SDI and PAL video streams are windowed and superimposed using the FPGA to output a single HDMI video signal (1920x1080P resolution @ 60Hz). Simultaneously, the parsed data packets are compressed and packaged into Ethernet packet format for data communication with external devices. It also performs relay forwarding of fiber optic data for selected fiber optic interface channels. The multi-channel data acquisition optoelectronic conversion adapter primarily implements fiber optic data parsing, forwarding, and video processing functions.

[0043] The integrated processing module processes the seven acquired video and network data channels according to the switching requirements and outputs the data to the monitor for display. Specifically, it implements the following functions:

[0044] a) It has the ability to communicate with external devices via 3 Gigabit Ethernet channels, one of which transmits data to the command vehicle, one of which transmits and receives data with the ground equipment detector, and the other is a backup.

[0045] b) It has fiber optic signal acquisition function with 7 external photoelectric conversion module (MWG6209) inputs, and supports hot-swapping;

[0046] c) Capable of separating 7 external fiber optic signals into data signals and video signals;

[0047] d) It has one HDMI output function with a resolution of 1920×1080P;

[0048] e) The 7 video signals obtained from the analysis can be switched using the button wheel, allowing you to select one or all 7 channels to be output via HDMI;

[0049] f) By using the button to cycle through the vehicle, the fiber optic signal of one of the 1 to 6 vehicles is forwarded to the portable display and control unit. At this time, the indicator light corresponding to that vehicle is always on, while the indicator lights of the other vehicles are always off. At the same time, the fiber optic signal of the portable display and control unit is forwarded to the designated vehicle.

[0050] g) In the output HDMI screen, the top left corner displays which vehicle the current screen belongs to and which vehicle's fiber optic signal is currently being forwarded to the portable display controller.

[0051] h) One-way 24V DC power supply function, and can also realize the power switch function through the button;

[0052] i) It has a working indicator light function;

[0053] j) It has BIT functionality.

[0054] In one embodiment, the FPGA used is a Xilinx XC7K325T-2FFG900. Its main features are as follows: a) 28nm process; b) 326,080 logic cells; c) 16,020Kb RAM; d) 10 PLLs; e) up to 500 I / O pins; f) one PCIe hard core interface; g) 16 GTX interfaces. See details for specific resources. Figure 3 As shown.

[0055] FPGA logic software design

[0056] like Figure 4 As shown, the functions implemented are as follows:

[0057] a) Implement 7 SRIO x1 interfaces with a tentative rate of 3.125Gbps for receiving PAL, HD-SDI video and network data;

[0058] b) Implement one SRIO x1 interface with a speed of 3.125Gbps for interconnection with a portable display;

[0059] c) Implement 7 BT656 interfaces for transmitting PAL or HD-SDI video data to HI3531 for processing;

[0060] d) Implement one PCIe x4@5Gbps EP interface for communication with the CPU;

[0061] e) Reserve one DDR3 controller interface for external 64-bit 2GB DDR3;

[0062] f) Implement video input functionality;

[0063] g) Implement the test color bar function;

[0064] h) Internship video selection and output function;

[0065] i) Implement the function of writing network data to CPU memory via DMA;

[0066] j) Implement the AXI2LB function to access the FPGA's internal registers; k) Implement the address decoding function;

[0067] l) Implement key scanning function;

[0068] m) Implements LED indicator function;

[0069] n) Implement FPGA online upgrade functionality;

[0070] o) Implement the interrupt management module functionality;

[0071] p) Implement clock allocation and reset management functions;

[0072] q) Implement watchdog functionality;

[0073] r) Implement the UART interface function to communicate with HI3531;

[0074] s) Implement the FPGA version register function.

[0075] Data flow control

[0076] Hi3531 video data

[0077] a) The FPGA receives external data through the SRIO interface;

[0078] b) The FPGA classifies and processes the data according to the SRIO data packet format;

[0079] c) The FPGA packages the video data in BT656 format and forwards it to the HI3531.

[0080] P2010 Network Data

[0081] a) The FPGA receives external data through the SRIO interface;

[0082] b) The FPGA classifies and processes the data according to the SRIO data packet format;

[0083] c) The FPGA DMAs the network data to different memory addresses according to the input channels; d) The FPGA completes the DMA or generates an interrupt notification to the software to process the data.

[0084] Portable display data

[0085] a) The FPGA receives external data through the SRIO interface;

[0086] b) The FPGA classifies and processes the data according to the SRIO data packet format;

[0087] c) The FPGA inputs and processes the video data;

[0088] d) 7-channel input video data and 1-channel input color bar gating video output;

[0089] e) Select to output the video to a portable monitor via the SRIO interface.

[0090] FPGA configuration resources

[0091] The main configuration resources of the FPGA are shown in Table 1.

[0092] Table 1 FPGA Configuration Resource Table

[0093]

[0094] In one embodiment, such as Figure 5 As shown, the CPU uses NXP's P2010NXE2KHC as the processor. Its main features are:

[0095] a) E500 core, 1GHz clock speed;

[0096] b) 45nm process;

[0097] c) Supports DDR2 SDRAM with ECC;

[0098] d) 4 SerDes, up to 3.125GHz, multiplexing between controllers, supports configuration as PCIe interface, SRIO interface and SGMII interface;

[0099] e) It has three 10 / 100 / 1000Mbps Ethernet ports;

[0100] f) Possesses eLBC, I 2 C, UART and general I / O interfaces, etc.

[0101] The following are the selection criteria for CPU peripheral memory chips:

[0102] The P2010NXE2KHC's DDR2 SDRAM uses DDR2 memory chips with a single chip capacity of 256MB × 8bit. Eight chips are connected in parallel to form a DDR2 SDRAM memory bank with a 64-bit bus width, totaling 2GB. The DDR3 chip used is Micron's MT47H256M8.

[0103] The boot FLASH uses a parallel port FLASH with a storage capacity of 512Kb.

[0104] Design a 128MB parallel port FLASH chip for program storage.

[0105] like Figure 6 As shown, the video processing chip uses Huawei HiSilicon's Hi3531DV100, whose main characteristics are:

[0106] a) ARM Cortex A9 dual-core processor, clock speed 1.4GHz;

[0107] b) Supports eight 8-bit video input interfaces, each of which supports one 1080P video stream;

[0108] c) Supports one HDMI 2.0 high-definition output interface, with a maximum output of 2840x2160@60fps;

[0109] d) Supports two 32-bit DDR3 SDRAM interfaces;

[0110] e) Supports peripheral interfaces such as Gigabit Ethernet, serial port, and SPI.

[0111] In one embodiment, the optoelectronic module uses Hongxin Optoelectronics' HUSC-6G10-31IL. Its main characteristics are:

[0112] a) Rate 6.25Gbps, 1310nm;

[0113] b) Single-mode fiber, transmission distance 10km;

[0114] c) Dual LC interfaces;

[0115] d) Compact structural design;

[0116] e) Vibration-resistant design.

[0117] In one embodiment, the adapter software primarily consists of FPGA logic software, P2010 software, and Hi3531 software. The FPGA logic software handles fiber optic data parsing and packetization, the P2010 software handles Ethernet communication and system control, and the Hi3531 software handles video selection, processing, switching, and display. The FPGA logic software is as described above.

[0118] like Figure 7 As shown, the P2010 software design is as follows:

[0119] Operating environment

[0120] a) Hardware platform: P2010

[0121] b) Operating System: VxWorks 6.9

[0122] Software configuration items

[0123] There are three software configuration items in P2010, as shown in Table 2.

[0124] Table 2P2010 Software Configuration Items

[0125]

[0126] Implement functions

[0127] a) U-boot (CSP2020): Completes the initialization of CPU, DDR, and FLASH, loads the OS into memory, jumps to the system entry point, and boots the VxWorks 6.9 operating system;

[0128] b) Initialize the network port and flash memory;

[0129] c) Electronic tag function;

[0130] d) Online dynamic OS updates;

[0131] e) Implement watchdog timer, bit information detection, and PCIe IPUART driver;

[0132] f) Parse and analyze the network data transmitted by the MWG6209G;

[0133] g) Implement serial communication protocol with HiSilicon to control HiSilicon status;

[0134] h) Read the FPGA version;

[0135] i) Supports IP serial port driver, FPGA online upgrade, LED indicator lights, and button scanning function. The Hi3531 software design is as follows:

[0136] Operating environment

[0137] a) Hardware platform: Hi3531

[0138] b) Operating System: Embedded Linux

[0139] Software configuration items

[0140] There are four software configuration items for the Hi3531, as shown in Table 3.

[0141] Table 3 Hi3531 Software Configuration Items

[0142]

[0143] like Figure 8 and Figure 9 As shown, the functions implemented are: a) initializing the CPU, DDR and basic peripherals, and booting the system; b) initializing the flash, network port and debug serial port.

[0144] c) Online dynamic OS updates;

[0145] d) Supports the "stop" command-line entry function;

[0146] e) Supports simultaneous input of 7 video streams on the BT656;

[0147] f) Supports BT656 video scaling, splicing, selection, and other modes; g) Supports 6-channel video encoding;

[0148] h) Supports 100 Mbps Ethernet communication;

[0149] i) Supports BIT information reporting;

[0150] j) Supports watchdog functionality;

[0151] k) Supports serial port program and p2010 communication.

[0152] 6.1.3.5 Functional Block Diagram

[0153] The Hi3531 software functional block diagram is as follows: Figure 9 As shown.

[0154] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A photoelectric conversion adapter supporting multi-channel data acquisition, characterized in that, The adapter is used to process fiber optic signals from multiple armored vehicles and network data signals from one command vehicle. The adapter includes an integrated processing board for Ethernet communication, video selection, video decoding, and video encoding. The integrated processing board includes a CPU, an FPGA, and a video processing chip. The CPU is equipped with a first gigabit Ethernet interface and a second gigabit Ethernet interface. The first gigabit Ethernet interface is connected to the command vehicle for data transmission, and the second gigabit Ethernet interface is connected to the ground equipment detector for data transmission and reception. The FPGA is equipped with multiple first optoelectronic modules to collect fiber optic signals from multiple external vehicles. The first optoelectronic modules are connected to the GTX interface on the FPGA. The FPGA is connected to the CPU via a PCIe bus. The FPGA is equipped with a video output selection module to realize the output video selection function. The video processing chip is connected to the FPGA via a general-purpose input / output GPIO and is connected to the display screen via an HDMI cable. The CPU performs Ethernet communication, BIT information reading and diagnosis, and debugging functions. According to the instructions sent by the FPGA, it distributes Ethernet data. The FPGA parses the multi-channel fiber optic data input from the outside and sends the parsed video data to the video processing chip through GPIO. The video output selection module selects one or more external fiber optic signals to be output. After receiving the instructions from the video output selection module, the video processing chip completes the windowing, overlay, and selection of the video signal. The FPGA determines the Ethernet data packet to communicate with the external device through the specific Gigabit Ethernet interface according to the commands in the parsed data. The FPGA is connected to the portable display controller via a second optoelectronic module. The video output selection module sends one of the fiber optic data channels to the portable display controller via the second optoelectronic module. At the same time, the fiber optic data received by the portable display controller is sent to the data source. The FPGA is equipped with an indicator light corresponding to each optical fiber signal. The video output selection module illuminates the indicator light corresponding to the optical fiber signal sent to the portable display controller, while the other indicator lights remain off. In the HDMI output to the display screen, the upper left corner displays the tank information of the current screen and the tank information of the current fiber optic signal forwarded to the portable display controller; The FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format. The FPGA then packages the video data in BT656 format and forwards it to the video processing chip.

2. The photoelectric conversion adapter supporting multi-channel data acquisition according to claim 1, characterized in that, The FPGA is connected to seven fiber optic signals.

3. The photoelectric conversion adapter supporting multi-channel data acquisition according to claim 1, characterized in that, The video processing chip is a Hisilicon SOC.

4. The photoelectric conversion adapter supporting multi-channel data acquisition according to claim 1, characterized in that, The FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format. The FPGA then DMAs the network data to different memory addresses according to the input channel. The FPGA generates an interrupt to notify the software to process the data when the DMA is completed or at a set time.

5. The photoelectric conversion adapter supporting multi-channel data acquisition according to claim 1, characterized in that, The FPGA receives external data through the SRIO interface. The FPGA classifies and processes the data according to the SRIO data packet format. The FPGA processes the input video data, selects one video output from multiple input video data and input color bars, and outputs the selected video to the portable display through the SRIO interface.

6. The photoelectric conversion adapter supporting multi-channel data acquisition according to claim 1, characterized in that, The adapter also includes a power module and a button. The power module supplies power to the adapter, and the button controls the video output selection.

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