High resolution array optoelectronic device and method of making same

Abstract

The application relates to the field of photoelectric devices, in particular to a high-resolution array photoelectric device and a preparation method thereof, which comprises the following steps: providing a substrate; forming a strip-shaped bottom electrode and an insulating layer in a transverse arrangement on the surface of the substrate; forming a lower carrier layer on the surface of a pixel point area of the bottom electrode; forming an active layer on the surface of the lower carrier layer; forming an upper carrier material layer, a top electrode material layer and a protective material layer on the surface of the active layer and the insulating layer; and patterning and etching the protective material layer, the top electrode material layer and the upper carrier material layer until the insulating layer is exposed. The vertical structure of the row and column electrodes improves the space utilization; after the upper carrier layer and the top electrode are deposited on the whole surface and are encapsulated by the protective layer, the upper carrier layer and the top electrode are etched, so that a solvent-sensitive photoelectric device with smaller pixel size and higher resolution can be prepared.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic devices, and in particular to a high-resolution array optoelectronic device and its fabrication method. Background Technology

[0002] Optoelectronic devices are the foundation for building optical communication systems and networks. The development, upgrading, and widespread application of high-speed optical transmission equipment, long-distance optical transmission equipment, and the most market-focused intelligent optical networks all depend on advancements in optoelectronic device technology and product upgrades. Therefore, people are constantly updating and upgrading optoelectronic devices.

[0003] Current organic array optoelectronic devices and perovskite array optoelectronic devices mostly adopt a horizontal arrangement, resulting in a high proportion of the electrode wiring area to the overall device area. This leads to a resolution of less than 100 ppi for these devices. Whether it is an LED or a photodetector, the ideal solution for these optoelectronic devices to achieve addressing functionality and high resolution is to use a vertical structure with intersecting rows and columns of electrodes. However, due to the incompatibility of the materials of many active layers with commercial photolithography technology, patterned top electrodes are fabricated using metal masks or 3D printing technology. These technologies still have drawbacks such as difficulty in alignment, difficulty in miniaturization, and long fabrication time, resulting in optoelectronic devices with large pixel sizes and low resolution. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a high-resolution array optoelectronic device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A method for fabricating a high-resolution array optoelectronic device, comprising:

[0006] Provide substrate;

[0007] A horizontally arranged strip-shaped bottom electrode is formed on the surface of the substrate, the bottom electrode including pixel areas and non-pixel areas;

[0008] An insulating layer is formed on the exposed substrate surface and the non-pixel area of ​​the bottom electrode, and the pixel area of ​​the bottom electrode is exposed.

[0009] A lower carrier layer is formed on the surface of the pixel region of the bottom electrode, and the thickness of the lower carrier layer is less than the thickness of the insulating layer;

[0010] An active layer is formed on the surface of the lower charge carrier layer;

[0011] An upper charge carrier material layer is formed on the surfaces of the active layer and the insulating layer;

[0012] A top electrode material layer is formed on the surface of the upper charge carrier material layer;

[0013] A protective material layer is formed on the surface of the top electrode material layer;

[0014] The protective material layer, top electrode material layer, and upper charge carrier material layer are patterned and etched until the insulating layer is exposed, forming a vertically arranged strip-shaped upper charge carrier layer, top electrode, and protective layer, and the intersection area of ​​the vertically arranged top electrode and the horizontally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

[0015] Optionally, the specific steps for forming an active layer on the surface of the lower charge carrier layer include: hydrophobically treating the surface of the insulating layer; and depositing an active material layer on the surface of the lower charge carrier layer by spin coating, wherein the hydrophilic lower charge carrier layer and the hydrophobic insulating layer achieve the deposition of the active material layer in the hydrophilic region and not in the hydrophobic region due to the difference in surface energy, thereby realizing the preparation of a patterned active layer.

[0016] Optionally, the hydrophobic treatment of the insulating layer surface specifically includes: forming a photoresist layer on the surface of the lower charge carrier layer; forming an oxide film on the insulating layer surface, and performing hydrophobic treatment on the exposed oxide film surface using self-assembled silane to obtain a hydrophobic layer, and then removing the photoresist layer; or when the insulating layer is an oxide insulating layer, performing hydrophobic treatment on the exposed insulating layer surface using self-assembled silane to obtain a hydrophobic layer.

[0017] Optionally, the active layer is made of either perovskite or organic active material, and the upper and lower carrier layers are made of NiO. X One of C60 and BCP.

[0018] Optionally, the protective layer is one of Parylene film, PMMA film, PI film, Al2O3 layer, and HfO2 layer.

[0019] Optionally, the specific steps for forming an active layer on the surface of the lower charge carrier layer include: forming an active layer on the surface of the lower charge carrier layer using one of the following processes: inkjet printing, nanoprinting, metal mask + vapor deposition, or directional transfer.

[0020] Optionally, forming transversely arranged strip-shaped bottom electrodes on the substrate surface specifically includes: forming a photolithographic pattern on the substrate surface using a photolithography process, then preparing the bottom electrode material using a thin film deposition process, and forming transversely arranged strip-shaped bottom electrodes after removing the resist.

[0021] Optionally, forming an insulating layer on the exposed substrate surface and the non-pixel area surface of the bottom electrode specifically includes:

[0022] Patterned photoresist is prepared by photolithography, and the patterned photoresist corresponds to the pixel area of ​​the bottom electrode. An insulating material layer is deposited using thin film deposition technology. After the photoresist is removed, an insulating layer is formed on the exposed substrate surface and the non-pixel area surface of the bottom electrode, and a via is formed in the pixel area of ​​the bottom electrode.

[0023] Alternatively, a patterned photoresist layer can be prepared using photolithography, with the photoresist layer serving as an insulating layer. The patterned photoresist layer exposes the pixel area of ​​the bottom electrode, forming a via.

[0024] Alternatively, an insulating material layer can be deposited on the exposed substrate surface and bottom electrode surface, and a patterned insulating layer can be achieved by photolithography and etching, i.e., through holes that fully expose the pixel area can be etched in the insulating layer.

[0025] The insulating layer is made of either an oxide insulating layer or a polymer insulating layer.

[0026] A high-resolution array optoelectronic device, characterized in that it comprises:

[0027] Substrate:

[0028] A strip-shaped bottom electrode and an insulating layer are arranged laterally on the surface of the substrate. The bottom electrode includes a pixel area and a non-pixel area. An insulating layer is formed on the substrate surface exposed by the bottom electrode and the surface of the non-pixel area of ​​the bottom electrode, and the pixel area of ​​the bottom electrode is exposed.

[0029] The lower charge carrier layer is located on the surface of the pixel region of the bottom electrode, and the thickness of the lower charge carrier layer is less than the thickness of the insulating layer;

[0030] An active layer located on the surface of the lower charge carrier layer;

[0031] A strip-shaped upper charge carrier layer, a top electrode, and a protective layer are stacked sequentially and arranged longitudinally on the surface of the active layer and part of the insulating layer. The intersection area of ​​the longitudinally arranged top electrode and the laterally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

[0032] In summary, the beneficial effects of the present invention are as follows:

[0033] 1. This invention improves the space utilization of optoelectronic devices by adopting a vertical structure with intersecting rows and columns of electrodes, compared to a horizontal arrangement. Furthermore, since many existing active layer materials are solution-sensitive and incompatible with commercial photolithography, it is impossible to pattern the active layer by patterning photoresist on the surface of the active layer, or to pattern the electrode layer using photoresist after forming the electrode layer on the surface of the active layer (because the electrode layer is thin, the organic solution of the photoresist will still affect the active layer). This results in insufficient etching precision, making it impossible to form a structure that can accommodate smaller pixel sizes and thus failing to improve the resolution of optoelectronic devices made of solvent-sensitive materials. This invention achieves compatibility between solvent-sensitive materials and photolithography technology by first forming an upper carrier material layer, a top electrode material layer, and a protective material layer on the surface of the active layer, and then uniformly performing photolithography etching to form a vertically arranged strip-shaped upper carrier layer, top electrode, and protective layer. Compared with the prior art that uses metal masks or printing technology to prepare patterned upper carrier layers and top electrodes, this invention has higher etching precision, can adapt to smaller pixel sizes, and improves the resolution of optoelectronic devices made of solvent-sensitive materials.

[0034] 2. By treating the surface of the insulating layer with hydrophobicity, the present invention can automatically achieve selective deposition of the active layer. This avoids the problem in the prior art where the active layer is formed using inkjet printing, nanoprinting, metal mask + vapor deposition, or directional transfer processes. Due to insufficient precision, the size of the final active layer is not easy to control and may be larger than the size of the pixel area of ​​the bottom electrode, resulting in a larger final pixel size and lower resolution of the optoelectronic device.

[0035] 3. By adjusting the materials of the lower carrier layer, active layer, and upper carrier layer, this invention can apply optoelectronic devices to different fields such as light emission and detection from ultraviolet to infrared. That is, it can fabricate optoelectronic devices with PIN, NIP, PN, or NP structures with high fabrication efficiency. Furthermore, since etching is performed after depositing the upper carrier layer, top electrode, and protective layer on the entire surface, there is no need to consider the material of the active layer, which can adapt to more application fields. Attached Figure Description

[0036] Figure 1 A top view of the bottom electrode deposition provided in an embodiment of the present invention;

[0037] Figure 2 A cross-sectional view of the bottom electrode deposition AA provided in an embodiment of the present invention;

[0038] Figure 3 A top view of insulating layer deposition provided in an embodiment of the present invention;

[0039] Figure 4 This is a cross-sectional view of the insulating layer deposition BB provided in an embodiment of the present invention;

[0040] Figure 5 This is a top view of the active material layer deposition provided in an embodiment of the present invention;

[0041] Figure 6 This is a cross-sectional view along the CC axis during the deposition of the active material layer, provided in an embodiment of the present invention.

[0042] Figure 7 This is a three-dimensional schematic diagram along the CC section during the deposition of the active material layer according to an embodiment of the present invention;

[0043] Figure 8 This is a three-dimensional schematic diagram of the array optoelectronic device before etching, provided in an embodiment of the present invention;

[0044] Figure 9 This is a top view of an array optoelectronic device provided in an embodiment of the present invention;

[0045] Figure 10 This is a three-dimensional schematic diagram of an array optoelectronic device provided in an embodiment of the present invention.

[0046] The labels for the attached figures are as follows:

[0047] 1. Substrate; 2. Bottom electrode; 3. Insulating layer; 4. Lower carrier layer; 5. Hydrophobic layer; 6. Active material layer; 7. Upper carrier layer; 8. Top electrode; 9. Protective layer. Detailed Implementation

[0048] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0049] See Figures 1-10 The present invention provides a high-resolution array optoelectronic device and its fabrication method, which is achieved through the following technical solution:

[0050] A method for fabricating a high-resolution array optoelectronic device, comprising:

[0051] Step S10: Provide a substrate and form transversely arranged strip-shaped bottom electrodes on the surface of the substrate, the bottom electrodes including pixel areas and non-pixel areas;

[0052] Step S20: An insulating layer is formed on the exposed substrate surface and the non-pixel area surface of the bottom electrode, and the pixel area of ​​the bottom electrode is exposed.

[0053] Step S30: A lower carrier layer is formed on the surface of the pixel region of the bottom electrode, the thickness of the lower carrier layer being less than the thickness of the insulating layer; an active layer is formed on the surface of the lower carrier layer.

[0054] Step S40: An upper charge carrier material layer is formed on the surface of the active layer and the insulating layer; a top electrode material layer is formed on the surface of the upper charge carrier material layer; a protective material layer is formed on the surface of the top electrode material layer.

[0055] Step S50: Pattern the protective material layer, top electrode material layer, and upper charge carrier material layer until the insulating layer is exposed, forming a vertically arranged strip-shaped upper charge carrier layer, top electrode, and protective layer, wherein the intersection area of ​​the vertically arranged top electrode and the horizontally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

[0056] Specifically, for step S10, please refer to... Figure 1 and Figure 2 A substrate 1 is provided, and horizontally arranged strip-shaped bottom electrodes 2 are formed on the surface of the substrate 1. The bottom electrodes 1 include pixel areas and non-pixel areas.

[0057] The substrate 1 can be a rigid substrate, such as a glass plate or a semiconductor insulating substrate, for example, a silicon substrate with a silicon oxide layer on its surface. Alternatively, the substrate can be a flexible substrate, such as a substrate derived from a polymer, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyetherimide (PEI), polyethersulfone (PES), polysulfone (PSF), polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyarylate (PAR), and polyamide-imide (PAI). Other resin materials include polycyclic olefin resins, acrylic resins, polystyrene, ABS, polyethylene, polypropylene, polyamide resins, polyvinyl chloride resins, polycarbonate resins, polyphenylene ether resins, and cellulose resins, etc.

[0058] A horizontally arranged strip-shaped bottom electrode 2 is formed on the surface of the substrate 1. The bottom electrode 1 includes pixel regions and non-pixel regions, wherein the pixel regions and non-pixel regions are arranged alternately. The area above the pixel regions is used to form a photoelectric structure consisting of a lower carrier layer, an active layer, and an upper carrier layer.

[0059] In this invention, the terms "horizontal arrangement" and "vertical arrangement" only indicate that the mapping positions of the bottom electrode and the top electrode are vertically arranged. Specifically, the bottom electrode can be arranged horizontally and the top electrode can be arranged vertically, or the bottom electrode can be arranged vertically and the top electrode can be arranged horizontally. No specific setting direction is limited.

[0060] In this embodiment, the materials of the bottom electrode and the top electrode are one of the known conductive metals such as Cu and Ag, or they can be organometallic polymer materials, oxide metal materials, graphene films, etc., wherein oxide metal materials are, for example, ITO materials.

[0061] Forming transversely arranged strip-shaped bottom electrodes on the substrate surface specifically includes: forming a photolithographic pattern on the substrate surface using a photolithography process, then preparing the bottom electrode material using a thin film deposition process, and finally forming transversely arranged strip-shaped bottom electrodes after removing the resist.

[0062] Please refer to step S20 for execution instructions. Figure 3 and Figure 4 An insulating layer 3 is formed on the exposed surface of the substrate 1 and the non-pixel area of ​​the bottom electrode 2, thereby exposing the pixel area of ​​the bottom electrode 2.

[0063] In this embodiment, forming an insulating layer on the exposed substrate surface and the non-pixel area of ​​the bottom electrode specifically includes: preparing patterned photoresist on the exposed substrate surface and the bottom electrode surface using a photolithography process, wherein the patterned photoresist corresponds to the pixel area of ​​the bottom electrode; depositing an insulating material layer using thin film deposition technology; and after removing the photoresist, forming an insulating layer on the exposed substrate surface and the non-pixel area of ​​the bottom electrode, and forming vias in the pixel area of ​​the bottom electrode.

[0064] In another embodiment, forming an insulating layer on the exposed substrate surface and the non-pixel region of the bottom electrode specifically includes: preparing a patterned photoresist layer on the exposed substrate surface and the bottom electrode surface using a photolithography process, wherein the photoresist layer serves as an insulating layer, and the patterned photoresist layer exposes the pixel region of the bottom electrode to form a via.

[0065] In another embodiment, forming an insulating layer on the exposed substrate surface and the non-pixel area of ​​the bottom electrode specifically includes: depositing an insulating material layer on the exposed substrate surface and the bottom electrode surface, and achieving a patterned insulating layer by photolithography and etching, that is, etching through holes that completely expose the pixel area within the insulating layer.

[0066] The insulating layer can be made of either an organic insulating layer or an oxide insulating layer. For example, an organic insulating layer can be made of photoresist, and an oxide insulating layer can be made of silicon oxide, aluminum oxide, titanium oxide, etc.

[0067] Please refer to the figure for step S30. Figure 5 , Figure 6 and Figure 7 A lower carrier layer 4 is formed on the surface of the pixel area of ​​the bottom electrode 1, and the thickness of the lower carrier layer 4 is less than the thickness of the insulating layer 3; an active layer 6 is formed on the surface of the lower carrier layer 4.

[0068] The specific process for forming the lower charge carrier layer 4 on the pixel area surface of the bottom electrode 1 includes: forming the lower charge carrier layer 4 inside the via on the pixel area surface of the bottom electrode 1 using one of the following processes: inkjet printing, nanoprinting, metal mask + vapor deposition, photoresist mask + vapor deposition, or directional transfer. The thickness of the lower charge carrier layer 4 is less than the thickness of the insulating layer 3, so that there is still space inside the via for filling active material to form an active layer.

[0069] In this embodiment, the active layer is made of either perovskite material or organic active material. The perovskite material can be MAPbI3, MAPbBr3, or the organic active material can be Alq3 (8-hydroxyquinoline aluminum), TBADN (2-tert-butyl-9,10-bis(2-naphthyl)anthracene), or the organic active material.

[0070] By adjusting the materials of the lower carrier layer, active layer, and upper carrier layer, this invention enables optoelectronic devices to be applied to different fields, from ultraviolet to infrared light emission and detection. It can fabricate optoelectronic devices with PIN, NIP, PN, or NP structures with high fabrication efficiency. Furthermore, since etching is performed after depositing the upper carrier layer, top electrode, and protective layer on the entire surface, there is no need to consider the material of the active layer, making it suitable for a wider range of applications.

[0071] Among them, the material of the lower carrier material layer is NiO. X The active material layer is made of MAPbI3 perovskite, and the upper carrier layer is a stacked structure of C60 and BCP (bromocresol violet). The corresponding optoelectronic device is a photodetector.

[0072] The material of the lower charge carrier layer is PEDOT:PSS, the material of the active material layer is MAPbBr3, and the material of the upper charge carrier layer is PC. 61 BM corresponds to another type of photoelectric detection device.

[0073] The material of the lower carrier layer is NPB (N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine), the material of the active material layer is doped Alq3, the material of the upper carrier layer is Alq3, and the corresponding optoelectronic device is a light-emitting device.

[0074] If the material of the lower carrier layer is Si, the material of the active material layer is PbS, and the upper carrier layer is TPBi, the corresponding optoelectronic device is another type of light-emitting device 2.

[0075] In this embodiment, the specific steps for forming the active layer 6 on the surface of the lower charge carrier layer 4 include: hydrophobically treating the surface of the insulating layer 3 to form a hydrophobic layer 5; and forming an active material layer on the surface of the hydrophobic layer 5 and the lower charge carrier layer 4 by spin coating. Since the lower charge carrier layer is hydrophilic and the hydrophobic layer on the surface of the insulating layer 3 is hydrophobic, the active material layer is deposited in the hydrophilic region and not deposited in the hydrophobic region due to the difference in surface energy. This allows the active material layer to be deposited only on the surface of the lower charge carrier layer 4 to form the active layer 6, thereby achieving the preparation of a patterned active layer.

[0076] The hydrophobic treatment of the insulating layer 3 specifically includes: forming a photoresist layer on the surface of the lower charge carrier layer 4; forming an oxide film on the surface of the insulating layer; and performing hydrophobic treatment on the exposed surface of the oxide film using a self-assembled silane to obtain a hydrophobic layer. Specifically, the hydrophobic treatment involves immersing the insulating layer in a self-assembled silane solution or using a gas phase to diffuse the self-assembled silane to the surface of the insulating layer for molecular self-assembly, followed by removal of the photoresist layer. Since 1H,1H,2H,2H-heptadecyltrimethoxysilane or octadecyltrichlorosilane can achieve hydrophobic treatment on the oxide film surface, when the insulating layer is a polymer insulating layer, an oxide film is formed on the surface of the insulating layer, and then hydrophobic treatment is performed on the surface of the oxide film using a self-assembled silane.

[0077] In other embodiments, when the insulating layer is an oxide insulating layer, a hydrophobic layer is obtained by directly applying a self-assembled silane to the exposed surface of the insulating layer.

[0078] In this embodiment of the invention, the self-assembled silane is 1H,1H,2H,2H-heptadecyltrimethoxysilane or octadecyltrichlorosilane. In other embodiments, the self-assembled silane may also be other materials suitable for self-assembly.

[0079] In this embodiment, the active layer is made of either perovskite or organic active material. Since the surface of the lower charge carrier layer is hydrophilic and the surface of the insulating layer 3 is hydrophobic, the active material layer is deposited in the hydrophilic region and not in the hydrophobic region due to the difference in surface energy. This allows the active material layer to be deposited only on the surface of the lower charge carrier layer 4 to form the active layer 6, thus achieving the preparation of a patterned active layer.

[0080] In other embodiments, an active layer can be formed on the surface of the lower carrier layer using one of the following processes: inkjet printing, nanoprinting, metal mask + vapor deposition, or directional transfer. However, due to the insufficient precision of existing inkjet printing, nanoprinting, metal mask + vapor deposition, or directional transfer processes, the size of the final active layer is difficult to control and may be larger than the size of the pixel area corresponding to the bottom electrode, resulting in a larger final pixel size and lower resolution of the optoelectronic device.

[0081] Please refer to step S40 for execution. Figure 8 An upper charge carrier material layer is formed on the surface of the active layer 6 and the insulating layer 3; a top electrode material layer is formed on the surface of the upper charge carrier material layer; and a protective material layer is formed on the surface of the top electrode material layer.

[0082] The material of the top electrode layer may or may not be the same as the material of the bottom electrode.

[0083] The protective material layer in this embodiment of the invention is a Parylene film. Since Parylene film is a polymer film material with very low oxygen permeability and water vapor permeability, it can effectively prevent the organic solution of photoresist from penetrating into the active layer without affecting the material properties of the active layer.

[0084] In other embodiments, the protective material layer may also be one of PMMA film, PI film, Al2O3 layer, or HfO2 layer.

[0085] Please refer to step S50 for execution. Figure 9 and Figure 10 The protective material layer, the top electrode material layer, and the upper charge carrier material layer are patterned and etched until the insulating layer is exposed, forming a vertically arranged strip-shaped upper charge carrier layer 7, a top electrode 8, and a protective layer 9, and the intersection area of ​​the vertically arranged top electrode and the horizontally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

[0086] In this embodiment, photoresist is formed on the surface of the protective material layer, the photoresist is patterned, and the protective material layer, the top electrode material layer, and the upper charge carrier material layer are etched until the insulating layer is exposed. Since existing commercial photolithography technologies can provide extremely small dimensions, the structure of this invention can utilize existing photolithography techniques, allowing the widths of the top and bottom electrodes to be very small, thereby significantly improving the resolution of optoelectronic devices.

[0087] This invention also provides a high-resolution array optoelectronic device, please refer to... Figure 10 ,include:

[0088] Substrate 1:

[0089] A strip-shaped bottom electrode 2 and an insulating layer 3 are arranged laterally on the surface of the substrate 1. The bottom electrode 2 includes a pixel area and a non-pixel area. An insulating layer 3 is formed on the surface of the substrate 1 exposed by the bottom electrode 2 and the surface of the non-pixel area of ​​the bottom electrode 2, and the pixel area of ​​the bottom electrode 2 is exposed.

[0090] The lower carrier layer 4 is located on the surface of the pixel area of ​​the bottom electrode 2, and the thickness of the lower carrier layer 4 is less than the thickness of the insulating layer 3.

[0091] The active layer 6 is located on the surface of the lower carrier layer 4;

[0092] A strip-shaped upper carrier layer 7, a top electrode 8, and a protective layer 9 are stacked sequentially and arranged longitudinally on the surface of the active layer 6 and part of the insulating layer 3. The intersection area of ​​the longitudinally arranged top electrode 8 and the laterally arranged bottom electrode 2 is located in the pixel area of ​​the bottom electrode.

[0093] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a high-resolution array optoelectronic device, characterized in that, include: Provide substrate; A horizontally arranged strip-shaped bottom electrode is formed on the surface of the substrate, the bottom electrode including pixel areas and non-pixel areas; An insulating layer is formed on the exposed substrate surface and the non-pixel area of ​​the bottom electrode, and the pixel area of ​​the bottom electrode is exposed. A lower carrier layer is formed on the surface of the pixel region of the bottom electrode, and the thickness of the lower carrier layer is less than the thickness of the insulating layer; An active layer is formed on the surface of the lower charge carrier layer; An upper charge carrier material layer is formed on the surfaces of the active layer and the insulating layer; A top electrode material layer is formed on the surface of the upper charge carrier material layer; A protective material layer is formed on the surface of the top electrode material layer; The protective material layer, top electrode material layer, and upper charge carrier material layer are patterned and etched until the insulating layer is exposed, forming a vertically arranged strip-shaped upper charge carrier layer, top electrode, and protective layer, and the intersection area of ​​the vertically arranged top electrode and the horizontally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

2. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The specific steps for forming an active layer on the surface of the lower charge carrier layer include: The surface of the insulating layer is treated with a hydrophobic coating; An active material layer is deposited on the surface of the lower charge carrier layer using a spin coating process. The hydrophilic lower charge carrier layer and the hydrophobic insulating layer have different surface energies, which allows the active material layer to be deposited in the hydrophilic region and not in the hydrophobic region, thus achieving the preparation of a patterned active layer.

3. The method for fabricating a high-resolution array optoelectronic device according to claim 2, characterized in that, The hydrophobic treatment of the surface of the insulating layer specifically includes: A photoresist layer is formed on the surface of the lower charge carrier layer; An oxide film is formed on the surface of the insulating layer, and a hydrophobic treatment is performed on the exposed surface of the oxide film using self-assembled silane to obtain a hydrophobic layer, and then the photoresist layer is removed. Alternatively, when the insulating layer is an oxide insulating layer, a hydrophobic layer is obtained by performing a hydrophobic treatment on the exposed surface of the insulating layer using self-assembled silane.

4. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The active layer is made of either perovskite or organic active material, and the upper and lower charge carrier layers are made of NiO. x One of C60 and BCP.

5. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The protective layer is one of the following: Parylene film, PMMA film, PI film, Al2O3 layer, and HfO2 layer.

6. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The specific steps for forming an active layer on the surface of the lower charge carrier layer include: An active layer is formed on the surface of the lower charge carrier layer using one of the following processes: inkjet printing, nanoprinting, metal mask + vapor deposition, or directional transfer.

7. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The formation of transversely arranged strip-shaped bottom electrodes on the substrate surface specifically includes: A photolithographic pattern is formed on the surface of the substrate using a photolithography process, and then a bottom electrode material is prepared using a thin film deposition process. After removing the resist, a horizontally arranged strip-shaped bottom electrode is formed.

8. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, Forming an insulating layer on the exposed substrate surface and the non-pixel area of ​​the bottom electrode specifically includes: Patterned photoresist is prepared by photolithography, and the patterned photoresist corresponds to the pixel area of ​​the bottom electrode. An insulating material layer is deposited using thin film deposition technology. After the photoresist is removed, an insulating layer is formed on the exposed substrate surface and the non-pixel area surface of the bottom electrode, and a via is formed in the pixel area of ​​the bottom electrode. Alternatively, a patterned photoresist layer can be prepared using photolithography, with the photoresist layer serving as an insulating layer. The patterned photoresist layer exposes the pixel area of ​​the bottom electrode, forming a via. Alternatively, an insulating material layer can be deposited on the exposed substrate surface and bottom electrode surface, and a patterned insulating layer can be achieved by photolithography and etching, i.e., through holes that fully expose the pixel area can be etched in the insulating layer.

9. The method for fabricating a high-resolution array optoelectronic device according to claim 1, characterized in that, The insulating layer is made of either an oxide insulating layer or a polymer insulating layer.

10. A high-resolution array optoelectronic device, fabricated using the fabrication method of a high-resolution array optoelectronic device as described in claim 1, characterized in that, include: Substrate; A strip-shaped bottom electrode and an insulating layer are arranged laterally on the surface of the substrate. The bottom electrode includes a pixel area and a non-pixel area. An insulating layer is formed on the substrate surface exposed by the bottom electrode and the surface of the non-pixel area of ​​the bottom electrode, and the pixel area of ​​the bottom electrode is exposed. The lower charge carrier layer is located on the surface of the pixel region of the bottom electrode, and the thickness of the lower charge carrier layer is less than the thickness of the insulating layer; An active layer located on the surface of the lower charge carrier layer; A strip-shaped upper charge carrier layer, a top electrode, and a protective layer are stacked sequentially and arranged longitudinally on the surface of the active layer and part of the insulating layer. The intersection area of ​​the longitudinally arranged top electrode and the laterally arranged bottom electrode is located in the pixel area of ​​the bottom electrode.

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