Pixel processing methods and graphics processors

Abstract

This application provides a pixel processing method, including: after rasterization of the current draw-call command, setting the value of a flag for a pixel region associated with the current draw-call according to the depth test mode of the current draw-call, indicating whether pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; executing the pixel shading and depth test of the current draw-call; and clearing the value of the flag for the associated pixel region to zero after the pixel shading and depth test of the current draw-call is completed. Based on the above method, when the current draw-call in a specific depth test mode affects the depth test of subsequent draw-calls, by setting a flag for a specific pixel region, the disabling of pixel shading and depth testing is constrained to the affected pixel region, while for the remaining pixel regions that are not disabled, subsequent draw-calls can continue to execute pixel shading and depth testing, thereby improving the coherence of draw-call command execution and minimizing the impact on GPU parallel computing capabilities.

Description

Technical Field

[0001] This application relates to the field of graphics processing unit (GPU) technology, and more particularly to pixel processing methods performed in a graphics processing unit. Background Technology

[0002] In current computer graphics systems, virtual 3D objects are rendered onto a 2D display screen by executing the graphics rendering pipeline in the graphics processing unit (GPU). Specifically, the GPU receives commands (such as draw-call commands) and / or data (including rendering states, such as the material, texture, shaders, etc. of the objects to be drawn) from, for example, the CPU, and receives vertex data from external system memory (not shown). Based on the commands, such as draw-call commands, it performs primitive rendering and finally generates the output image on the display screen.

[0003] When the GPU calls the Draw-Call command for rendering, due to the rendering order of objects, objects rendered later may be occluded by those rendered earlier. In the graphics rendering pipeline, after the rasterizer, a depth test is performed on the pixel data to cull occluded primitives or pixels that no longer need to be rendered. Generally, a draw-call command is configured with a corresponding depth test mode: for example, Early-Z test, Late-Z test, or Conservative-Z test. In most scenarios, depth testing can be performed before pixel shading; pixels that are not discarded then enter pixel shading for rendering. This is called Early-Z test. In some scenarios, such as when the depth value is affected by pixel shading, depth testing needs to be performed after pixel shading. This is called Late-Z test. In some cases, although the depth value is affected by pixel shading, it can be known in advance that the effect always changes in one direction. For example, the depth value after pixel shading will always be larger than the original value. In this case, an early-Z test can be performed before pixel shading, and a late-Z test can be performed after pixel shading. This is called a conservative-Z test.

[0004] In existing technologies, certain draw-calls in depth testing modes, such as Late-Z or Conservative-Z tests, can affect the depth testing of subsequent draw-calls. For example, for Late-Z or Conservative-Z test draw-calls, if these draw-calls have not yet completed the depth testing and depth buffer update (i.e., reads and writes to the depth buffer), subsequent draw-calls (e.g., Early-Z draw-calls) will pause their depth testing; otherwise, inconsistencies in the depth buffer will occur. This obviously degrades the continuity of draw-call execution, leading to a significant decrease in GPU performance. Summary of the Invention

[0005] This application provides a pixel processing method to at least address one of the aforementioned drawbacks in the prior art.

[0006] According to a first aspect of this application, a pixel processing method is provided, comprising: after rasterization of a current draw-call, setting a value of a marker for a pixel region associated with the current draw-call according to the depth test mode of the current draw-call, indicating whether pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; performing pixel shading and depth testing of the current draw-call; and after the pixel shading and depth testing of the current draw-call is completed, clearing the value of the marker for the associated pixel region to zero.

[0007] Based on the above method, when the current draw-call in a specific depth test mode will affect the depth test of subsequent draw-calls, a mark (PipeNeedDrain) is set for the pixel region associated with the current draw-call. This restricts the disabling of pixel shading and depth testing for subsequent draw-calls to the affected pixel region. For the remaining pixel regions that are not disabled, subsequent draw-calls can continue to perform pixel shading and depth testing, thereby improving the coherence of draw-call command execution and minimizing the impact on GPU parallel computing capabilities.

[0008] Optionally, if the depth test mode is an advance depth test, the method further includes: after the rasterization of the current draw-call, setting the value of a flag for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; wherein, performing the pixel shading and depth test of the current draw-call includes: performing an advance depth test of the current draw-call, and performing pixel shading of the current draw-call after the advance depth test passes and the corresponding depth buffer is updated.

[0009] Optionally, if the depth test mode is a conservative depth test, the method further includes: after the rasterization of the current draw-call, setting the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; wherein performing pixel shading and depth testing of the current draw-call includes: performing an early depth test of the current draw-call, performing pixel shading of the current draw-call after the early depth test passes, and performing a late depth test of the current draw-call after the pixel shading of the current draw-call.

[0010] Optionally, if the depth test is a post-depth depth test, the method further includes: after the rasterization of the current draw-call, setting the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; wherein performing pixel shading and depth testing of the current draw-call includes: performing pixel shading of the current draw-call, and performing post-depth depth testing of the current draw-call.

[0011] According to a second aspect of this application, a graphics processor is provided, including a memory for storing instructions, and a processing unit configured to perform any of the methods described above when executing instructions.

[0012] According to a third aspect of this application, a computer-readable storage medium is provided, wherein program code is stored therein, and when executed by a computer or processor, the program code implements any of the methods described above.

[0013] According to a fourth aspect of this application, a computer program product is provided, wherein the program code contained in the computer program product, when executed by a computer or processor, implements any of the methods described above.

[0014] According to a fifth aspect of this application, a graphics processing system is provided, comprising: a setting unit configured to, after rasterization of a current draw-call, set a value of a marker for a pixel region associated with the current draw-call according to a depth test mode of the current draw-call, indicating whether pixel shading and depth testing of subsequent draw-calls after the current draw-call is disabled for the associated pixel region, and clearing the value of the marker for the associated pixel region to zero after the pixel shading and depth testing of the current draw-call is completed; and a pixel processing unit configured to perform pixel shading and depth testing of the current draw-call.

[0015] Optionally, if the depth test mode is an advance depth test, then the setting unit is further configured to: after the rasterization of the current draw-call, set the value of a flag for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; the pixel processing unit is configured to: perform an advance depth test for the current draw-call, and after the advance depth test passes and the corresponding depth buffer is updated, perform pixel shading for the current draw-call.

[0016] Optionally, if the depth test mode is a conservative depth test, the setting unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform an early depth test for the current draw-call, perform pixel shading for the current draw-call after the early depth test passes, and perform a late depth test for the current draw-call after the pixel shading of the current draw-call.

[0017] Optionally, if the depth test is a post-depth depth test, the setting unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform pixel shading and post-depth depth testing for the current draw-call.

[0018] According to a sixth aspect of this application, a graphics processing system is provided, comprising: a control unit configured to: after rasterization of a current draw-call, set a value of a marker for a pixel region associated with the current draw-call according to a depth test mode of the current draw-call, indicating whether pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; and clear the value of the marker for the pixel region to zero after the depth test for the pixel region is completed; a pixel shader configured to: perform pixel shading for the current draw-call; a depth test unit configured to: perform depth testing for the current draw-call; and a marker buffer configured to: store the value of the marker for the associated pixel region.

[0019] Optionally, if the depth test mode is an advance depth test, the control unit is further configured to: after the rasterization of the current draw-call, set the value of a flag for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; the depth test unit includes an advance depth test unit configured to: perform an advance depth test for the current draw-call; the pixel shader is configured to: perform pixel shading for the current draw-call after the advance depth test passes and the corresponding depth buffer is updated.

[0020] Optionally, if the depth test mode is a conservative depth test, the control unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the depth test unit includes an early depth test unit and a late depth test unit, the early depth test unit is configured to: perform an early depth test for the current draw-call; the pixel shader is configured to: perform pixel shading for the current draw-call after the early depth test passes; the late depth test unit is configured to: perform a late depth test for the current draw-call after pixel shading of the current draw-call.

[0021] Optionally, if the depth test is a late-stage depth test, the control unit is further configured to: after the rasterization of the current draw-call, set the value of a flag for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the depth test unit includes a late-stage depth test unit, and the pixel shader is configured to: perform pixel shading for the current draw-call; the late-stage depth test unit is configured to perform a late-stage depth test.

[0022] Based on the method proposed in this application, when the current draw-call of a specific depth testing mode affects the depth testing of subsequent draw-calls, a flag is set for the affected pixel area. This restricts the disabling of pixel shading and depth testing for subsequent draw-calls to the affected pixel area. For the remaining pixel areas that are not disabled, subsequent draw-calls can continue to execute pixel shading and depth testing. Compared to the prior art, which requires waiting for the draw-call pipeline of the specific depth testing mode to be cleared or for the pixel shading and depth testing of the draw-call of the specific depth testing mode to be completed before the pixel shading and depth testing of subsequent draw-calls can be executed, this method improves the coherence of draw-call command execution and minimizes the impact on the GPU's parallel computing capabilities. Attached Figure Description

[0023] Figure 1 A schematic diagram of a computing device for implementing embodiments of this application.

[0024] Figure 2A schematic diagram of a GPU for implementing embodiments of this application.

[0025] Figure 3 for Figure 2 An example of a rendering pipeline implemented in a GPU.

[0026] Figure 4 An example of a rendering pipeline implemented in a GPU for carrying out the pixel processing method of the embodiments of this application.

[0027] Figure 5 A flowchart of a pixel processing method provided in an embodiment of this application.

[0028] Figure 6 A flowchart of the pixel processing method provided in the embodiments of this application in Early-Z mode.

[0029] Figure 7 A flowchart of the pixel processing method provided in the embodiment of this application in the conservative depth test mode.

[0030] Figure 8 This is a flowchart of the pixel processing method provided in the embodiments of this application in Late-Z mode.

[0031] Figure 9 This is a schematic diagram of an implementation scenario for the pixel processing method provided in the embodiments of this application.

[0032] Figure 10 This is a schematic diagram of a graphics processing system that implements the pixel processing method of the embodiments of this application. Detailed Implementation

[0033] The technical solutions provided in this application will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the system structures and application scenarios provided in the embodiments of this application are mainly for explaining some possible implementations of the technical solutions of this application, and should not be construed as the sole limitation on the technical solutions of this application. Those skilled in the art will understand that the technical solutions provided in this application will still be applicable as systems change and newer application scenarios emerge.

[0034] The terms "first," "second," and "third," etc., used in the embodiments and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to indicate non-exclusive inclusion, for example, including a series of steps or units. A method, system, product, or apparatus is not necessarily limited to those steps or units literally listed, but may include other steps or units not literally listed or inherent to these processes, methods, products, or apparatuses.

[0035] It should be understood that in this application, the number of the steps does not imply the order of execution. The execution order of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0036] The methods provided in this application are implemented, for example, in a computing device. The overall architecture of the computing device is as follows: Figure 1 As shown.

[0037] Reference Figure 1 The document illustrates a computing device 100 configured to implement one or more aspects of the embodiments of this application. The computing device 100 may include, but is not limited to, personal computers, such as laptops, desktop computers, tablet computing devices, etc., and may also be wireless devices, mobile phones (including smartphones), personal digital assistants (PDAs), video game consoles (including video displays, mobile video game devices, mobile video conferencing units), set-top boxes, in-vehicle intelligent systems, smart wearable devices, e-book readers, fixed or mobile media players, etc.

[0038] exist Figure 1 In one embodiment, the computing device 100 may include a central processing unit (CPU) 102 and system memory 101 communicating via, for example, a memory bridge 104. The memory bridge 104 may be, for example, a northbridge chip, connected to an I / O (input / output) bridge 105 via a bus or other communication path 112 (e.g., a HyperTransport link). The I / O bridge 105 may be, for example, a southbridge chip, receiving user input from one or more input devices 107 (e.g., a keyboard, mouse, trackball, touchscreen of a display device, or other types of input devices) and forwarding the user input to the CPU 102 via the communication path 112 and the memory bridge 104. A graphics processing unit (GPU) 103 communicates with the CPU 102 and system memory 101 via a bus or other communication path 112 (e.g., PCI Express, Accelerated Graphics Port, or HyperTransport link) coupled to the memory bridge 104. In one embodiment, the GPU 103 may perform graphics processing operations to generate pixel data and transmit the pixel data to the display device 110.

[0039] System disk 106 is also connected to I / O bridge 105. Computing device 100 may also include other components (not explicitly shown), such as USB or other port connections, CD drives, DVD drives, and similar components, which may also be connected to I / O bridge 105. Figure 1The communication paths for interconnecting various components can be implemented using any suitable protocol, such as PCI (Peripheral Component Interconnect), PCI-Express, AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol, and connections between different devices can use different protocols known in the art.

[0040] Figure 1 The configuration of the computing device 100 shown is merely an example, and those skilled in the art will understand that other configurations of the computing device 100 may exist. It should be understood that variations and modifications are possible. The connection topology, such as the number and arrangement of bridges, the number of CPUs, and the number of GPUs, can be modified as needed. In other embodiments, the computing device 100 may include two or more CPUs 102 and two or more GPUs 103.

[0041] In one embodiment, GPU 103 includes circuitry optimized for graphics and video processing, including, for example, video output circuitry. GPU 103 can be integrated with one or more other components, such as memory bridge 104, CPU 102, and I / O bridge 105, to form a system-on-a-chip (SoC).

[0042] Figure 2 The methods that can be implemented according to the embodiments of this application are shown. Figure 1 A schematic block diagram of a GPU 103 in a computing device 100. In one embodiment, the GPU 103 includes circuitry for graphics processing and video processing.

[0043] GPU 103 may include a processing core array 203, which may include multiple processing cores 2031-2036. Figure 4 As an example, only six processing cores are shown; those skilled in the art will understand that the number of processing cores can vary. The shown processing cores can be, for example, general-purpose processing cores or fixed-function processing cores. Based on multiple general-purpose processing cores in the processing core array 203, the GPU 103 is capable of concurrently executing a large number of program tasks or computational tasks. Each general-purpose processing core can be programmed to perform processing tasks related to various programs, including but not limited to graphics rendering operations. Fixed-function processing cores may contain hardware hardwired to perform certain specific functions.

[0044] In this embodiment, the graphics memory 204 may be part of the GPU 103. The GPU 103 can read data from or write data to the graphics memory 204. That is, the GPU 103 can use local storage devices instead of external memory to store data. In some cases, the GPU 103 may also read and write data via a bus, such as communication path 112, using system memory 101. The graphics memory 204 may include one or more volatile or non-volatile memories or storage devices, such as random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data storage devices, or optical storage devices.

[0045] GPU 103 can be configured to perform various operations such as receiving graphics data from CPU 102 and / or system memory 101 via memory bridge 104 and bus, such as communication path 112, and then processing the graphics data to generate pixel data, interacting with local graphics memory 204 to store and update pixel data, and transferring pixel data to display device 110.

[0046] In operation, CPU 102 is the main processor of computing device 100, which controls and coordinates the operation of other components. Specifically, CPU 102 issues commands to control the operation of GPU 103. In some embodiments, CPU 102 writes a command stream for controlling GPU 103 to, for example, system memory 101, graphics memory 204, or other storage locations accessible to both CPU 102 and GPU 103. GPU 103 reads the command stream and can execute the commands asynchronously relative to the operation of CPU 102.

[0047] like Figure 2 As shown, GPU 103 includes an I / O (input / output) unit 202 that communicates with other components of computing device 100 via a communication path 112 connected to memory bridge 104. The connections of GPU 103 to other components of computing device 100 may also vary. In some embodiments, GPU 103 may be implemented as an external card, for example, it may be inserted into an expansion slot of computing device 100.

[0048] In one embodiment, the communication path 112 connecting GPU 103 to memory bridge 104 may be a PCI-EXPRESS link. As is known in the art, a dedicated channel is allocated to GPU 103 in a PCI-EXPRESS link. I / O unit 202 receives all incoming data packets (or other signals) from communication path 112, directs the incoming data packets to the appropriate components of GPU 103, or transmits data packets (or other signals) via communication path 112 to components outside GPU 103. For example, I / O unit 202 may direct commands related to processing tasks to scheduler 201, and commands related to memory operations (e.g., reads or writes to graphics memory 204) to graphics memory 204.

[0049] The processing core array 203 can receive processing tasks to be executed from the scheduler 201. The scheduler 201 can independently schedule tasks for execution by the resources of the GPU 103 (e.g., one or more processing cores of the processing core array 203). In one embodiment, the scheduler 201 may be a hardware processor. Figure 2 In the illustrated embodiment, scheduler 201 may be included within GPU 103. In other embodiments, scheduler 201 may also be a separate unit from CPU 102 and GPU 103. Scheduler 201 may also be configured to receive streams of commands and / or operations from any processor.

[0050] During operation, CPU 102 utilizes... Figure 1 The GPU driver contained in system memory 101 can send a command stream containing a series of operations to be executed by GPU 103 to scheduler 201. Scheduler 201 can receive the operation flow including the command stream through I / O unit 202 and can process the operations in the command stream sequentially based on the order of operations in the command stream, and can schedule the operations in the command stream for execution by one or more processing cores in processing core array 230.

[0051] In practice, each general-purpose processing core can be programmed to perform processing tasks associated with various programs, including but not limited to various operations in the graphics rendering pipeline (e.g., vertex shader and / or pixel shader programs, etc.).

[0052] Figure 3 An example of a graphics rendering pipeline implemented by GPU 103 is shown.

[0053] It should be noted that the graphics rendering pipeline is a logical function formed by cascading the processing cores (such as general-purpose processing cores and / or fixed-function processing cores) included in the processing core array. The scheduler 201, graphics memory 204, I / O unit 202, etc., included in the GPU 103 are peripheral circuits or devices that implement the logical functions of the rendering pipeline. For example, the graphics rendering pipeline typically includes programmable modules and fixed-function modules. The programmable modules are executed by general-purpose processing cores, and the fixed-function modules are implemented by corresponding fixed-function processing cores.

[0054] like Figure 3 As shown, for example, the rendering pipeline of GPU 103 includes an input assembler (IA), a vertex shader (VS), a primitive assembler (PA), a rasterizer, an early-Z test unit, a pixel shader, a late-Z test unit, and an output unit.

[0055] The rendering pipeline described above is merely an example and is not limited to the description herein. A rendering pipeline may also contain other units or modules. The logical order of these units or modules within the rendering pipeline is also not limited to... Figure 3 The examples in the text are not fixed, but can be varied as needed.

[0056] The aforementioned units or modules can be implemented in a separately designed fixed-function processor within the GPU 103, or by executing specific programs within the processing cores of the GPU 103. For example, the vertex shader can be implemented in a separately designed fixed-function processor within the GPU 103, or by executing shader programs within the processing cores of the GPU 103. Similarly, the input assembler can also be implemented in a separately designed fixed-function processor within the GPU 103, or by executing specific programs within the processing cores of the GPU 103.

[0057] In addition, such as Figure 3 The device also includes a vertex buffer (VB) for receiving vertex data from system memory 101 and transferring the vertex data to the input assembler. Generally, the vertex buffer is stored in graphics memory 204 on the GPU 103. A cache (not shown) may also be located between graphics memory 204 and the processing core array 203 in the GPU 103. The vertex buffer may also be stored in the cache or other storage areas accessible to the processing cores (2031-2036). A depth buffer (DB) is also present, which may be stored in, for example... Figure 2 The graphics memory 204 shown may also be stored in a cache (not shown) or other memory areas accessible to the processing core.

[0058] During the execution of the rendering pipeline, the GPU 103 receives commands (e.g., draw-call commands) and / or data (including rendering states, such as the material, texture, shader program, etc. of the objects being drawn) from, for example, the CPU 102, and receives vertex data from external system memory 101. It then performs primitive rendering according to the commands (e.g., draw-call commands) and finally generates the output image on the display screen.

[0059] Specifically, the Input Assembler (IA) receives vertex data (vertex coordinates and indices) from the vertex buffer and combines it into geometric primitives (e.g., triangles, lines, etc.).

[0060] Next, the vertex shader determines the vertex attributes (lighting, color, etc.) and provides the shaded vertex data to the primitive assembler. The primitive assembler generates primitives through operations such as clipping, perspective splitting, and viewport transformation. Then, the rasterizer uses the primitives generated by the primitive assembler (PA) to produce pixels on the screen representing the corresponding primitives. The pixel shader determines the color of each pixel by executing pixel shader instructions.

[0061] When the GPU 103 calls the Draw-Call command for rendering, due to the rendering order of objects, objects rendered later may be occluded by objects rendered earlier. In the graphics rendering pipeline, after the rasterizer, a depth test is performed on the pixel data to cull occluded primitives or pixels that no longer need to be rendered.

[0062] In the depth buffer, each pixel stores its corresponding depth value. During depth testing, the pixel's depth value is compared with the current depth value in the depth buffer. If it is greater than or equal to the depth value in the depth buffer, the pixel is considered occluded and is therefore discarded; otherwise, the pixel's corresponding depth value is written to the depth buffer to update the depth value in the depth buffer.

[0063] Generally, a draw-call command is configured with a corresponding depth test mode: for example, Early-Z test, Late-Z test, or Conservative-Z test. Early-Z and Late-Z tests are performed in the Early-Z test unit and Late-Z test unit, respectively. During the corresponding depth test, a reference value is read from the depth buffer for the depth test. If the test passes, the depth value of the passed pixel is written to the depth buffer to update it. Conservative-Z tests involve both Early-Z and Late-Z tests, which are performed in... Figure 3 The test was completed in the Early-Z test unit and Late-Z test unit shown.

[0064] The above descriptions of the functions of each unit or module in the rendering pipeline are exemplary and not restrictive.

[0065] The pixel processing method of this application aims to solve the problem of discontinuous draw-call in the prior art by improving the method, thereby improving the performance of computer graphics processing system.

[0066] The pixel processing method proposed in this application can be applied, for example, to the rendering process of a computer graphics processing system. In particular, the pixel processing method of this application can be applied, for example, to the pixel shading and depth testing stages after rasterization in the rendering pipeline, to improve the problem of discontinuity in draw-calls during the pixel processing stages (e.g., including pixel shading and depth testing).

[0067] The following reference Figure 4 and Figure 5 The pixel processing method provided in the embodiments of this application is described in detail.

[0068] Figure 4 This is a schematic diagram of a rendering pipeline in a GPU 103 implementing the pixel processing method of this application. Figure 3 The difference in the rendering pipeline is that, Figure 4 In this configuration, a control unit and a tag buffer are set up. The control unit can be a separate hardware unit within the GPU 103, or it can be a module implemented by executing computer programs within the processing core of the GPU 103. The tag buffer can be stored separately on the GPU 103's graphics memory 204.

[0069] like Figure 5 As shown, in step S10, after the rasterization of the current draw-call, the control unit reads the marker buffer to determine whether the value of the marker PipeNeedDrain corresponding to the pixel region associated with the current draw-call is 0. If so, it indicates that the pixel shading and depth test of the current draw-call can be performed, that is, the current draw-call can enter the next stage of the rendering pipeline. Here, the depth test mode includes, but is not limited to, Early-Z test, conservative depth test, or Late-Z test.

[0070] Next, in step S11, the control unit sets the value of the PipeNeedDrain flag for the associated pixel region based on the depth test mode of the current draw-call. This controls whether subsequent draw-calls following the current draw-call can perform pixel shading and depth testing on that pixel region. For example, the control unit writes the set flag for the pixel region associated with the current draw-call into a flag buffer to control whether subsequent draw-calls following the current draw-call can perform pixel shading and depth buffering on that pixel region.

[0071] If the current draw-call's depth test mode is Early-Z test mode, then for its associated pixel region, the previous PipeNeedDrain flag is kept at 0, indicating that subsequent draw-call pixel shading and depth tests can continue to be performed for that pixel region.

[0072] If the current draw-call's depth test mode is conservative depth test or Late-Z test mode, then the PipeNeedDrain flag for its associated pixel region should be set to 1. This indicates that for that pixel region, subsequent draw-calls after the current draw-call cannot perform pixel shading and depth testing until the PipeNeedDrain flag for that pixel region is cleared to zero.

[0073] Next, in step S12, for the pixel region, the pixel shading and depth test of the current draw-call are performed.

[0074] Next, in step S13, after the pixel shading and depth test of the current draw-call is completed, the control unit clears the mark PipeNeedDrain corresponding to the pixel area to zero, that is, the pixel shading and depth test of subsequent draw-calls can continue to be performed for the pixel area.

[0075] Preferably, if the depth test mode of the subsequent draw-call is Late-Z test, then for the pixel region associated with the current draw-call, even if the PipeNeedDrain flag is 1, the subsequent draw-call can continue to perform pixel shading and depth testing without waiting for the PipeNeedDrain flag corresponding to the pixel region to be cleared to zero.

[0076] The following reference Figure 6-8 Describe for respectively Figure 5The specific processes for the current draw-call depth testing modes in the pixel processing methods are Early-Z testing, conservative depth testing, and Late-Z testing.

[0077] Figure 6 This is for the current draw-call depth testing mode, which is Early-Z testing.

[0078] For example, as shown in step S110, after the current draw-call is rasterized, the control unit reads the marker buffer to determine whether the value of the marker PipeNeedDrain for the pixel region associated with the current draw-call is 0. If it is, it indicates that the pixel shading and depth test for the current draw-call can be performed, meaning that the current draw-call can proceed to the next stage of the rendering pipeline.

[0079] Next, the control unit resets the value of the PipeNeedDrain marker for the pixel region associated with the current draw-call according to the current draw-call's depth test mode. If the current draw-call's depth test mode is Early-Z test, then, as shown in step S111, the value of the PipeNeedDrain marker for the pixel region associated with the current draw-call is kept at 0, indicating that for this pixel region, pixel shading and depth testing of subsequent draw-calls can continue.

[0080] Next, as shown in step S112, the depth test of the current draw-call, namely the Early-Z test, is performed.

[0081] If the Early-Z test fails, the primitives of the current draw-call are discarded. If the Early-Z test of the current draw-call passes, and the corresponding depth buffer is updated, pixel shading of the current draw-call is performed as shown in step S113.

[0082] After the pixel coloring of the current draw-call is completed, as shown in step S114, the control unit clears the value of the PipeNeedDrain marker for that pixel area to zero.

[0083] Figure 7 This is aimed at situations where the current draw-call depth testing mode is a conservative depth testing method.

[0084] In step S120, after the current draw-call is rasterized, the control unit reads the marker buffer to determine whether the value of the marker PipeNeedDrain for the pixel region associated with the current draw-call is 0. If it is, it indicates that the pixel shading and depth test for the current draw-call can be performed, meaning the current draw-call can proceed to the next stage of the rendering pipeline.

[0085] Next, the control unit resets the value of the PipeNeedDrain flag for the pixel region associated with the current draw-call according to the depth test mode of the current draw-call. This resets the value of the PipeNeedDrain flag for the pixel region associated with the current draw-call. This reset controls whether subsequent draw-calls can perform pixel shading and depth testing on the pixel region associated with the current draw-call.

[0086] Specifically, as shown in step S121, if the depth test mode of the current draw-call is conservative-Z mode, then the value of the PipeNeedDrain flag associated with the current draw-call is reset to 1, that is, for this pixel region, the pixel shading and depth test of subsequent draw-calls after the current draw-call cannot be performed, and only the pixel shading and depth test of the current draw-call can be performed.

[0087] Then, as shown in step S122, perform the Early-Z test for the current draw-call.

[0088] After the Early-Z test of the current draw-call passes, as shown in step S123, pixel shading of the current draw-call is executed. Here, since the current draw-call's depth test mode is a conservative depth test, which will perform a Late-Z test later, the depth buffer is not updated immediately after the Early-Z test of the current draw-call passes. Instead, the depth buffer is updated after the Late-Z test passes.

[0089] After pixel shading in the current draw-call, perform the Late-Z test for the current draw-call. After the Late-Z test passes and the depth buffer is updated, as shown in step S124, clear the PipeNeedDrain flag of the associated pixel region, meaning that for that pixel region, pixel shading and depth tests for subsequent draw-calls can continue to be performed.

[0090] Similarly, preferably, if the depth test mode of the subsequent draw-call is Late-Z test, then for the pixel region associated with the current draw-call, the subsequent draw-call can directly continue to perform pixel shading and Late-Z test without waiting for the corresponding PipeNeedDrain marker of the pixel region to be cleared.

[0091] Figure 8 This is for the current draw-call depth testing mode, which is Late-Z testing.

[0092] In step S130, after the rasterization of the current draw-call, the control unit reads the marker buffer to determine whether the value of the marker PipeNeedDrain for the pixel region associated with the current draw-call is 0. If it is, it indicates that the pixel shading and depth test of the current draw-call can be performed, meaning that the current draw-call can proceed to the next stage of the rendering pipeline.

[0093] Next, the control unit resets the value of the PipeNeedDrain flag for the pixel region associated with the current draw-call according to the depth test mode of the current draw-call. This resets the value of the PipeNeedDrain flag for the pixel region associated with the current draw-call. This reset controls whether subsequent draw-calls can perform pixel shading and depth testing on the pixel region associated with the current draw-call.

[0094] Specifically, as shown in step S131, if the depth test mode of the current draw-call is Late-Z mode, then the value of the PipeNeedDrain flag associated with the current draw-call is reset to 1, that is, for this pixel region, the pixel shading and depth test of subsequent draw-calls after the current draw-call cannot be performed.

[0095] Next, as shown in step S132, pixel shading for the current draw-call is performed; after pixel shading, its Late-Z test is performed. After the Late-Z test passes and the corresponding depth buffer is updated, as shown in step S133, the control unit clears the PipeNeedDrain marker for the corresponding pixel region to zero.

[0096] The following reference Figure 9 A specific application scenario of an embodiment of the present invention will be described in detail.

[0097] like Figure 9As shown, the screen is divided into 16 pixel regions t0 to t15. In the current rendering scene, six draw-call commands are executed, in the order of rendering d1 to d6. The depth test mode for d3 and d4 is late-Z mode, while the remaining d1-d2 and d5-d6 are early-Z mode.

[0098] Here, the division of pixel regions is illustrative; the screen can be divided into more or fewer pixel regions.

[0099] Initially, in the marker buffer, a marker, such as PipeNeedDrain, is set to an initial value of 0 for each pixel region. This means that each pixel region can perform pixel shading and depth testing via draw-call. For example, as shown in diagrams (0-a) and (0-b), initially, the PipeNeedDrain value for all pixel regions (t0~t15) is 0. The PipeNeedDrain value for each pixel region is stored in, for example, a marker buffer, which can be allocated storage space in memory or cache.

[0100] The depth testing of draw-calls mentioned here includes, but is not limited to, Early-Z testing, conservative depth testing, or Late-Z testing. This depends on the specific depth testing mode for the draw-call.

[0101] After the current draw-call is rasterized, the value of the PipeNeedDrain flag for the pixel region associated with that draw-call is determined. If the value is 0, it indicates that pixel shading and depth testing for the current draw-call can be performed; if the value is 1, it indicates that pixel shading and depth testing are disabled. Pixel shading and depth testing for the current draw-call in that pixel region can only be performed when the value of the PipeNeedDrain flag for that pixel region is 0.

[0102] As shown in diagrams (1-a) and (1-b), after rasterization of the current draw-call (e.g., d1), if the PipeNeedDrain flag for the pixel region t0 associated with the current draw-call d1 is set to its initial value of 0, then pixel shading and depth testing of d1 can be executed normally. Since the depth testing mode of d1 is Early-Z testing, it has no impact on the depth testing of subsequent draw-calls. Therefore, the control unit keeps the PipeNeedDrain flag for the corresponding pixel region t0 at 0, indicating that for this pixel region t0, pixel shading and depth testing of subsequent draw-calls can continue. The same applies to the next draw-call d2, which is also in Early-Z mode, and will not be elaborated further.

[0103] As shown in diagrams (2-a) and (2-b), after rasterization of draw-call d3, the control unit reads the depth buffer to determine that the PipeNeedDrain flag for the corresponding pixel region t9 is 0, allowing the pixel shading and depth test of d3 to be executed normally. At this point, because its Late-Z test mode will affect the depth test of subsequent draw-calls, the PipeNeedDrain flag for the pixel region t9 corresponding to d3 is set to 1. The value of PipeNeedDrain 1 indicates that for this pixel region t9, at least pixel shading and depth tests for subsequent draw-calls after draw-call d3 are disabled. Only after the pixel shading and late-Z tests of d3 are completed, and the PipeNeedDrain flag for pixel region t9 is cleared to zero, can the pixel shading and depth test for subsequent draw-calls for pixel region t9 be executed.

[0104] Similarly, after rasterization of draw-call d4, the PipeNeedDrain flags for its associated pixel regions t12 to t15 are determined. Since the PipeNeedDrain flags for pixel regions t12 to t15 are all 0, the pixel shading and depth tests for d4 can be executed normally, meaning draw-call d4 enters the next stage of its rendering pipeline. Because its Late-Z test mode will affect the depth tests of subsequent draw-calls, the PipeNeedDrain flags for the current d4-associated pixel regions t12 to t15 are set to 1. This indicates that for pixel region t9, at least the pixel shading and depth tests for subsequent draw-calls after draw-call d4 are disabled, and only the pixel shading and depth tests for the current draw-call d4 can be executed. After the pixel shading of the current d4 is completed and the late-Z operation is performed, the flags for t12 to t15 are cleared to zero.

[0105] Next, as shown in diagrams (3-a) and (3-b), the object in draw-call d5 needs to cover pixel regions t6, t7, t12, and t13. After rasterization of d5, the PipeNeedDrain marker for each corresponding pixel region t6, t7, t12, and t13 is determined. For example, if the marker for regions t6 and t7 is 0, pixel shading and depth testing for d5 in regions t6 and t7 can be performed directly. For regions t12 and t13, since d4 sets the PipeNeedDrain marker for the associated pixel regions t12 to t15 to 1, Early-Z testing and pixel shading for d5 in regions t12 and t13 can only be performed after the PipeNeedDrain marker for these two regions is cleared to zero. For example, after the pixel coloring and late-Z operation of d4 are completed, and the flags of t12 to t15 are cleared to 0, the Early-Z test and pixel coloring of d5 for the t12 and t13 regions can be performed.

[0106] As shown in diagrams (4-a) and (4-b), the object of the current draw-call d6 needs to cover t8, t10, and t11, and the corresponding PipeNeedDrain flags are all 0. Therefore, the Early-Z test and pixel shading of the current draw-call d6 can be started directly.

[0107] In existing technologies, such as Figure 4In scenarios where d3 and d4 are in late-Z depth testing mode, depth testing for all subsequent draw-calls after d3 and d4 in the current frame cannot begin until the pixel shading and depth testing for d3 and d4 are completed. The technical solution of the above embodiments of this application sets a marker only for the pixel areas affected by d3 and d4 to indicate that pixel shading and depth testing for subsequent draw-calls is disabled until the markers for the pixel areas affected by d3 and d4 are cleared. The remaining pixel areas not affected by d3 and d4 can continue to perform pixel shading and depth testing for subsequent draw-calls, further improving the coherence and performance of draw-call execution.

[0108] Based on the method proposed in this application, when the current draw-call of a specific depth testing mode affects the depth testing of subsequent draw-calls, a flag is set for the affected pixel area, restricting the disabling of pixel shading and depth testing to the affected pixel area. For the remaining pixel areas that are not disabled, subsequent draw-calls can continue to execute pixel shading and depth testing. Compared to the prior art, which requires waiting for the pixel shading and depth testing of the current draw-call of the specific depth testing mode to be completed before the pixel shading and depth testing of subsequent draw-calls can be executed, this method improves the coherence and parallelism of draw-call command execution and minimizes the impact on the GPU's parallel computing capabilities.

[0109] The methods in the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer program codes or computer program instructions, which can be stored in memory. When the computer program instructions are loaded and executed on a computer or processor, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device.

[0110] The computer program code or computer program instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program code or computer program instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic cable, etc.) or wireless (e.g., infrared, radio, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid-state drive (SSD).

[0111] The methods of this application may include various other operations and / or variations of the operations shown. Similarly, the order of operations in the flowchart may be modified. It should be understood that not all operations in the flowchart are executable. In various embodiments, one or more operations of the method may be controlled or managed by software, firmware, hardware, or any combination thereof, but are not limited thereto. The method may include the processes of embodiments of this disclosure, which may be controlled or managed by a processor and / or electronic components under the control of computer- or computing device-readable and executable instructions (or code).

[0112] The following reference Figure 10 A detailed description is provided of a graphics processing system 120 that implements the pixel processing method of any of the embodiments of this application described above.

[0113] like Figure 10 As shown, the graphics processing system 120 includes: a determination unit 121, a pixel processing unit 122, and a setting unit 123.

[0114] Specifically, in implementing the method of one embodiment of this application, the setting unit 123 is configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call according to the depth test mode of the current draw-call, indicating whether to disable pixel shading and depth testing for subsequent draw-calls after the current draw-call for the associated pixel region, and clear the value of the marker of the associated pixel region to zero after the pixel shading and depth testing of the current draw-call is completed; the pixel processing unit 123 is configured to perform the pixel shading and depth testing of the current draw-call.

[0115] Furthermore, when implementing the method of this embodiment, if the depth test mode of the current draw-call is advance depth test, then the setting unit 123 is configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; the pixel processing unit 122 is configured to: perform advance depth testing of the current draw-call, and after the advance depth test passes and the corresponding depth buffer is updated, perform pixel shading of the current draw-call.

[0116] Furthermore, in implementing the method of this embodiment, if the depth test mode of the current draw-call is conservative depth test, then the setting unit 123 is configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform an early depth test of the current draw-call, perform pixel shading of the current draw-call after the early depth test passes, and perform a late depth test of the current draw-call after the pixel shading of the current draw-call.

[0117] Furthermore, when implementing the method of this embodiment, if the depth test of the current draw-call is a later depth test, then the setting unit 123 is configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform pixel shading and later depth testing of the current draw-call.

[0118] Furthermore, in implementing the method of this embodiment, the current draw-call is associated with multiple pixel regions. When performing pixel shading and depth testing of the current draw-call, the value of the flag for each pixel region is set according to the depth testing mode of the current draw-call, indicating whether pixel shading and depth testing of subsequent draw-calls is disabled for that pixel region; and after the pixel shading and depth testing of the current draw-call for each pixel region is completed, the value of the flag for that pixel region is cleared to zero.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A pixel processing method, characterized in that, include: After the rasterization of the current draw-call command, the value of the marker of the pixel region associated with the current draw-call is set according to the depth test mode of the current draw-call, indicating whether pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region. The depth test mode includes early depth test, late depth test or conservative depth test. Perform the pixel shading and depth test for the current draw-call; as well as After the pixel shading and depth test of the current draw-call is completed, the value of the marker for the associated pixel region is cleared to zero.

2. The pixel processing method as described in claim 1, characterized in that, The depth test mode is an advance depth test, and the method further includes: after the rasterization of the current draw-call, setting the value of a flag for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; The process of performing pixel shading and depth testing for the current draw-call includes: performing an advance depth test for the current draw-call; and performing pixel shading for the current draw-call after the advance depth test passes and the corresponding depth buffer is updated.

3. The pixel processing method as described in claim 1, characterized in that, If the depth test mode is a conservative depth test, the method further includes: after the rasterization of the current draw-call, setting the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; The process of performing pixel shading and depth testing for the current draw-call includes: performing an early depth test for the current draw-call; performing pixel shading for the current draw-call after the early depth test passes; and performing a late depth test for the current draw-call after the pixel shading of the current draw-call.

4. The pixel processing method as described in claim 1, characterized in that, If the depth test is a later depth test, the method further includes: after the rasterization of the current draw-call, setting the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; The execution of pixel shading and depth testing for the current draw-call includes: performing pixel shading and post-deep testing for the current draw-call.

5. A graphics processor, characterized in that, It includes a memory for storing instructions and a processing unit configured to perform the method as described in any one of claims 1-4 when executing instructions.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code that, when executed by a computer or processor, implements the method as described in any one of claims 1-4.

7. A computer program product, characterized in that, When the program code contained in the computer program product is executed by a computer or processor, it implements the method as described in any one of claims 1-4.

8. A graphics processing system, characterized in that, include: The setting unit is configured to, after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call according to the depth test mode of the current draw-call, indicating whether to disable pixel shading and depth testing for subsequent draw-calls after the current draw-call for the associated pixel region, and to clear the value of the marker of the associated pixel region to zero after the pixel shading and depth testing of the current draw-call is completed, wherein the depth test mode includes early depth testing, late depth testing, or conservative depth testing; A pixel processing unit is configured to perform pixel shading and depth testing for the current draw-call.

9. The graphics processing system as described in claim 8, characterized in that, The depth test mode is an advance depth test. The setting unit is further configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; the pixel processing unit is configured to: perform the advance depth test of the current draw-call, and after the advance depth test passes and the corresponding depth buffer is updated, perform pixel shading of the current draw-call.

10. The graphics processing system as described in claim 8, characterized in that, The depth test mode is a conservative depth test. The setting unit is further configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform an early depth test of the current draw-call, perform pixel shading of the current draw-call after the early depth test passes, and perform a late depth test of the current draw-call after the pixel shading of the current draw-call.

11. The graphics processing system as described in claim 8, characterized in that, The depth test is a post-depth depth test, and the setting unit is further configured to: after the rasterization of the current draw-call, set the value of the marker of the pixel region associated with the current draw-call, indicating that pixel shading and depth testing of subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the pixel processing unit is further configured to: perform pixel shading and post-depth depth testing of the current draw-call.

12. A graphics processing system, characterized in that, include: The control unit is configured to: after rasterization of the current draw-call, set the value of a marker for a pixel region associated with the current draw-call according to the depth test mode of the current draw-call, indicating whether pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; and after the depth test for the pixel region is completed, clear the value of the marker for the pixel region to zero, wherein the depth test mode includes early depth test, late depth test, or conservative depth test; A pixel shader configured to: perform pixel shading for the current draw-call; The depth testing unit is configured to: perform a depth test on the current draw-call; and A tag buffer, configured to store the tag values ​​of the associated pixel region.

13. The graphics processing system as described in claim 12, characterized in that, The deep testing mode is to perform deep testing in advance. The control unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for a pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are not disabled for the associated pixel region; The depth testing unit includes an advance depth testing unit, configured to: perform advance depth testing of the current draw-call; The pixel shader is configured to perform pixel shading of the current draw-call after the prior depth test passes and the corresponding depth buffer is updated.

14. The graphics processing system as described in claim 12, characterized in that, The depth testing mode is a conservative depth testing mode. The control unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for a pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; The depth testing unit includes an early depth testing unit and a late depth testing unit. The early depth testing unit is configured to: perform an early depth test on the current draw-call; The pixel shader is configured to: perform pixel shading of the current draw-call after the advance depth test passes; The late depth test unit is configured to perform a late depth test on the current draw-call after the pixel shading of the current draw-call.

15. The graphics processing system as described in claim 12, characterized in that, If the depth test is a late-stage depth test, then the control unit is further configured to: after the rasterization of the current draw-call, set the value of a marker for the pixel region associated with the current draw-call, indicating that pixel shading and depth testing for subsequent draw-calls after the current draw-call are disabled for the associated pixel region; the depth test unit includes a late-stage depth test unit, and the pixel shader is configured to: perform pixel shading of the current draw-call; the late-stage depth test unit is configured to perform a late-stage depth test.

Images