Resistive memory array

Abstract

A vertical resistive memory array is presented. The array includes a pillar electrode and a switch liner around the lateral perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switch liner. The juxtaposition of the switch liner, the pillar electrode, and each SC electrode forms a respective resistive switching cell (e.g., an OxRRAM cell). Vertical groups or banks of these cells can be connected in parallel and each share the same pillar electrode. Cells in a vertical bank of cells can be written or read as a bank to limit the impact of inconsistent CF formation of any one or more individual cells within the bank.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductor devices, and more specifically to non-volatile resistive random access memory (ReRAM) arrays. Background Technology

[0002] Typically, ReRAM is based on a sandwich structure or cell that includes a first electrode, a switching layer, and a second electrode. When a specific voltage is intentionally applied, a reversible and repeatable resistance change is achieved by controlling the connection and disconnection of conductive filaments (CF) in the switching layer.

[0003] When the CF ament is connected to the electrode, the ReRAM device exhibits high conductivity and is in a low resistance state (LRS). When the CF ament is disconnected from the electrode and there is a gap, the ReRAM is in a high resistance state (HRS). Based on the composition of the CF ament, ReRAM can be divided into oxygen vacancy-based ReRAM (OxRRAM) or metal ion-based ReRAM (also known as conductive bridge random access memory, CBRAM).

[0004] The resistivity mechanism of CBRAM is explained by the formation of metal ions and their connection to an electrode, which has been observed and confirmed by microscopy. The resistivity switching mechanism of OxRRAM is relatively more theoretical and has been explained by the migration of oxygen vacancies, which are activated by a combination of electric and thermal effects.

[0005] The migration of oxygen vacancies is inherently random. Therefore, the resistance variation of OxRRAM is random due to inconsistent CF formation. Inconsistent CF formation can be considered as CF formation failure (e.g., HRS of an OxRRAM cell when LRS is expected), can be considered as CF over-formation (e.g., LRS of an OxRAM cell when HRS is expected), or variable CF formation across a series of cells (e.g., different low resistance values ​​and / or high resistance values ​​across a series of OxRAM cells). Summary of the Invention

[0006] In an embodiment of the invention, a vertical resistive memory array is provided. The vertical resistive memory array includes front vertical resistive memory cells, each including a front resistive random access memory (ReRAM) pillar and a first vertically stacked electrode group connected to a first side of the front ReRAM pillar. The front ReRAM pillar includes a first pillar electrode and a first switch pad surrounding and contacting the sidewall perimeter of the first pillar electrode. The first vertically stacked electrode group includes a first upper single cell (SC) electrode in contact with the first switch pad and a first lower SC electrode in contact with the first switch pad.

[0007] In another embodiment of the invention, a method for a vertical resistive memory array is proposed. The method includes receiving a read request from a requesting device using a memory controller to obtain data stored in a single memory cell. The method includes applying a read potential to the vertical resistive memory cell using the memory controller, the vertical resistive memory cell comprising a plurality of ReRAM cells sharing a common pillar electrode. The method includes determining the equivalent resistance of the vertical resistive memory cell using the memory controller. The method includes determining the resistance state of the vertical resistive memory cell using the memory controller. The method further includes returning a data value associated with the determined resistance state of the vertical resistive memory cell to the requesting device using the memory controller.

[0008] In another embodiment of the invention, a method for a vertical resistive memory array is proposed. The method includes receiving a read request from a requesting device using a memory controller to obtain data stored in a single memory cell. The method includes applying a read potential to the vertical resistive memory cell using the memory controller, the vertical resistive memory cell comprising a plurality of ReRAM cells sharing a common pillar electrode. The method includes determining the resistance of each ReRAM cell in the plurality of ReRAM cells in the vertical resistive memory cell using the memory controller. The method includes determining a combined resistance of each resistance of the plurality of ReRAM cells in the vertical resistive memory cell using the memory controller. The method further includes: determining a resistance state of the vertical resistive memory cell from the combined resistance using the memory controller; and returning a data value associated with the determined resistance state of the vertical resistive memory cell to the requesting device using the memory controller.

[0009] These and other embodiments, features, aspects, and advantages will be better understood with reference to the following description, the appended claims, and the accompanying drawings. Attached Figure Description

[0010] To obtain and understand in detail the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to the embodiments of the invention shown in the accompanying drawings.

[0011] However, it should be noted that the accompanying drawings only illustrate typical embodiments of the invention and should not be considered as limiting the scope of the invention, as the invention can allow for other equally effective embodiments.

[0012] Figure 1 This is a perspective view of a vertical resistive memory array 100 according to an embodiment of the present invention.

[0013] Figure 2A A cross-section of a vertical resistive memory cell according to various embodiments of the present invention is depicted.

[0014] Figure 2B A cross-section of a ReRAM cell according to various embodiments of the present invention is depicted.

[0015] Figure 2C Circuit diagrams of a pair of vertical ReRAM cell libraries according to various embodiments of the present invention are depicted.

[0016] Figure 2D Circuit diagrams are depicted for a pair of vertical ReRAM cell libraries having inconsistent CF formation, according to various embodiments of the present invention.

[0017] Figure 3A and Figure 3B A front view depicting a wiring and electrode pattern according to an embodiment of the present invention is shown.

[0018] Figures 4 to 13 The manufacturing stages of an integrated circuit device including a vertical resistive memory array according to various embodiments of the present invention are described.

[0019] Figure 14 Normal diagrams of layers in a vertical resistive memory array according to various embodiments of the present invention are depicted.

[0020] Figure 15 A block diagram depicting a memory device embodying a vertical resistive memory array according to various embodiments of the present invention is shown.

[0021] Figures 16 to 19 The manufacturing stages of an integrated circuit device including a vertical resistive memory array according to various embodiments of the present invention are described.

[0022] Figure 20 Methods for writing data to a vertical resistive memory array according to various embodiments of the present invention are described.

[0023] Figure 21 Methods for reading data from a vertical resistive memory array according to various embodiments of the present invention are described.

[0024] Figure 22 Methods for reading data from a vertical resistive memory array according to various embodiments of the present invention are described.

[0025] Figure 23 Methods for manufacturing integrated circuit devices including vertical resistive memory arrays according to various embodiments of the present invention are described.

[0026] The accompanying drawings are not necessarily drawn to scale. They are schematic representations only and are not intended to describe specific parameters of the invention. The drawings are intended to illustrate exemplary embodiments of the invention only. In the drawings, the same reference numerals denote the same elements. Detailed Implementation

[0027] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, and they may be implemented in different forms. These exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Details of well-known features and techniques may be omitted in the description and drawings to avoid unnecessarily obscuring the presented embodiments.

[0028] Referring to the accompanying drawings, in which the same numerals denote the same components, exemplary manufacturing steps for forming an IC device comprising one or more ReRAM memory cells 100 are shown and described in more detail below. It should be noted that although this description may relate to some components of an IC device in a singular tense, an IC device may include more than one component. The specific components and cross-sectional orientations depicted in the drawings have been chosen to best illustrate the different embodiments described herein.

[0029] A vertical resistive memory array is presented. The array includes pillar electrodes and switch pads surrounding the side periphery of the pillar electrodes. The array includes two or more vertically stacked individual cell (SC) electrodes connected to a first side of the switch pads. The juxtaposition of the switch pads, pillar electrodes, and each SC electrode forms a corresponding resistive switching cell (e.g., an 0xRRAM cell). Vertical groups or sets of these cells can be connected in parallel and each shares the same pillar electrode. Cells within a vertical cell group can be written, read, reset, etc., as a group to limit the impact of inconsistent CF formation from any one or more individual cells within the group.

[0030] For clarity, different numbers are used here. When a number is followed by a subscript, refer to the specific instance of the number element. When a number does not include a subscript, the number element is generally referred to.

[0031] Figure 1 This is a perspective view of a vertical resistive memory array 100 according to an embodiment of the present invention.

[0032] The vertical resistive memory array 100 may include ReRAM pillars 102 and vertically stacked, and referred to herein as vertically aligned, individual cell (SC) electrodes 104, each connected to the ReRAM pillars 102. The ReRAM pillars 102 include switching pads 202 surrounding the periphery of the conductive pillar electrodes 204, such as... Figure 2A As shown. The juxtaposition of the switch pad 202, the pillar electrode 204, and each SC electrode 104 forms a corresponding ReRAM cell. The vertical resistive memory array 100 may further include vertically stacked multiple cell (MC) electrodes 106 connected to at least two SC electrodes 104 via high-resistance elements (HREs) 108.

[0033] For example, the vertical resistive memory array 100 may include front ReRAM pillars 102. f and ReRAM column 102 r The vertical resistive memory array 100 may include connections to the front ReRAM pillar 102. f Vertically stacked SC electrodes 104 flr and vertically stacked SC electrodes 104 fur The vertical resistive memory array 100 may further include connections to the front ReRAM pillar 102. f Vertically stacked SC electrodes 104 fll and vertically stacked SC electrodes 104 ful Similarly, the vertical resistive memory array 100 may include connections to the rear ReRAM pillars 102. r Vertically stacked SC electrodes 104 rlr and vertically stacked SC electrodes 104 rur Similarly, the vertical resistive memory array 100 may further include connections to the rear ReRAM pillars 102. r Vertically stacked SC electrodes 104 rll and vertically stacked SC electrodes 104 rul .

[0034] The vertical resistive memory array 100 may further include vertically stacked MC electrodes 106. 1r and MC electrode 106 ur It may also include vertically stacked MC electrodes 106 11 and MC electrode 106 ul MC electrode 106 1rIt can be done via HRE108 flr Connected to SC electrode 104 flr And it can be done via HRE 108 rlr Connected to SC electrode 104 rlr MC electrode 106 ur It can be done via HRE 108 fur Connected to SC electrode 104 fur And it can be done via HRE 108 rur Connected to SC electrode 104 rur MC electrode 106 11 It can be done via HRE 108 fll Connected to SC electrode 104 fll And it can be done via HRE 108 rll Connected to SC electrode 104 rll MC electrode 106 ul It can be done via HRE 108 ful Connected to SC electrode 104 ful And it can be done via HRE 108 rul Connected to SC electrode 104 rul .

[0035] SC electrode 104 flr SC electrode 104 fll SC electrode 104 rlr SC electrode 104 rll MC electrode 106 1r MC electrode 106 11 HRE electrode 108 flr HRE electrode 108 fll HRE electrode 108 rlr and / or HRE electrode 108 rll They can be located in the same lower wiring layer. For example, the corresponding top surfaces of such components can be coplanar and the corresponding bottom surfaces of such components can be coplanar.

[0036] Similarly, SC electrode 104 fur SC electrode 104 ful SC electrode 104 rur SC electrode 104 rul MC electrode 106 ur MC electrode 106 ul HRE electrode 108 fur HRE electrode 108 ful HRE electrode 108 rur and / or HRE electrode 108 rulThey can be located in the same upper wiring layer. For example, the corresponding top surfaces of such components can be coplanar and the corresponding bottom surfaces of such components can be coplanar.

[0037] Although Figure 1 The embodiment shown illustrates a vertical resistive memory array 100 including a pair of ReRAM pillars 102 and associated other vertically aligned wiring features. However, it should be understood that this particular configuration is not required, and other alternative configurations are possible. For example, the vertical resistive memory array 100 may include additional ReRAM pillars 102 and associated other vertically aligned wiring features and / or additional vertically aligned wiring features associated with the pair of ReRAM pillars 102, etc.

[0038] The vertical distance between wiring levels can vary depending on various factors and requirements. Similarly, the longitudinal length between wiring features can vary depending on various factors and requirements. Furthermore, it should be understood that each SC electrode 104 and MC electrode 106 can be a patterned conductive element and can be formed from a first conductor material such as copper (Cu), tungsten (W), etc., and HRE 108 can be a patterned conductive element and can be formed from a second conductor material such as tantalum nitride (TaN), titanium nitride (TiN), etc., which has a higher resistance than the first conductor.

[0039] It should also be understood that the MC electrode 106, two or more SC electrodes 104, and two or more associated HREs 108 are electrically connected. For example, the MC electrode 106 ul Electrically connected to HRE 108 ul And therefore with HRE 108 ul Communication, electrical connection to HRE108 ul And therefore with HRE 108 rul Communication. HRE 108 ful Electrically connected to SC electrode 104 ful And therefore with SC electrode 104 ful Communication. HRE 108 rul Electrically connected to SC electrode 104 rul And therefore with SC electrode 104 rul communication.

[0040] It should be understood that the vertical resistive memory array 100 can be operably disposed above a first metallization layer and below a second metallization layer in a wafer assembly. One or more of the features of the vertical resistive memory array 100 can provide electrical connections and communication between different components of at least the first and second metallization layers of the wafer assembly.

[0041] Figure 2AA cross-section of a vertical resistive memory cell 210 according to various embodiments of the present invention is depicted. The vertical resistive memory cell 210 typically includes a single ReRAM pillar 102 and vertically stacked SC electrodes 104 in an upper wiring layer and in a lower wiring layer. The juxtaposition of the switch pads 202 of the ReRAM pillar 102, the pillar electrodes 204 of the ReRAM pillar 102, and each SC electrode 104 forms a corresponding ReRAM cell 230. A first set of vertically stacked SC electrodes 104 may contact a first side of the ReRAM pillar 102, and a second set of vertically stacked SC electrodes 104 may contact a second side of the ReRAM pillar 102.

[0042] For example, the vertical resistive memory cell 2101 includes an SC electrode 104. 1a SC electrode 104 1b SC electrode 104 1c SC electrode 104 1d ReRAM pillar 102. Switch pad 202, pillar electrode 204, and SC electrode 104. 1a The juxtaposition of these elements forms the corresponding ReRAM cells 230. 1a Similarly, the switch pad 202, the pillar electrode 204, and the SC electrode 104 1b The juxtaposition of these elements forms the corresponding ReRAM cells 230. 1b ReRAM cell 230 1c and ReRAM cell 230 1d Similarly, it is formed. Accordingly, the vertical resistive memory cell 2101 includes a group or set of vertically aligned ReRAM cells 230, which include ReRAM cells 230. 1a ReRAM cell 230 1b ReRAM cell 230 1c and ReRAM cell 230 1d .

[0043] Similarly, vertical resistive memory cell 210 r Including SC electrode 104 ra SC electrode 104 rb SC electrode 104 rc SC electrode 104 rd And the same ReRAM pillar 102 associated with the vertical resistive memory cell 2101. Switch pad 202, pillar electrode 204, and SC electrode 104 ra The juxtaposition of these elements forms the corresponding ReRAM cells 230. ra Similarly, the switch pad 202, the pillar electrode 204, and the SC electrode 104 rbThe juxtaposition of these elements forms the corresponding ReRAM cells 230. rb ReRAM cell 230 rc and ReRAM cell 230 rd Similarly, it is formed. Accordingly, the vertical resistive memory cell 210 r Includes one or more vertically aligned ReRAM cells 230, each ReRAM cell 230 comprising a ReRAM cell 230. ra ReRAM cell 230 rb ReRAM cell 230 rc and ReRAM cell 230 rd .

[0044] Figure 2B A cross-section of a ReRAM cell 230 according to various embodiments of the present invention is depicted.

[0045] ReRAM is a non-volatile solid-state memory technology that utilizes the changing resistance of an insulator, such as a binary metal oxide, under an applied electric field. A basic memory cell (“cell”) can be programmed to exhibit at least two distinct states or levels exhibiting different resistance characteristics. Programmable cell states can be used to represent different data values, allowing for the storage of information.

[0046] ReRAM architecture typically includes resistance-switched memory cells with a metal-insulator-metal structure commonly referred to as a MIM structure. This structure includes an insulating layer (I) sandwiched between two metal (M) electrodes. Applying a voltage pulse to the ReRAM cell allows the device to transition from an HRS or off state (commonly referred to as logic value '0') to an LRS or on state (commonly referred to as logic value '1'), and vice versa.

[0047] Typically, the fabricated ReRAM cell is initially in the HRS, and to switch the device from the HRS to the LRS, the application of a formation voltage (e.g., a high-voltage pulse, write voltage, etc.) enables the formation of a CF in the switching layer, thereby switching the ReRAM cell to the LRS. This process, which occurs due to the soft breakdown of the metal-insulator-metal (MIM) structure, is commonly referred to as "electroforming," and the voltage at which this process occurs is called the formation voltage. To switch the ReRAM cell from the LRS to the HRS, a voltage pulse called the RESET voltage is applied.

[0048] To read data from a ReRAM cell, a read voltage that does not interfere with the cell's current state is applied to determine whether the cell is in HRS or LRS. Since LRS and HRS retain their respective values ​​even after the applied voltage is removed, ReRAM is a non-volatile memory.

[0049] The switching of ReRAM cells is based on the growth of CFs within the insulating layer. CFs are channels with nanometer-scale diameters that connect the electrodes of the cell. When CFs are connected between electrodes, LRS with high conductivity is obtained, and HRS is obtained when the filaments are disconnected from the electrodes.

[0050] The exemplary ReRAM cell 230 includes a switching pad 202 located between the SC electrode 104 and the pillar electrode 204. The cell state shown represents the LRS state, wherein the CF 204 has been formed within the switching pad 202 and is in contact, touching, or otherwise connected to both the SC electrode 104 and the pillar electrode 204. During the formation of the CF 204 and the corresponding electrical connection between the SC electrode 104 and the pillar electrode 204, and when a read voltage is applied to read the programmed cell state, the resulting read current flows primarily through the current path to / from the SC electrode 104 and the pillar electrode 204 and through the CF 204, preferentially over the high-resistivity insulating material of the switching pad 202 in which the CF 204 is not yet formed.

[0051] In order to write to ReRAM cell 230, a write or formation voltage is applied to SC electrode 104 or pillar electrode 204, and the resulting programming current through the cell causes the switching pad 202 to break down and the CF 204 connecting SC electrode 104 and pillar electrode 204 to form, thereby switching ReRAM cell 200 from initial HRS to LRS.

[0052] Reading of ReRAM cell 230 is performed using the resistance of cell 230 as a measure of cell state. A read voltage is applied to SC electrode 104 or pillar electrode 204, causing a read current to flow through cell 230. The read current depends on the resistance across SC electrode 104 and pillar electrode 204 or between SC electrode 104 and pillar electrode 204. Therefore, the measurement of the cell read current provides an indication of the state of the programmed cell 230. A sufficiently low read voltage is used for this resistance measurement to ensure that the application of the read voltage does not interfere with the programmed cell state. Cell state detection can then be performed by comparing the resistance measurement with a predefined reference level for the programmable cell state. To switch ReRAM cell 230 from LRS back to the initial HRS, a voltage pulse, known as the RESET voltage, is applied to SC electrode 104 or pillar electrode 204.

[0053] Figure 2C The pair of vertical resistive memory cells 2101, 210 according to various embodiments of the present invention are depicted. r The circuit diagram. As depicted, when vertical resistive memory cell 2101 and vertical resistive memory cell 210... rWhen they share the same pillar electrode 204, they share a circuit node. The voltage applied at this node is described as V. 204 In the embodiment, the applied voltage V 204 It can be a low potential or ground potential, a set potential or write potential, a read potential, a reset potential, etc.

[0054] The voltage applied at each SC electrode 104 associated with the vertical resistive memory cell 2101 is described as V. I In relation to the vertical resistive memory cell 210 r The voltage applied at each associated SC electrode 104 is described as V r In the embodiments, the applied voltage, voltage pulse, etc. l and V r It can be a high voltage, such as a forming voltage, reading voltage, or setting / resetting voltage. Typically, the SC electrodes 104 are not directly connected in the vertical direction. Therefore, each SC electrode 104 can be connected via, for example... Figure 18 The MC electrode 108 / HRE 108, VIA 420, or other wiring features shown are physically connected, or can be virtually connected by applying the same bias or potential to the corresponding SC electrode 104.

[0055] It should be understood that the vertical resistive memory cell 2101 can therefore be configured as a first group or vertically aligned ReRAM cells 230 that are programmed, read, and / or reset into a group (i.e., a set). All vertically aligned ReRAM cells 230 in the vertical resistive memory cell 2101 undergo the same programming, writing, reading, resetting, etc. operations. Similarly, the vertical resistive memory cell 2101 can also be configured as a second group or set of vertically aligned ReRAM cells 230 that are programmed, read, and / or reset into a set.

[0056] In the embodiment, V l equals V r Accordingly, vertical resistive memory cells 2101 and 210... r The ReRAM cells 230 in both undergo the same and simultaneous read, write, and reset operations. In other embodiments, V l Not equal to V r Accordingly, each vertical resistive memory cell 2101, 210 r The ReRAM cell 230 can undergo different and / or simultaneous read, write, and reset operations. For example, the vertical resistive memory cell 210... l The ReRAM cell 230 can be written to, while the vertical resistive memory cell 210... rThe ReRAM cell 230 in the memory can be read simultaneously.

[0057] Figure 2D A pair of vertical resistive memory cells 2101, 210 according to various embodiments of the present invention are depicted. r The circuit diagram shows the pair of vertical resistive memory cells 2101 and 210. r Each of the ReRAM cells 230 has an inconsistent CF formation.

[0058] As noted herein, inconsistent CF formation can be considered as CF 206 formation failure. This occurs when ReRAM cell 230 has been programmed into the LRS (i.e., expected LRS but cell 230 remains in the HRS), or when ReRAM cell 230 remains in its HRS. Inconsistent CF formation can also be considered as CF 206 exceeding formation. This subsequently occurs, with ReRAM cell 230 remaining in the LRS even after a reset operation (i.e., LRS). (The HRS is determined by the cell 230 remaining in the LRS). For example, as shown, this occurs relative to other ReRAM cells 230 in the vertical resistive memory cell 2101. 1a 230 1b and 230 1d It can be found in ReRAM cell 230 1c The formation of CF 206 failed. ReRAM cell 230 1c This failure to form CF 206 may lead to ReRAM cell 230 1c The HRS, while other ReRAM cells 230 in the vertical resistive memory cell 2101 1a 230 1b and 230 1d In LRS. Or, ReRAM cell 230. 1c This failure to form CF 206 may lead to ReRAM cell 230 1c The LRS, while the other ReRAM cells 230 in the vertical resistive memory cell 2101. 1a 230 1b and 230 1d In HRS.

[0059] It should also be noted that inconsistent CF formation can be considered as variable CF 206 formation over a certain range of cells 230. This occurs when the ReRAM cells 230 within the vertical resistive memory cell 210 have been subjected to operations such as writes or resets, and when the ReRAM cells 230 within the vertical resistive memory cell 210 have different or variable resistance values ​​over a range. For example, the vertical resistive memory cell 210r Each ReRAM cell in the 230 ra ReRAM cell 230 rb ReRAM cell 230 rc and ReRAM cell 230 rd Each can withstand a reset operation and is within the HRS, but can have relatively different resistances across it. Similarly, the vertical resistive memory cell 210 r Each ReRAM cell in the 230 ra ReRAM cell 230 rb ReRAM cell 230 rc and ReRAM cell 230 rd Each can be subjected to write operations and is therefore in the LRS, but can have relatively different resistances across the LRS.

[0060] To limit the impact of inconsistent CF 206 formation in any one or more individual cells 230 within the vertical resistive memory cell 210, each of the cells 230 can undergo the same simultaneous write, reset, program, and other operations. Subsequently, one or more cells 230 within the vertical resistive memory cell 210 may experience inconsistent CF 206 formation.

[0061] Cells 230 within the vertical resistive memory cell 210 are further read into a group. During a read operation, the resistance values ​​of each corresponding cell 230 can be combined (e.g., the average, median, pattern, trimmed average, etc., of the resistance values ​​can be determined), and the combined resistance values ​​can be used to determine the resistance state (e.g., LRS, HRS, etc.) of all cells 230 within the vertical resistive memory cell 210. Therefore, even if one or more cells 230 within the vertical resistive memory cell 210 may have individually experienced inconsistent CF 206 formation, the normalized resistance state of that group of cells 230 can be determined due to the presence or influence of other cells 230 within the vertical resistive memory cell 210 that have not yet experienced inconsistent CF 206 formation. The normalized resistance state of this group of cells 230 more accurately indicates the expected LRS or HRS of cells 230 within the vertical resistive memory cell 210 because there are a greater number of cells 230 within cell 210 compared to those cells 230 (i.e., those cells 230 that have not experienced inconsistent CF 206 formation, have experienced slightly inconsistent CF 206 formation, etc.). Abnormal cells (within cell 210) have experienced inconsistent CF 206 formation, resulting in a large difference in resistance value relative to the average resistance value of cells 230 within cell 210.

[0062] The number of ReRAM cells 230 within the vertical resistive memory cell 210 can be determined from a predetermined acceptable standard deviation of the resistance value of each cell 230 within the cell 210. If each ReRAM cell 230 within the cell 210 has a random variation in its resistance value over the average resistance value of the cells 230 within the cell 210, then the standard deviation for determining the range of resistance values ​​of each cell 230 within the cell 210 is reduced by the square root of “n”, where “n” is the number of ReRAM cells 230 within the vertical resistive memory cell 210.

[0063] Figure 3A and Figure 3B A front view depicting a wiring and electrode pattern 250 according to an embodiment of the present invention is shown. Figure 3A As shown, the wiring and electrode pattern 250 can be a wiring pattern formed of a first conductor material, such that the MC electrode 106, SC electrode 104, and HRE 108 are formed of or made of the first conductor material. Figure 3B As shown, the wiring and electrode pattern 250 can be a wiring pattern formed of a first conductor material and a second conductor material, such that the MC electrode 106 and the SC electrode 104 are formed of the first conductor material or are formed of the first conductor material, and the HRE 108 is formed of the second conductor material or is formed of the second conductor material.

[0064] It should be understood that the HRE 108 can take the form of a serpentine wiring connected to the corresponding SC electrode 104 and the corresponding MC electrode 106. The HRE 108 can be connected in series to the corresponding SC electrode 104 and the corresponding MC electrode 106. The HRE 108 is used to reduce, limit, or gradually decrease the current at ReRAM cell 230. Typically, if the current at ReRAM cell 230 is too high, it may increase the formation of inconsistent CF 206. For example, if the current through ReRAM cell 230 is too high, over-formation may be more likely, which may ultimately cause ReRAM cell 230 to get stuck in HRS. Accordingly, the presence of the HRE 108 gradually reduces, decreases, or otherwise limits the current through ReRAM cell 230 relative to the current through ReRAM cell 230 if the HRE 108 were not present.

[0065] HRE 108 assists in the formation of CF 206 by establishing a lower limit or bottom layer of resistance that sets or limits the current through ReRAM cell 230. In an illustrative example, an initial voltage of 5 volts is established on ReRAM cell 230, and the associated HRE is 10 kOhm. Initially, all 5V drops across ReRAM cell 230 before CF 206 forms because switch pad 202 is infinite or otherwise much higher. Once CF 206 formation begins, the resistance of the filamentary path through switch pad 202 decreases. For example, the resistance through switch pad 202 drops to 100 kOhm (the total resistance through HRE 108 and switch pad 202 is 110 kOhm). In this respect, the voltage drop across switch pad 202 is 5V. 10kOhm / 110kOhm to HRE 108 and 5V The initial flow rate is 100 kOhms to the switch pad 202. Over time, CF 206 grows further and a filament of 10 kOhms can now be constructed. Then 5V... 10kOhm / 20kOhm across HRE 108 drops, while 5V A 10kOhm / 20kOhm voltage drop occurs across ReRAM cell 230. At this point, the 2.5V drop across CF 206 is insufficient, and ReRAM cell 230 may not have a sufficient voltage drop (or electric field) to induce further movement of oxygen vacancies. Therefore, CF 206 growth or formation ceases. Accordingly, CF 206 formation can be controlled using an external resistor, HRE 108.

[0066] The HRE 108 also establishes a lower limit to prevent damage caused by a short circuit in the ReRAM cell 230. If a short circuit occurs, the HRE 108 effectively combines with the resistor of the short-circuited ReRAM cell 230, ensuring that no excessive current flows through the cell 230.

[0067] In some embodiments, the SC electrode 104 may include a partial pillar recess, which may be a recess through the SC electrode 104 of a shape associated with the periphery of the ReRAM pillar 102, or may not exist. For example, the SC electrode 104 fl SC electrode 104 fr SC electrode 104 rl and SC electrode 104 rr Each may include a partial pillar recess. Partial pillar recesses of adjacent device SC electrodes 104 (i.e., those SC electrodes associated with the same ReRAM pillar 102) may together form a pillar recess 252 associated with the entire perimeter of the ReRAM pillar 102. For example, SC electrode 104 fl and SC electrode 104 frThe internal column recesses can be formed together to create column recess 252. f And SC electrode 104 rl and SC electrode 104 rr The internal column recesses can be formed together to create column recess 252. r .

[0068] The sidewall of the SC electrode 104 that faces or otherwise defines the column recess 252 may be referred to herein as column sidewall 254, column-facing sidewall 254, etc.

[0069] Figure 4 A manufacturing stage 300 of an IC device manufacturing method according to various embodiments of the present invention is shown. In stage 300, a plurality of RRAM levels are formed, each RRAM level including a dielectric layer 406 and wiring and electrode patterns 250 formed on the dielectric layer 406.

[0070] For example, dielectric layer 4061 may be formed on dielectric layer 402 and / or metal or conductive layer 404. In some implementations, dielectric layer 402 and / or metal or conductive layer 404 may be the top layer of the first shoreline end (BEOL) metallization level.

[0071] Wiring and electrode patterns 2501 may be formed on dielectric layer 4061. The wiring and electrode patterns 2501 can be formed on dielectric layer 4061 using a subtractive technique, wherein undesired portions of the conductive material layer are removed, while desired portions of the conductive material layer are retained to form the wiring and electrode patterns 2501. In an exemplary embodiment, a mask (not shown) may be formed on a conductive material layer (not shown). The mask may be patterned using known photolithography techniques. Portions of the mask may be retained to protect the underlying and desired portions of the conductive material layer. An etchant may remove the undesired portions of the conductive material layer while retaining the protected and desired portions. The mask may be removed to expose the desired portions of the conductive material layer for effectively forming the wiring and electrode patterns 2501.

[0072] Wiring and electrode patterns 2501 can be formed on dielectric layer 4061 using additive techniques, wherein conductive material is added to or deposited on dielectric layer 4061. In an exemplary implementation, a first mask (not shown) can be formed on upper dielectric layer 4061. The first mask can be patterned using known photolithography techniques to form first wiring and / or electrode trenches that expose the lower portion of dielectric layer 4061. A first conductive material can be electroplated or otherwise deposited within the first wiring and / or electrode trenches, on the exposed lower portion of dielectric layer 4061. A second mask (not shown) can be formed on the first mask and the first conductive material. The second mask and the first mask can be patterned using known photolithography techniques to form second wiring and / or electrode trenches that expose the lower portion of dielectric layer 4061. The second conductive material may be electroplated or otherwise deposited within the second wiring and / or electrode trenches, on the exposed lower layer portion of the dielectric layer 4061. The first and second masks may be removed, retaining the characteristics of the first and second conductive materials. The first conductive material can effectively form the SC electrode 104 and the MC electrode 106, and the second conductive material can effectively form the HRE 108.

[0073] Another dielectric layer 4062 may be formed on dielectric layer 4061 and wiring and electrode pattern 2501. Another wiring and electrode pattern 2502 may be formed on dielectric layer 4062 using subtractive or additive forming techniques. Another dielectric layer 4063 may be formed on dielectric layer 4062 and wiring and electrode pattern 2502. Another wiring and electrode pattern 2503 may be formed on dielectric layer 4063 using subtractive or additive forming techniques. Another dielectric layer 4064 may be formed on dielectric layer 4063 and wiring and electrode pattern 2503. Another wiring and electrode pattern 2504 may be formed on dielectric layer 4064 using subtractive or additive forming techniques. These processes may continue until dielectric layer 406... n Formed on the underlying dielectric layer 406 and the underlying wiring and electrode pattern 250. Another wiring and electrode pattern 250. n It can be formed on dielectric layer 406 using subtractive or additive forming techniques. n Above. In some embodiments, dielectric layer 406 may be used. n Above and in wiring and electrode patterns 250 n A dielectric layer 408 is formed on top.

[0074] The dielectric layers 406, 408, etc. can be layers such as octamethylcyclotetrasiloxane (OMCTS) or tetraethyl orthosilicate (TEOS) and can have a sheet thickness of 150 nm – 1500 nm.

[0075] 250 through wiring and electrode patternn Different wiring and electrode patterns 2501 can be formed to be vertically aligned with each wiring and electrode pattern 250 n The adjacent SC electrodes 104 within the column recess 252 are associated with each other. For example, the corresponding centers of the column recess 2521, column recess 2522, column recess 2523 and column recess 2524 may be oriented, coincident or otherwise on the same vertical axis 411.

[0076] Figure 5 The illustration shows manufacturing stage 302 of an IC device manufacturing method according to various embodiments of the present invention. In stage 302, pillar trenches 412 are formed.

[0077] The columnar trench 412 can be a trench, hole, well, etc., formed within the stack of dielectric layers 406, 408 by vertically aligned columnar trenches 254, which can expose the columnar sidewalls 254 of the SC electrode 104. As depicted, the columnar trench 412 can expose a portion of the dielectric layer 402.

[0078] The columnar trench 412 can be fabricated using a subtractive forming technique that removes unwanted portions of the dielectric layers 406, 408. In an exemplary embodiment, a mask (not shown) can be formed on the dielectric layer 408. The mask can be patterned using known photolithography techniques. Portions of the mask can be retained to protect the underlying and desired portions of the dielectric layers 406, 408. The removed portions of the mask can be perpendicularly aligned with the aligned columnar trench 254. An etchant can remove the unwanted portions of the dielectric layers 406, 408, thus forming the columnar trench 412. The mask can be removed. Different known etching techniques can be used to form tapered, angled, or inclined trench 412 sidewalls relative to the xz plane, or trench 412 sidewalls orthogonal to the xy plane.

[0079] Figure 6 The illustration shows manufacturing stage 304 of an IC device manufacturing method according to various embodiments of the present invention. In stage 304, a switch pad 202 is formed within a pillar groove 412.

[0080] The switch pad 202 can be formed using known additive forming techniques. For example, the switch pad 202 can be formed on the sidewalls and lower surface of the trench 412 by chemical vapor deposition (CVD) or the like.

[0081] Switch pad 202 can be HfO x WO x TaO x TiO x NiO x SiO x Layers such as GeS and GeSe can be used, and can have thicknesses ranging from 1 nm to 30 nm.

[0082] Figure 7 The illustration shows manufacturing stage 306 of an IC device manufacturing method according to various embodiments of the present invention. In stage 306, a pillar electrode 204 is formed on a switch pad 202 within a pillar trench 412.

[0083] The pillar electrode 204 can be formed on the switch pad 202 within the pillar trench 412 using an addition technique that involves adding or depositing conductive material. In an exemplary embodiment, a mask (not shown) may be formed on the upper dielectric layer 408. The mask may be patterned using known photolithography techniques to form an opening above the pillar trench 412. The conductive material may be electroplated or otherwise deposited within the pillar trench 412 on the switch pad 202. The mask may be removed, and chemical mechanical polishing (CMP) may planarize the top surface of the pillar electrode 204 with the top surface of the dielectric layer 408. It should be understood that when the pillar electrode 204 is formed on the switch pad 202, the ReRAM pillar 102 is thereby formed.

[0084] Figure 8 Manufacturing stage 308 of an IC device manufacturing method according to various embodiments of the present invention is depicted. In stage 308, a dielectric layer 414 is formed on a dielectric layer 408 and a conductor 416 (if formed within the dielectric layer 414).

[0085] In some implementations, dielectric layer 414 may be the bottom layer of the second BEOL metallization layer.

[0086] Conductors 416 may be formed within dielectric layer 414. Wiring trenches may be formed within dielectric layer 414 using a subtraction technique, wherein unwanted portions of dielectric layer 414 are removed to form a wiring pattern while retaining desired portions of dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on dielectric layer 414. The mask may be patterned using known photolithography techniques. An etchant may remove unwanted portions of dielectric layer 414. The mask may be removed to expose portions of the upper surface of dielectric 408 and the upper surface of ReRAM pillar 102.

[0087] Conductors 416 can be formed within dielectric layer 414 using additive techniques, wherein conductive material is added or deposited within wiring trenches in dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on upper dielectric layer 414. The mask may be patterned using known photolithography techniques to remove portions above the wiring trenches. Conductive material may be electroplated or otherwise deposited within the wiring trenches in dielectric layer 414 on exposed lower portions of ReRAM pillar 102. The mask may be removed, and CMP may planarize the top surface of conductor 416 and the upper surface of dielectric layer 414.

[0088] Figure 9The illustration shows a manufacturing stage 310 of an IC device manufacturing method according to various embodiments of the present invention. In stage 310, a pillar trench 412 is formed. The pillar trench 412 may be a trench, hole, well, etc., formed within the stack of dielectric layers 406, 408 by vertically aligned pillar trenches 254, which may expose a portion of the pillar sidewalls 254 of the SC electrode 104 and the upper surface of the metal or conductive layer 404.

[0089] Figure 10 The illustration shows manufacturing stage 312 of an IC device manufacturing method according to various embodiments of the present invention. In stage 312, a switch pad layer 202' is formed within the pillar trench 412 and on the dielectric layer 408.

[0090] The switch pad 202 can be formed using known additive forming techniques. For example, the switch pad layer 202' can be formed on the dielectric layer 408 and on the sidewalls and lower surface of the trench 412 using atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The switch pad layer 202' can be HfO. x WO x TaO x TiO x NiO x SiO x It can have GeS and GeSe layers and can have a sheet thickness of 1 nm to 30 nm.

[0091] Figure 11 Manufacturing stage 314 of an IC device manufacturing method according to various embodiments of the present invention is shown. In stage 314, while remaining on the sidewalls of the pillar trench 412, the switch pad layer 202' is partially removed from the upper surface of the dielectric layer 408 and from the upper surface of the metal or conductor layer 404, thereby forming the switch pad 202.

[0092] The switch pad layer 202' can be partially removed using a subtraction technique, wherein unwanted portions of the switch pad layer 202' are removed while desired portions are retained to form the switch pad 202. In an exemplary embodiment, directional etching can be used to remove unwanted switch pad layers 202' from the upper surface of the dielectric layer 408 and from the bottom of the pillar trench 412. Etching typically exposes a portion of the metal layer 404 within the pillar trench 412.

[0093] Figure 12 The illustration shows manufacturing stage 316 of an IC device manufacturing method according to various embodiments of the present invention. In stage 316, pillar electrodes 204 are formed on switch pads 202 and on metal layers 404 within pillar trenches 412.

[0094] The pillar electrode 204 can be formed on the switch pad 202 and on the metal layer 404 within the pillar trench 412 by adding or depositing conductive material. In an exemplary embodiment, a mask (not shown) may be formed on the upper dielectric layer 408. The mask may be patterned using known photolithography techniques to form an opening above the pillar trench 412. The conductive material may be electroplated or otherwise deposited on the switch pad 202 and within the pillar trench 412 on the metal layer 404. The mask may be removed, and chemical mechanical polishing (CMP) may planarize the top surface of the pillar electrode 204 with the top surface of the dielectric layer 408. It should be understood that when the pillar electrode 204 is formed on the switch pad 202, the ReRAM pillar 102 is thereby formed.

[0095] Figure 13 Manufacturing stage 318 of an IC device manufacturing method according to various embodiments of the present invention is depicted. In stage 318, if a dielectric layer 414 and a conductor 416 are formed within a dielectric layer 414, then a dielectric layer 414 is formed on the dielectric layer 408 and the conductor 416.

[0096] In some implementations, dielectric layer 414 may be the bottom layer of the second BEOL metallization layer.

[0097] Conductors 416 may be formed within dielectric layer 414. Wiring trenches may be formed within dielectric layer 414 using a subtraction technique, wherein unwanted portions of dielectric layer 414 are removed to form a wiring pattern while retaining desired portions of dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on dielectric layer 414. The mask may be patterned using known photolithography techniques. An etchant may remove unwanted portions of dielectric layer 414. The mask may be removed to expose portions of the upper surface of dielectric 408 and the upper surface of ReRAM pillar 102.

[0098] Conductors 416 can be formed within dielectric layer 414 using additive techniques, wherein conductive material is added or deposited within wiring trenches in dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on upper dielectric layer 414. The mask may be patterned using known photolithography techniques to remove portions above the wiring trenches. Conductive material may be electroplated or otherwise deposited within the wiring trenches in dielectric layer 414 on exposed lower portions of ReRAM pillar 102. The mask may be removed, and CMP may planarize the top surface of conductor 416 and the upper surface of dielectric layer 414.

[0099] It should be understood that the wiring 416 and dielectric layer 414 structure can replace the conductor or metal layer 404. In other words, instead of the potential plane conductor or metal layer 404, a wiring layer having the structure of wiring 416 and dielectric layer 414 can be used as a base layer in which IC devices may be formed. In these embodiments, the ReRAM pillar 102 may contact the upper wiring 416, as depicted, and the lower base wiring, as described.

[0100] Figure 14 A front view depicting the hierarchy of a vertical resistive memory array 100 according to various embodiments of the present invention is shown. The hierarchy of the vertical resistive memory array 100 includes wiring and electrode patterns 250 having ReRAM pillars 102 respectively formed in or replacing the pillar recesses 252.

[0101] For example, including pillar electrode 204 r and switch pad 202 r ReRAM column 102 r It has already formed in the column recess 252 r Internal or replacement column recess 252 r And includes pillar electrode 204 f and switch pad 202 f ReRAM column 102 f It has already formed in the column recess 252 f Internal or replacement column recess 252 f ReRAM column 102 r It is formed on the ReRAM pillar 102 in combination with the corresponding SC electrode 104. rr ReRAM cell 230 on the first side rl and in ReRAM column 102 r ReRAM cell 230 on the second side rr Formed in ReRAM column 102 f ReRAM cell 230 on the first side fl and in ReRAM column 102 fr ReRAM cell 230 on the second side fr .

[0102] In some embodiments, the MC electrode 106 includes a VIA recess 419. The VIA recess 419 in each layer of the vertical resistive memory array 100 can be vertically aligned and can generally define the location of the VIA of the MC electrode 106 that can be connected to different layers of the vertical resistive memory array 100.

[0103] Figure 15A block diagram of a memory 500 device embodying a vertical resistive memory array 100 according to various embodiments of the present invention is depicted. The device 500 includes a vertical resistive memory array 100 for storing and / or reading data therefrom. Reading and writing data to the vertical resistive memory array 100 can be performed by a read / write controller or controller 510. Controller 510 includes circuitry of generally known form for programming appropriately vertically aligned cells 230 in the memory cells 210 during data write operations, and for performing read measurements to detect the state of the corresponding cells 230 of the vertical resistive memory cells 210 during data read operations. During these operations, the read / write controller 510 can address individual vertical resistive memory cells 210 by applying appropriate control signals to the word lines and bit lines of the array 100. Input data, or data to be written to the device 500, can undergo some form of write processing, such as encoding for error correction purposes, by a write processing module 520 before being supplied as input data to controller 510. Similarly, the output data or data read by the controller 510 can be processed by the read processing module 530, for example, for codeword detection and / or error correction, to recover the original input data.

[0104] The vertical resistive memory array 100 can store information, for example, in two programmable cell 230 states. As previously described, the programmable cell states correspond to different relative resistances across the respective cells 230. These states include at least HRS and LRS. The programmable cell 230 states are typically defined in the controller 510 based on a predetermined reference value or range of values ​​for a combined resistance measurement of the vertical resistive memory cells 210 used for read detection. To program the vertical resistive memory cells 210 during a write operation, the controller 510 applies, for example, a corresponding voltage to the MC electrode 106, such that a write voltage, set voltage, programming voltage, etc., are applied at the SC electrode 104. A ground / low potential at the post electrode 204 causes the resulting programming signal to set the associated cell 230 to the desired state (e.g., LRS).

[0105] During a read operation, a (lower) read voltage is applied to the vertical resistive memory cells 210 and the resulting current through these cells 230 is measured to obtain the resistance of these cells 230. The controller 510 can then detect the state of the programmed cells 230 by combining the resistances of the vertically aligned cells 230 and comparing the combined measured resistance with the appropriate reference value described above.

[0106] During the reset operation, the controller 510 applies a voltage to the vertical resistive memory cell 210, such that a corresponding reset voltage is applied at the SC electrode 104, for example, at the SC electrode 104. The ground / low potential at the pillar electrode 204 causes the resulting reset signal to effectively reset the associated cell 230 back to the HRS state.

[0107] Figure 16 A manufacturing stage 330 of an IC device manufacturing method according to various embodiments of the present invention is illustrated. In stage 330, a plurality of RRAM levels are formed, each RRAM level including a dielectric layer 406 and wiring and electrode patterns 250 formed on the dielectric layer 406. In some implementations, stage 330 may be the same as stage 300.

[0108] Patterns can be formed through wiring and electrodes 250 n Different wiring and electrode patterns 2501 are used to vertically align the VIA recess 419 within the vertically aligned MC electrode 106. For example, the corresponding centers of VIA recess 4191, VIA recess 4192, VIA recess 4193 and VIA recess 4194 may be oriented, coincident, etc. on the same vertical axis 415.

[0109] Figure 17 Manufacturing stage 332 of an IC device manufacturing method according to various embodiments of the present invention is depicted. In stage 332, a VIA trench 413 is formed. In some implementations, stage 332 may be the same as stage 302 or stage 310.

[0110] VIA trench 413 may be a trench, hole, well, etc., formed within the stack of dielectric layers 406, 408 through vertically aligned VIA recesses 419. As depicted, pillar trench 412 may expose a portion of dielectric layer 402 or metal or conductor layer 404.

[0111] The VIA trench 413 can be fabricated using a subtractive forming technique that removes unwanted portions of the dielectric layers 406, 408. In an exemplary embodiment, a mask (not shown) can be formed on the dielectric layer 408. The mask can be patterned using known photolithography techniques. Portions of the mask can be retained to protect the underlying and desired portions of the dielectric layers 406, 408. The removed portions of the mask can be perpendicularly aligned with the aligned VIA recess 419. An etchant can remove the unwanted portions of the dielectric layers 406, 408, thus forming the VIA trench 413. The mask can then be removed. Different known etching techniques can be used to form tapered, angled, or VIA trench 413 sidewalls relative to the xz plane, or to form VIA trench 413 sidewalls orthogonal to the xy plane.

[0112] Figure 18Manufacturing stage 334 of an IC device manufacturing method according to various embodiments of the present invention is depicted. In stage 334, a VIA 420 is formed within a VIA trench 413 and on a dielectric layer 402 or on a conductor or metal layer 404. In some embodiments, stage 334 may be performed prior to stage 304 or 312, such that a switch pad 202 or a switch pad layer 202' is not formed within the VIA trench 413.

[0113] The VIA 420 can be formed within the VIA trench 413 by adding or depositing conductive material. In an exemplary embodiment, a mask (not shown) may be formed on the upper dielectric layer 408. The mask may be patterned using known photolithography techniques to form an opening above the VIA trench 413. Conductive material may be electroplated or otherwise deposited within the VIA trench 413 that contacts the sidewalls of the VIA recess 419 of the MC electrode 106 and contacts the dielectric layer 402 or the conductor or metal layer 404. The mask may be removed, and chemical mechanical polishing (CMP) may planarize the top surface of the VIA 420 with the top surface of the dielectric layer 408.

[0114] Figure 19 Manufacturing stage 335 of an IC device manufacturing method according to various embodiments of the present invention is depicted. In stage 335, a dielectric layer 414 is formed on a dielectric layer 408 and a conductor 417 (if formed within the dielectric layer 414). In some implementations, stage 335 may be the same as stage 308 or stage 318.

[0115] Conductors 417 may be formed within dielectric layer 414. Wiring trenches may be formed within dielectric layer 414 using a subtraction technique, wherein unwanted portions of dielectric layer 414 are removed to form a wiring pattern while retaining desired portions of dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on dielectric layer 414. The mask may be patterned using known photolithography techniques. An etchant may remove unwanted portions of dielectric layer 414. The mask may be removed to expose portions of the upper surface of dielectric 408 and the upper surface of VIA 420.

[0116] Conductors 417 can be formed within dielectric layer 414 using additive techniques, wherein conductive material is added or deposited within wiring trenches in dielectric layer 414. In an exemplary embodiment, a mask (not shown) may be formed on upper dielectric layer 414. The mask may be patterned using known photolithography techniques to remove portions above the wiring trenches. Conductive material may be electroplated or otherwise deposited within the wiring trenches in dielectric layer 414 on the exposed lower portion of VIA 420. The mask may be removed, and CMP may planarize the top surface of wiring 417 and the upper surface of dielectric layer 414.

[0117] Figure 20A method 700 for writing data to a vertical resistive memory array 100 according to various embodiments of the present invention is depicted. Method 700 may be implemented by a controller 500, a controller unit within a processor, or other known memory array controller. Method 700 begins at block 702 and may continue to receive requests to write data values ​​(block 703). For example, controller 500 may receive a request to write data values ​​(e.g., write data values) from a processor or other requesting device. (High "1" or low "0") to a specific individual cell.

[0118] Method 700 may further determine whether the data value is associated with the HRS or LRS (blocks 704, 706). For example, if the data value is a high "1", the LRS is indicated, and if the data value is a low "0", the HRS is indicated. Therefore, if the data value associated with a write request is a high "1", the controller 500 determines that it needs to program the vertical resistive memory cell 210 in the LRS. Similarly, if the data value associated with a write request is a low "0", the controller 500 determines that it needs to program, maintain, etc., the vertical resistive memory cell 210 in the HRS.

[0119] If the LRS has been determined by applying a high write voltage to the vertical resistive memory cell 210, then method 700 may continue (block 708). For example, controller 500 applies a voltage corresponding to the high write voltage at SC electrode 104 to MC electrode 106 (block 712) and applies a ground / low voltage to the post electrode 204 associated with SC electrode 104 (block 710). Alternatively, controller 500 may apply a ground or low voltage to MC electrode 106, corresponding to the ground or low voltage at SC electrode 104, and apply a high voltage to post electrode 204.

[0120] Method 700 can continue to program each of those cells 230 in the LRS by the corresponding current of the corresponding cell 230 within the vertical resistive memory cell 210 (to resolve any inconsistencies in CF 206 formation) so that they effectively store the data value high “1” (box 714).

[0121] If the HRS has been determined by applying a low write voltage, a ground voltage, etc., to the vertical resistive memory cell 210, then method 700 may continue (block 716). For example, controller 500 applies a ground / low voltage to MC electrode 106, which corresponds to a ground or low write voltage at SC electrode 104 (block 720), and applies a ground / low voltage to the post electrode 204 associated with SC electrode 104 (block 718). Alternatively, controller 500 may apply a ground voltage or a low voltage to MC electrode 106 (which corresponds to a ground voltage or low voltage at SC electrode 104), and may apply a low voltage or a ground voltage to post electrode 204.

[0122] Method 700 may continue to program each of those cells 230 (subject to any inconsistencies in CF 206) in the HRS with a corresponding low current or no current through the corresponding cells 230 within the vertical resistive memory cell 210, such that they effectively store the data value low "0" (box 722). Method 700 may end at box 724.

[0123] It should be understood that the controller 500 can receive a request to store a specific data value in a single or specific cell, and can use the data value to program cell 230 in the vertical resistive memory cell 210.

[0124] Figure 21 A method 750 for reading data from a vertical resistive memory array according to various embodiments of the present invention is depicted. Method 750 may be implemented by controller 500, a controller unit within a processor, or other known memory array controller. Method 750 begins at block 752 and may continue to receive requests to read data values ​​(block 754). For example, controller 500 may receive requests to read data values ​​(e.g., a high "1" or low "0" from a specific individual cell).

[0125] Method 750 may further determine the resistance of each cell 230 within the vertical resistive memory cell 210. In an exemplary embodiment, the resistance of each 230 within the vertical resistive memory cell 210 may be determined by setting the memory bank iteration variable “x” to equal 0 (block 756).

[0126] Method 750 may continue to apply a read voltage to the ReRAM cell "x" within the vertical resistive memory cell 210 (block 758). For example, controller 500 applies a voltage to MC106 such that the corresponding read voltage is applied at the SC electrode "x" and a low / ground voltage is applied to the cylinder electrode 204. Alternatively, controller 500 applies a read voltage to the cylinder electrode and applies a ground / low potential at the SC electrode "x".

[0127] Method 750 may continue to sense the current through the ReRAM cell "x" within the vertical resistive memory cell 210 (block 760). For example, controller 500 measures or senses the current through the ReRAM cell "x" as a result of the applied read voltage.

[0128] Method 750 can further determine the resistance of the ReRAM cell "x" within the vertical resistive memory cell 210 from the sensed current through the ReRAM cell "x" (block 762). For example, controller 500 determines the resistance of the ReRAM cell "x" from the sensed current through the ReRAM cell "x".

[0129] Method 750 can then proceed to determine whether ReRAM cell "x" is the last cell within vertical resistive memory cell 210 (block 764). If ReRAM cell "x" is not the last cell within vertical resistive memory cell 210, the memory iteration variable "x" is incremented (block 766), and method 750 returns to block 758 until the resistance of each cell 230 in vertical resistive memory cell 210 has been determined. As depicted, the loops 758, 760, 762, 764, and 766 can be executed sequentially by applying the loops of blocks 758, 760, 762, 764, and 766. Alternatively, such loops can be executed in parallel to simultaneously determine the corresponding resistance of each of the cells 230 within vertical resistive memory cell 210.

[0130] Method 750 can further combine the determined resistances of the ReRAM cells within the vertical resistive memory cell 210 (block 768). For example, controller 500 can calculate the average resistance of the determined resistances of the ReRAM cells within the vertical resistive memory cell 210, controller 500 can calculate the median resistance of the determined resistances of the ReRAM cells within the vertical resistive memory cell 210, and controller 500 can calculate the pattern resistance of the determined resistances of the ReRAM cells within the vertical resistive memory cell 210. In a specific embodiment, controller 500 can calculate a trimmed intermediate resistance of the determined resistances of the ReRAM cells within the vertical resistive memory cell 210, wherein, in determining the trimmed intermediate resistance value, a predetermined amount or percentage of the highest determined resistance and / or a predetermined amount or percentage of the lowest determined resistance are discarded. For example, if there are ten ReRAM cells 230 in the vertical resistive memory cell 210, controller 500 can discard or otherwise discard the highest and lowest determined resistances of the group of ReRAM cells 230 and calculate the average resistance over eight value ranges. The combined resistance values ​​(e.g., average, median, mode, trimmed average, etc.) determined in box 768, which combine the determined resistance values ​​of each ReRAM cell 230 within the vertical memory cell or group, are defined herein as combined resistance.

[0131] Method 750 may further determine whether the combined resistance is above or below a predetermined threshold (block 770). The predetermined threshold may be an expected or theoretical resistance measure associated with the ReRAM cells 230 in the vertical resistive memory cell 210, wherein if the combined resistance is above the threshold, the weighted, majority, etc., cells 230 within the vertical resistive memory cell 210 are substantially programmed in the HRS, and if the combined resistance is below the threshold, the cells 230 within the vertical resistive memory cell 210 are substantially programmed in the LRS.

[0132] If the combined resistance is below a threshold, then method 750 can continue to effectively determine that the vertical resistive memory cell 210 stores a data value associated with the LRS (block 772). For example, if the combined resistance is below the threshold, controller 500 can determine that the vertical resistive memory cell 210 stores a high "1". Method 750 can then continue to return the data value associated with the LRS to the requesting device (block 774). For example, controller 500 can return a high "1" data value to the requesting device (e.g., a processor, etc.).

[0133] If the combined resistance is above a threshold, then method 750 can continue to effectively determine that the vertical resistive memory cell 210 stores a data value associated with the HRS (box 776). For example, if the combined resistance is above a threshold, controller 500 can determine that the vertical resistive memory cell 210 stores a low "0". Method 750 can then continue to return the data value associated with the LRS to the requesting device (box 778). For example, controller 500 can return a high "1" data value to the requesting device (e.g., a processor, etc.).

[0134] Method 750 may continue to reset cell 230 within vertical resistive memory cell 210 upon request for a reset operation (block 780). For example, controller 500 may receive a reset request. Controller 500 may then reset cell 230 within vertical resistive memory cell 210 by, for example, applying a reset voltage to the associated SC electrode 104 and applying a ground / low voltage to the shared pillar electrode 204. Method 750 may end at block 782. Alternatively, controller 500 may reset cell 230 within vertical resistive memory cell 210 by, for example, applying a reset voltage to pillar electrode 204 and applying a ground / low voltage to the associated SC electrode 104. Method 750 may end at block 782.

[0135] It should be understood that the controller 500 can receive a request to return a specific data value in a single or specific cell, and can cause cell 230 in the vertical resistive memory cell 210 to identify a common data value stored in the vertical resistive memory cell 210 and return that value to the requesting device.

[0136] Figure 22A method 850 for reading data from a vertical resistive memory array according to various embodiments of the present invention is depicted. Method 850 may be implemented by a controller 500, a controller unit within a processor, or other known memory array controller. Method 850 begins at block 852 and may continue to receive requests to read data values ​​(block 854). For example, controller 500 may receive a request to read data values ​​(e.g., read data values ​​from a processor or other requesting device, indicated by a high "1" or low "0" from a specific individual cell).

[0137] Method 850 can then proceed to determine the resistance across the vertical resistive memory cell 210. This can be achieved by applying a read voltage to each SC electrode 104 of the cell 230 within the vertical resistive memory cell 210 (block 856). For example, controller 500 applies a voltage to MC 106 such that the corresponding read voltage is applied at each SC electrode 104 of the cell 230 within the vertical resistive memory cell 210.

[0138] Method 850 may continue to sense the current through the vertical resistive memory cell 210 (block 858). For example, controller 500 measures or senses the current through the vertical resistive memory cell 210 due to the read voltage applied at each SC electrode of cell 230 within the vertical resistive memory cell 210.

[0139] Method 850 can further determine the equivalent resistance of the vertical resistive memory cell 210 from the sensed current through the vertical resistive memory cell 210 (block 860). For example, controller 500 determines the equivalent resistance of the vertical resistive memory cell 210 from the sensed current through the vertical resistive memory cell 210.

[0140] Method 850 can then further determine whether the equivalent resistance is higher or lower than a predetermined threshold (box 862). The predetermined threshold may be an expected or theoretical resistance measure associated with the ReRAM cells 230 in the vertical resistive memory cell 210, wherein if the equivalent resistance is higher than the threshold, the weighted, majority, etc., cells 230 within the vertical resistive memory cell 210 are substantially programmed in the HRS, and if the equivalent resistance is lower than the threshold, the cells 230 within the vertical resistive memory cell 210 are substantially programmed in the LRS.

[0141] If the equivalent resistance is below a threshold, then method 850 can continue to effectively determine that the vertical resistive memory cell 210 stores a data value associated with the LRS (box 864). For example, if the equivalent resistance is below the threshold, controller 500 can determine that the vertical resistive memory cell 210 stores a high "1". Method 850 can continue to return the data value associated with the LRS to the requesting device (box 866). For example, controller 500 can return a high "1" data value to the requesting device (e.g., a processor, etc.).

[0142] If the equivalent resistance is higher than a threshold, then method 850 can continue to effectively determine that the vertical resistive memory cell 210 stores a data value associated with the HRS (box 868). For example, if the equivalent resistance is higher than the threshold, controller 500 can determine that the vertical resistive memory cell 210 stores a low "0". Method 850 can then continue to return the data value associated with the LRS to the requesting device (box 870). For example, controller 500 can return a high "1" data value to the requesting device (e.g., a processor, etc.).

[0143] Method 850 may continue to reset cell 230 within vertical resistive memory cell 210 upon request for a reset operation (block 872). For example, controller 500 may receive a reset request. Controller 500 may then reset cell 230 within vertical resistive memory cell 210 by, for example, applying a reset voltage to the associated SC electrode 104 and applying a ground / low voltage to the shared pillar electrode 204. Alternatively, controller 500 may reset cell 230 within vertical resistive memory cell 210 by, for example, applying a reset voltage to pillar electrode 204 and applying a ground / low voltage to the associated SC electrode 104. Method 750 may end at block 782. Method 850 may end at block 874.

[0144] It should be understood that the controller 500 can receive a request to return a specific data value in a single or specific cell, and can cause the vertical resistive memory cell 210 to be read in order to identify the common data value stored in the vertical resistive memory cell 210 and return that value to the requesting device.

[0145] Figure 23 A method 800 for manufacturing an IC device including a vertical resistive memory array 100 according to various embodiments of the present invention is described. The method 800 can be used to manufacture IC devices such as processors, memories, ASICs, FPGAs, etc.

[0146] Method 800 begins at frame 802 and continues to form a first dielectric layer (frame 804). For example, dielectric layer 4061 is formed on dielectric layer 402, conductor or metal layer 404, etc.

[0147] Method 800 may continue to form a first wiring and electrode layer on the first dielectric layer (box 806). For example, wiring and electrode pattern 2501 is formed on dielectric layer 4061.

[0148] Method 800 may continue to form a second dielectric layer on the first wiring and electrode layer and on the first dielectric layer (box 808). For example, dielectric layer 4062 is formed on wiring and electrode pattern 2501 and dielectric layer 4061.

[0149] Method 800 may continue to form a second wiring and electrode layer on the second dielectric layer (box 810). For example, wiring and electrode pattern 2502 is formed on dielectric layer 4062. Pillar recesses associated with the SC electrodes of the first wiring and electrode layer may be vertically aligned with pillar recesses associated with the SC electrodes of the second wiring and electrode layer (box 812). For example, pillar recess 2521 associated with the SC electrode 1041 of wiring and electrode pattern 2501 may be vertically aligned with pillar recess 2522 associated with the SC electrode 1042 of the second wiring and electrode pattern 2502. VIA recesses associated with the MC electrodes of the first wiring and electrode layer may be vertically aligned with VIA recesses associated with the SC electrodes of the second wiring and electrode layer (box 814). For example, VIA recess 4191 associated with the MC electrode 1061 of wiring and electrode pattern 2501 may be vertically aligned with VIA recess 4192 associated with the MC electrode 1062 of the second wiring and electrode pattern 2502.

[0150] Method 800 may continue to form pillar trenches through the first wiring and electrode layer and through the second wiring and electrode layer, thereby exposing the pillar sidewalls of the SC electrodes in the first wiring and electrode layer and the pillar sidewalls of the SC electrodes in the second wiring and electrode layer (box 816). For example, pillar trench 412 is formed through wiring and electrode patterns 2501, 2502, dielectric layer 4062, and dielectric layer 4061. Pillar trench 412 exposes the pillar sidewalls 2541 of SC electrode 1041 and 2542 of SC electrode 1042. Pillar trench 412 may also expose a portion of the underlying dielectric layer 402, a portion of the underlying conductor or metal layer 404, a portion of the underlying conductor or wire, etc.

[0151] Method 800 may further form a switch pad (block 818) on the sidewall of the post trench. For example, switch pad 202 is formed on the sidewall of post trench 412. Switch pad 202 may be further formed on the lower surface of post trench 412, or in other words, on the portion of dielectric layer 402 exposed by post trench 412. The switch pad is connected to the post sidewall of the SC electrode of the first wiring and electrode layer and the post sidewall of the SC electrode of the second wiring and electrode layer (block 820). For example, switch pad 202 may contact the exposed post sidewall 2541 of SC electrode 1041 and also contact the exposed post sidewall 2542 of SC electrode 1042.

[0152] Method 800 may continue to form VIA trenches through the first wiring and electrode layer and the second wiring and electrode layer, thereby exposing the sidewalls of the MC electrodes in the first wiring and electrode layer and the sidewalls of the MC electrodes in the second wiring and electrode layer (box 822). For example, a VIA trench 413 is formed through wiring and electrode patterns 2501, 2502, dielectric layer 4062, and dielectric layer 4061. VIA trench 413 exposes the sidewalls of the VIA recess 419 of MC electrode 1061 and the sidewalls of the VIA recess 419 of MC electrode 1062. VIA trench 413 may also expose a portion of the underlying dielectric layer 402, a portion of the underlying conductor or metal layer 404, a portion of the underlying conductor or wire, etc.

[0153] Method 800 may continue to form a pillar electrode (frame 824) on the switch pad within the pillar groove. For example, a pillar electrode 204 is formed on the switch pad 202 within the pillar groove 412.

[0154] Method 800 may continue to form a VIA within the VIA trench (box 826). For example, a VIA 420 is formed within a VIA trench 413. The VIA is connected to the VIA recess sidewall of the MC electrode of the first wiring and electrode layer and the VIA recess sidewall of the MC electrode of the second wiring and electrode layer (box 828). For example, VIA 420 contacts the exposed VIA recess 419 sidewall of the MC electrode 1061 and also contacts the exposed VIA recess 419 sidewall of the MC electrode 1062.

[0155] Method 800 may continue to form a first wiring feature of a top dielectric layer having contact pillar electrodes and a second wiring feature of a contact VIA within the top dielectric layer (box 830). For example, dielectric layer 408 is formed on dielectric layer 4062. Line 416 is formed within dielectric layer 408, contacting pillar electrode 204, and line 417 is formed within dielectric layer 408, contacting VIA 420. Method 800 may end at box 832.

[0156] It should be understood that the descriptions or Figure 23The manufacturing stages in the various boxes depicted do not necessarily occur in the presented order, but can be performed in a sequence that efficiently manufactures IC devices, including vertical resistive memory arrays 100 as described herein.

[0157] The accompanying drawings and description depict and illustrate embodiments of the invention, as well as its features and components. Those skilled in the art will understand that any specific terminology used in this specification is merely for convenience, and therefore the invention should not be limited to the specific processes identified and / or implied by such terminology. Accordingly, it is intended that the embodiments described herein be considered illustrative rather than restrictive in all respects, and that the scope of the invention be determined with reference to the appended claims.

[0158] The exemplary methods and techniques described herein can be used for the manufacture or verification of IC chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads attached to a motherboard or other more advanced carrier) or in a multi-chip package (e.g., a ceramic carrier with either surface interconnects or buried interconnects, or both). The chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. As a non-limiting example, the final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with numerous components (e.g., displays, keyboards or other input devices, and / or central processing units).

[0159] The terms such as “vertical” and “horizontal” used herein are used to establish a reference frame by way of example rather than limitation. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane or surface of the dielectric layer 402, metal or conductor layer 404, etc., regardless of the actual spatial orientation of the IC device. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms such as “on,” “above,” “below,” “side” (as in “sidewall”), “higher,” “lower,” “over,” “top,” “under,” “beneath”, etc., are defined relative to a horizontal plane. It should be understood that various other reference frames may be used to describe the invention without departing from the scope of the invention.

Claims

1. A vertical resistive memory array, comprising: A front-vertical resistive memory cell includes a front-resistive random access memory (RRAM) column and a first vertically stacked electrode group connected to a first side of the front RRAM column. The front RRAM post includes a first post electrode and a first switch pad, the first switch pad being located around and contacting the sidewall perimeter of the first post electrode; and The first vertically stacked electrode group includes a first upper single-cell SC electrode and a first lower SC electrode. The first upper SC electrode is in contact with a first upper high-resistance element HRE and is in contact with the front RRAM post through contact with the first switch pad. The first lower SC electrode is in contact with the first lower HRE and is in contact with the front RRAM post through contact with the first switch pad.

2. The vertical resistive memory array according to claim 1, wherein, The front vertical resistive memory cell also includes: The second vertically stacked electrode group is connected to the second side of the front RRAM post. The second vertically stacked electrode group includes a second upper SC electrode and a second lower SC electrode. The second upper SC electrode contacts the second upper HRE and contacts the front RRAM post through contact with the first switch pad. The second lower SC electrode contacts the second lower HRE and contacts the front RRAM post through contact with the first switch pad.

3. The vertical resistive memory array according to claim 2, further comprising: A rear vertical resistive memory cell, comprising a rear RRAM pillar and a third vertical stacked electrode group connected to a first side of the rear RRAM pillar; The rear RRAM post includes a second post electrode and a second switch pad surrounding the sidewall perimeter of the second post electrode; as well as The third vertically stacked electrode group includes a third upper SC electrode and a third lower SC electrode. The third upper SC electrode is in contact with the third upper HRE and is in contact with the rear RRAM post by contacting the second switch pad. The third lower SC electrode is in contact with the third lower HRE and is in contact with the rear RRAM post by contacting the second switch pad.

4. The vertical resistive memory array according to claim 3, wherein, The rear vertical resistive memory cell also includes: A fourth vertically stacked electrode group is connected to the second side of the rear RRAM pillar. The fourth vertically stacked electrode group includes a fourth upper SC electrode and a fourth lower SC electrode. The fourth upper SC electrode contacts the fourth upper HRE and contacts the rear RRAM pillar through contact with the second switch pad. The fourth lower SC electrode contacts the fourth lower HRE and contacts the rear RRAM pillar through contact with the second switch pad.

5. The vertical resistive memory array according to claim 4, comprising: The first upper multi-unit MC electrode is connected to the first upper HRE and also to the third upper HRE.

6. The vertical resistive memory array according to claim 5, comprising: The second upper MC electrode is connected to the second upper HRE and also to the fourth upper HRE.

7. The vertical resistive memory array according to claim 6, comprising: The first lower MC electrode is connected to the first lower HRE and also to the third lower HRE.

8. The vertical resistive memory array according to claim 7, comprising: The second lower MC electrode is connected to the second lower HRE and also to the fourth lower HRE.

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