Glitch filter system

Abstract

One example includes a glitch filter system (100). The system (100) includes an input stage (102) to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element (104) receives the first digital signal and the second digital signal and provides a third digital signal in a first logic state in response to each of the first digital signal and the second digital signal having a second logic state opposite the first logic state. An output latch (106) provides an output signal in a second logic state in response to the first logic state of the third digital signal. The output latch (106) also receives the first digital signal and the second digital signal to maintain the first logic state of the third digital signal in response to one of the first digital signal and the second digital signal changing from the second logic state to the first logic state.

Description

Technical Field

[0001] This specification generally relates to electronic circuits, and more specifically to glitch filter systems. Background Technology

[0002] Computer systems typically operate based on digital signals with binary logic states. In such systems, which implement Complementary Metal-Oxide-Semiconductor (CMOS) circuits, transistors can switch between active and inactive states based on logic signals. However, in high-speed applications, such as those based on high-speed clock signals, the time spent switching between states can lead to metastability in a given logic signal, resulting in unexpected states or insufficient amplitude. Glitch filters and other circuitry can be implemented to mitigate the metastability of a given logic signal. However, conflicting design considerations and logic processing can make implementing glitch filters difficult in some CMOS circuit applications. Summary of the Invention

[0003] One example includes a glitch filter system. The system includes an input stage for receiving an input signal, a first output for providing a first digital signal, and a second output for providing a second digital signal. A C element receives the first and second digital signals, and provides a third digital signal in the first logic state in response to each of the first and second digital signals having a second logic state opposite to the first logic state. An output latch provides an output signal in the second logic state in response to the first logic state of the third digital signal. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.

[0004] Another example includes a glitch filter system. This system includes an input stage configured to receive an input signal and generate a first digital signal and a second digital signal, which are separate, corresponding delayed versions of the input signal. The system also includes a C element configured to receive the first and second digital signals, and in response to a logic state of each of the first and second digital signals being a first state, to set the logic state of a third digital signal at a control node to a second state, opposite to the first state. The system further includes an output latch coupled to the C element and configured to set the logic state of the output signal to the first state in response to the second state of the third digital signal. The output latch may be further configured to maintain the logic state of the third digital signal at the control node in the second state in response to the first and second digital signals having separate, corresponding logic states. The output latch may be configured to override the C element when setting the logic state of the third digital signal.

[0005] Another example includes an integrated circuit (IC) chip. The IC includes a clock system comprising an oscillator circuit configured to generate an input signal and a glitch filter system. The glitch filter system includes an input stage having an input for receiving the input signal, a first output for providing a first digital signal, and a second output for providing a second digital signal. The first and second digital signals correspond to separate, respective delayed versions of the input signal. The glitch filter system also includes a C element having a first input for receiving the first digital signal and a second input for receiving the second digital signal. The C element further includes an output for providing a third digital signal. A third digital signal in the first logic state can be provided in response to each of the first and second digital signals having a second logic state opposite to the first logic state. The glitch filter system further includes an output latch having a first input coupled to the output of the C element and an output for providing an output clock signal in the second logic state in response to the first logic state of the third digital signal. The output latch further includes a second input terminal for receiving a first digital signal and a third input terminal for receiving a second digital signal, so as to maintain the first logic state of the third digital signal in response to one of the first digital signal and the second digital signal changing from a second logic state to a first logic state. Attached Figure Description

[0006] Figure 1 An example of a glitch filter system is shown.

[0007] Figure 2 An example of a glitch filter circuit is shown.

[0008] Figure 3 An example of a clock system is shown. Detailed Implementation

[0009] This specification relates generally to electronic circuits, and more specifically to glitch filter systems. Glitch filter systems can be implemented, for example, in high-speed complementary metal-oxide-semiconductor (CMOS) circuits, such as clock or data circuits. Therefore, glitch filter systems can mitigate glitches that may occur during the generation of digital signals (e.g., clock signals) due to potential metastability in switching. A glitch filter system may include an input stage that provides a first digital signal and a second digital signal in response to an input signal. For example, the input signal may be provided as an oscillating digital signal from a local oscillator circuit, and the first and second digital signals may be separate, correspondingly delayed versions of the input signal. The glitch filter system also includes a C-element (e.g., a Muller C-element) that can operate as a modified inverter circuit that can provide a third digital signal at a control node, the third digital signal having a first logic state in response to both the first and second digital signals having a second logic state opposite to the first logic state.

[0010] The glitch filter system also includes an output latch. The output latch may include an output inverter that inverts a third digital signal to generate an output signal, such as inverting a first logic state of the third digital signal to provide an output signal in a second logic state. The output latch also includes a feedback inverter configured to control the logic state of the third digital signal based on the logic state of the output signal in response to the first and second digital signals having different logic states, and may respond to the first digital signal DIG. A Second digital signal DIG B The first and second digital signals are deactivated because they have the same logic state. Therefore, a feedback inverter can maintain the logic state of a third digital signal in response to a change in the logic state of one of the first and second digital signals. For example, a feedback inverter includes an inverter with a common output and controlled by corresponding first and second digital signals. The inverters can be arranged between transistors controlled by the output signal. Therefore, the feedback inverter can maintain the logic state of the output signal at the control node in response to a change in the logic state of one of the first and second digital signals relative to the other.

[0011] For example, an output latch can be configured to override the C element while maintaining the logic state of a third digital signal. As described herein, the term "override" in relation to controlling the state based on an output latch (e.g., a feedback inverter) and a C element refers to the ability of the output latch to override the C element while setting the logic state of the third digital signal at a control node, in the event that the output latch and the C element compete to set different logic states of the third digital signal. For example, the feedback inverter of the output latch may include a transistor larger than the transistor of the C element. Therefore, activation of the transistor in the feedback inverter can override the transistor of the C element that competes to control the logic state of the third digital signal at the control node.

[0012] Figure 1 An example of a glitch filter system 100 is shown. The glitch filter system 100 can be implemented, for example, in a high-speed complementary metal-oxide-semiconductor (CMOS) circuit such as a clock circuit. As described herein, the glitch filter system 100 can mitigate glitches that may occur during the generation of digital signals (e.g., clock signals) due to the potential metastability of switching.

[0013] The glitch filter system 100 includes an input stage 102 configured to provide a first digital signal DIG in response to an input signal IN. A Second digital signal DIG B For example, the input signal IN can be provided as a signal from a local oscillator circuit ( Figure 1 (Not shown in the example) provides an oscillating digital signal. As an example, input stage 102 may include one or more delay elements that can provide a first digital signal DIG. A Second digital signal DIG B As a separate, corresponding delayed version of the input signal IN, the glitch filter system 100 also includes a C element (e.g., a Mueller C element) 104, which can operate as a modified inverter circuit based on the first digital signal DIG. A Second digital signal DIG B To provide the third digital signal DIG C Due to the inverting function of C element 104, C element 104 can respond to the first digital signal DIG. A Second digital signal DIG B Both have a second logic state opposite to the first logic state, thus providing a third digital signal DIG that is in the first logic state. CAs described herein, the terms "first logical state" and "second logical state" are arbitrary relative to each other and are used to specify binary logical states that are opposite to each other. For example, the first logical state can be logical 1 and the second logical state can be logical 0, or the first logical state can be logical 0 and the second logical state can be logical 1.

[0014] The glitch filter system 100 further includes an output latch 106. The output latch 106 may include an output inverter that can convert the third digital signal DIG... C Inverting to generate the output signal, Figure 1 In the example, this is shown as the signal OUT. For example, the output inverter of output latch 106 can convert the third digital signal DIG. C The first logic state is inverted to provide the output signal OUT in the second logic state. Figure 1 In the example, the output latch 106 includes a feedback inverter 108, which is configured to control the third digital signal DIG based on the logic state of the output signal OUT. C The logical state. For example... Figure 1 As shown in the example, the first digital signal DIG A Second digital signal DIG B It is provided to the feedback inverter 108. For example, the feedback inverter 108 may respond to the first digital signal DIG. A Second digital signal DIG B It has different logic states to control the third digital signal DIG. C The logic state, and can respond to the first digital signal DIG. A Second digital signal DIG B They are deactivated because they have the same logical state.

[0015] As an example, the feedback inverter 108 can respond to the first digital signal DIG. A Second digital signal DIG B One of them changes the logic state relative to the other to drive the third digital signal DIG. C The logic state. As a result, the feedback inverter 108 can respond to a change in the logic state of either the first digital signal or the second digital signal to change the logic state of the third digital signal DIG. C The logic state is maintained in the same state as that controlled by element C 104. As an example, the feedback inverter 108 can be configured to maintain the third digital signal DIG. CThe logic state is overridden when controlling the C element 104. For example, the transistor of the feedback inverter 108 can be manufactured as a larger transistor than the transistor of the C element to overridden the C element 104 to control the third digital signal DIG. C The logical state.

[0016] Therefore, based on the arrangement of the feedback inverter 108 described herein, the glitch filter system 100 can substantially reduce the glitches in the third digital signal DIG. C The metastability of the logic state of the output signal OUT is mitigated by reducing the metastability of the logic state of the output signal OUT. For example, in an alternative glitch filter system including a C element and a feedback inverter, the C element is designed as an overriding feedback element so that the C element can change the logic state of the signal output from the C element, while the feedback inverter latches and inverts the logic state of the output signal. By designing the C element to overridden the feedback inverter, such as based on the input stage delay being approximately equal to the switching time between state changes of the input signal, the output latch can exhibit greater metastability during the switching of the output signal. As described herein, the term "approximate" can include some deviation from the exact value (e.g., + / - 5%). However, because the glitch filter system 100 implements the feedback inverter 108 as an overriding C element 104, the metastability switching window of the output signal OUT can be significantly reduced. Furthermore, by using the first digital signal DIG... A Second digital signal DIG B To control the operation of the feedback inverter 108, the feedback inverter 108 can be controlled by a first digital signal DIG having the same logic state. A Second digital signal DIG B And be deactivated to activate the third digital signal DIG. C The control of the logic state is returned to element C 104. Therefore, the feedback inverter 108 in the glitch filter system 100 can alleviate the glitches in the third digital signal DIG. C This reduces the metastability of the output signal OUT, while still allowing element C to respond to the first digital signal DIG. A Second digital signal DIG B The third digital signal DIG has the same logical state to change. C The logical state.

[0017] Figure 2 An example of a glitch filter system 200 is shown. The glitch filter system 200 can correspond to... Figure 1 The example shows the glitch filter system 100. Therefore, similar to that described above, the glitch filter system 200 can mitigate glitches that may occur during the generation of digital signals (e.g., clock signals) due to the potential metastability of switching.

[0018] The glitch filter system 200 includes an input stage 202 that receives the input signal IN. For example, the input signal IN can be received from a local oscillator circuit ( Figure 2 (Not shown in the example) The oscillating digital signal is provided. Input stage 202 includes a first buffer 204, a delay element 206, and a second buffer 208. The input signal IN is provided through the first buffer 204 to provide the second digital signal DIG. B The second digital signal, DIG. B The first digital signal DIG is provided through the delay element 306 and the second buffer 208. A Each of buffers 204 and 208 can have an inherent switching delay, and delay element 306 can be configured or programmed to have a predetermined amount of delay. Therefore, the first digital signal DIG... A Second digital signal DIG B Each can be a separate, corresponding delayed version of the input signal IN.

[0019] The glitch filter system 200 also includes a C-element (e.g., a Mueller C-element) 210, which can operate as a modified inverter circuit. The C-element 210 includes a first P-channel field-effect transistor (P-FET) P1, a second P-FET P2, a first N-channel field-effect transistor (N-FET) N1, and a second N-FET N2. The first P-FET P1 directs the high voltage rail V... DD Interconnected to the second P-FET P2, and controlled by the second digital signal DIG. B Control. The second P-FET P2 interconnects the first P-FET P1 with the control node 212, and is controlled by the first digital signal DIG. A Control. The first N-FET N1 interconnects the control node 212 with the second N-FET N2, and is controlled by the first digital signal DIG. A Control. The second N-FET N2 interconnects the first N-FET N1 to a low-voltage rail (e.g., ground) and is controlled by a second digital signal DIG. B control.

[0020] Therefore, based on the arrangement of C element 210, C element 210 can operate as a modified inverter in response to the first digital signal DIG. A Second digital signal DIG B Both have a second logic state that is the opposite of the first logic state, while a third digital signal DIG in the first logic state is provided at control node 212. C For example, if the digital signal DIG A and DIG BIf both are in a logic 0 state, then N-FETs N1 and N2 are deactivated, and P-FETs P1 and P2 are activated to couple control node 212 to the high voltage rail V. DD This provides a third digital signal DIG in a logic 1 state. C Similarly, if the digital signal DIG A and DIG B If both are in a logic 1 state, then P-FETs P1 and P2 are deactivated, and N-FETs N1 and N2 are activated to couple control node 212 to the low voltage rail to provide the third digital signal DIG in a logic 0 state. C .

[0021] The glitch filter system 200 further includes an output latch 214. The output latch 214 includes an output inverter 216 that interconnects the control node 212 with an output node 218, at which an output signal OUT is provided. Therefore, the output inverter 216 can convert the third digital signal DIG... C The logic state is inverted to provide an output signal OUT at output node 218. Furthermore, output latch 214 includes a feedback inverter 220 disposed between output node 218 and control node 212. Figure 2 For example, feedback inverter 220 receives the first digital signal DIG. A Second digital signal DIG B The output signal OUT is used as an input. Therefore, the feedback inverter 220 can be based on the logic state of the output signal OUT and the first digital signal DIG. A Second digital signal DIG B To control the third digital signal DIG C The logical state.

[0022] The feedback inverter 220 includes a first P-FET P3, a second P-FET P4, and a third P-FET P5, as well as a first N-FET N3, a second N-FET N4, and a third N-FET N5. The first P-FET P3 directs the high voltage rail V... DDInterconnected to the second P-FET P4 and the third P-FET P5. The first N-FET N3 interconnects the low voltage rail with the second N-FET N4 and the third N-FET N5. The first P-FET P3 and the first N-FET N3 are each controlled by the output signal OUT. The second P-FET P4 and the third P-FET P5 interconnect the first P-FET P3 with the control node 212, and the second N-FET N4 and the third N-FET N5 interconnect the control node 212 with the first N-FET N3. The second P-FET P4 and the second N-FET N4 are controlled by the first digital signal DIG. A Controlled, and the third P-FET P5 and the third N-FET N5 are controlled by the second digital signal DIG. B Control. Therefore, the arrangement of the second P-FET P4 and the second N-FET N4, as well as the arrangement of the third P-FET P5 and the third N-FET N5, can respectively correspond to the counter inverters between the first P-FET P3 and the first N-FET N3 and have a common coupled output at the control node 212.

[0023] As described above, the feedback inverter 220 can respond to the first digital signal DIG. A Second digital signal DIG B One of them changes the logic state relative to the other, driving the third digital signal DIG at control node 212. C The logic state. As a result, the feedback inverter 220 can respond to a change in the logic state of either the first digital signal or the second digital signal to change the logic state of the third digital signal DIG. C The logic state remains the same as the state controlled by element C 210. For example, in response to the first digital signal DIG A Second digital signal DIG B Having a logic 1 state, C element 210 (e.g., through the first N-FET N1 and the second N-FET N2 of C element 210) transmits the third digital signal DIG. C The logic state is driven to logic 0. The output inverter 216 converts the third digital signal DIG... C The logic 0 state is inverted to provide an output signal OUT at logic 1. The logic 1 state of the output signal OUT also activates the first N-FET N3 of the output latch 214 and deactivates the first P-FET P3. Furthermore, the first digital signal DIG... A Second digital signal DIG BThe logic 1 state causes the N-FETs N4 and N5 to be activated and the P-FETs P4 and P5 to be deactivated. Therefore, control node 212 is driven to the low voltage rail via N-FETs N3, N4, and N5. Consequently, feedback inverter 220, along with C element 210, can also drive the third digital signal DIG. C Drive to logic 0.

[0024] Based on the arrangement of input stage 202, the second digital signal DIG B In response to a change in the logic state of the input signal IN, the first digital signal DIG... A The state was changed previously. Therefore, in response to the second digital signal DIG... B The logic state changes to logic 0, and within a short period of time defined by the delay time of the delay element 206 and the second buffer 208, the first digital signal DIG... A It has a logic 1 state. As a result, in response to the first digital signal DIG... A Second digital signal DIG B With different logic states, element C 210 stops driving the third digital signal DIG based on the deactivation of the second N-FET N2. C The logic state. In other words, C element 210 (e.g., based on the deactivated second P-FET P2) disconnects control node 212 from the high voltage rail V. DD The path between and (e.g., based on the deactivated second N-FET N2) the path between control node 212 and the low voltage rail is disconnected. However, the second digital signal DIG B The change to logic 0 does not affect the feedback inverter 220 driving the third digital signal DIG. C The logic state of the feedback inverter 220 maintains the third digital signal DIG. C The previous logic state. For example, the second digital signal DIG. B The logic 0 state causes the activation of the third P-FET P5 and the deactivation of the third N-FET N5 in the feedback inverter 220. However, the first N-FET N3 and the second N-FET N4 of the feedback inverter 220 are still activated by the first digital signal DIG. A The output signal OUT is activated to sink control node 212 to the low voltage rail, and thus the third digital signal DIG is activated. C It remains in logic 0, and thus keeps the output signal OUT in logic 1.

[0025] As described above, the transistor size (e.g., channel size) of the feedback inverter 220 can be larger than that of the transistor in the C element 210. Therefore, in response to the first digital signal DIG as described above... ASecond digital signal DIG B Since their logical states are different from each other, the feedback inverter 220 can override the drive of the control node 212, and thus override the third digital signal DIG. C The logic state. For example, the delay time of delay element 206 and second buffer 208 is related to the second digital signal DIG. B When the state changes are approximately uniform, potential race conditions may occur in C element 210 and feedback inverter 220, leading to metastable switching. However, because N-FETs N3, N4, and N5, and P-FETs P3, P4, and P5 can all have channel sizes larger than those of N-FETs N1 and N2, and P-FETs P1 and P2, feedback inverter 220 can control C element 210 to change the third digital signal DIG differently from the previously maintained logic state. C Any potential attempts at switching logic states. Therefore, in contrast to alternative glitch filter systems, the metastability window of switching C element 210 can be mitigated by overriding the transistor of C element 210 based on the larger transistor of the feedback inverter 220. Thus, glitch filter system 200 can mitigate metastability during switching between logic states compared to alternative glitch filter systems.

[0026] After a duration defined by the delay time of the delay element 206 and the second buffer 208, the first digital signal DIG... A It can also switch to logic 0, and thus switch to the second digital signal DIG. B Same logical state. Response to the first digital signal DIG. A Second digital signal DIG B Having a logic 0 state, the first digital signal DIG A Second digital signal DIG B This results in the deactivation of N-FETs N4 and N5 and the activation of P-FETs P4 and P5. However, assuming the output signal OUT initially remains in logic 1, the output signal OUT maintains the activation of the first N-FET N3 of the feedback inverter 220. Therefore, control node 212 does not have access to the high voltage rail V. DD (e.g., based on the deactivation of the first P-FET P3) or a current path to a low voltage rail (e.g., based on the deactivation of N-FETs N4 and N5). As a result, the first digital signal DIG... A The logic state changes to be related to the second digital signal DIG. B The same logic state as the feedback inverter 220 causes the C element to drive the third digital signal DIG at the control node 212, thus allowing the C element to drive the third digital signal DIG. C The logical state.

[0027] For example, based on the first digital signal DIG A Second digital signal DIG B In the logic 0 state of both, P-FETs P1 and P2 are activated, and N-FETs N1 and N2 are deactivated to bring the high voltage rail V to its normal state. DD This is provided to control node 212. Therefore, control node 212 switches to logic 1 state based on the inverting operation provided by element C 210 and the deactivation of feedback inverter 220. Output inverter 216 outputs the third digital signal DIG. C The logic 0 state is inverted to provide an output signal OUT at logic 1. The logic 1 state of the output signal OUT also activates the first N-FET N3 of the output latch 214 and activates the first P-FET P3. As a result, control node 212 is also provided with access to the high voltage rail V through P-FET P3 and P-FETs P4 and P5. DD The path. As a result, the third digital signal DIG is initially set in component C 210. C After the logic state, the feedback inverter 220 can also convert the third digital signal DIG. C Driven to logic 0. Because the feedback inverter 220 sets the third digital signal DIG at element C 210. C The logic state is deactivated beforehand, so C element 210 does not need to set the third digital signal DIG as required in some alternative glitch filter systems. C The logic state of the overriding feedback inverter 220. Therefore, as described above, the arrangement of the feedback inverter 220 provides the ability to mitigate the metastable switching of the glitch filter system 200, while also facilitating the correct operation of the C element 210 in setting the logic state of the output signal OUT.

[0028] As described above, the glitch filter system 200 can be implemented in a clock system to generate a clock signal that exhibits greater stability. Figure 3 An example of a clock system 300 is shown. The clock system 300 can be implemented in any of a variety of digital circuits, such as those used to control computer systems or wireless communication devices. As an example, the clock system 300 can be included as an integrated circuit (IC) or a part thereof. The clock system 300 includes a local oscillator 302, which can be configured as, for example, a crystal oscillator. The local oscillator 302 can generate input signals, such as an input signal IN. The clock system 300 also includes a glitch filter system 304. As an example, the glitch filter system 304 can correspond to... Figure 1 and Figure 2The corresponding example is either glitch filter system 100 or glitch filter system 200. Therefore, glitch filter system 304 can generate a clock signal CLK, which can be... Figure 1 and Figure 2 The corresponding example shows the output signal OUT. Since the glitch filter system 304 can correspond to either glitch filter system 100 or glitch filter system 200, the glitch filter system 304 can mitigate metastability switching to generate the clock signal CLK, as described above. Therefore, the clock signal CLK can be generated as a much more stable clock signal, such as compared to a clock signal generator implementing an alternative glitch filter system.

[0029] Modifications to the embodiments are possible within the scope of the claims, and other embodiments are also possible.

[0030] The term "coupling" is used throughout this specification. This term can encompass connection, communication, or signaling paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, in the first example, device A is coupled to device B; or in the second example, if intermediate component C does not substantially alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that device B is controlled by control signals generated by device A.

[0031] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) to perform that function during manufacturing by the manufacturer, and / or can be configured (or reconfigured) by the user after manufacturing to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof. Furthermore, a circuit or device described as including certain components can be configured to be coupled to these components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage sources and / or current sources) can include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and can be configured to be coupled to at least some of the passive elements and / or sources to form the structure, for example, by an end user and / or a third party, during or after manufacturing.

Claims

1. A glitch filter system, comprising: An input stage having an input terminal for receiving an input signal, a first output terminal for providing a first digital signal, and a second output terminal for providing a second digital signal, wherein the first digital signal and the second digital signal are separate, corresponding delayed versions of the input signal; A C-element has a first input terminal for receiving the first digital signal and a second input terminal for receiving the second digital signal. The C-element further has an output terminal for providing a third digital signal, wherein the third digital signal is provided in the first logic state in response to each of the first digital signal and the second digital signal having a second logic state opposite to the first logic state. as well as An output latch having a first input coupled to the output of the C element and an output for providing an output signal in a second logic state in response to a first logic state of the third digital signal, the output latch further having a second input for receiving the first digital signal and a third input for receiving the second digital signal, to maintain the first logic state of the third digital signal in response to one of the first digital signal and the second digital signal changing from the second logic state to the first logic state.

2. The system according to claim 1, wherein the output latch comprises: An output inverter configured to invert the third digital signal to generate the output signal; as well as A feedback inverter having a second input and a third input, and configured to invert the output signal in response to different logic states of the first digital signal and the second digital signal to control the logic state of the third digital signal.

3. The system of claim 2, wherein the feedback inverter includes a first transistor configured to conduct current from a high voltage rail or to a low voltage rail in response to different logic states of the first digital signal and the second digital signal to set the logic state of the third digital signal, wherein the C element includes a second transistor configured to conduct current from the high voltage rail or to the low voltage rail in response to the same logic state of each of the first digital signal and the second digital signal to set the logic state of the third digital signal, wherein the first transistor is larger than the second transistor.

4. The system according to claim 2, wherein the feedback inverter comprises: A first inverter transistor pair, controlled by the first digital signal, has an output terminal coupled to the output terminal of the C element and the input terminal of the output latch; as well as The second inverter transistor pair is controlled by the second digital signal and has an output terminal corresponding to the output terminal of the C element and the input terminal of the output latch.

5. The system of claim 4, wherein the feedback inverter further comprises: The first transistor interconnects the high voltage rail with the first inverter transistor pair and the second inverter transistor pair, and is activated by the logic low state of the output signal. as well as The second transistor interconnects the first inverter transistor pair and the second inverter transistor pair with a low voltage rail and is activated by the logic high state of the output signal.

6. The system of claim 1, wherein the input stage includes a delay element between the first digital signal and the second digital signal, the delay element being configured to delay the second digital signal relative to the first digital signal for a predetermined duration.

7. The system of claim 1, wherein the output latch includes a first transistor configured to conduct current from a high voltage rail or to a low voltage rail to set the logic state of the third digital signal, wherein the C element includes a second transistor configured to conduct current from the high voltage rail or to the low voltage rail to set the logic state of the third digital signal, wherein the first transistor is larger than the second transistor.

8. A clock system comprising the glitch filter system according to claim 1.

9. The clock system of claim 8, further comprising an oscillator circuit configured to generate the input signal, wherein the output signal is provided as a clock signal from the glitches filter system.

10. An integrated circuit, or IC, comprising the glitch filter system according to claim 1.

11. A glitch filter system, comprising: An input stage is configured to receive an input signal and generate a first digital signal and a second digital signal, the first digital signal and the second digital signal being separate, corresponding delayed versions of the input signal; Component C is configured to receive the first digital signal and the second digital signal, and in response to the logic state of each of the first digital signal and the second digital signal being a first state, to set the logic state of the third digital signal at the control node to a second state opposite to the first state. as well as An output latch, coupled to the C element and configured to set the logic state of an output signal to the first state in response to the second state of the third digital signal, the output latch being further configured to maintain the logic state of the third digital signal at the control node in the second state in response to the first digital signal and the second digital signal having separate corresponding logic states, the output latch being configured to override the C element while maintaining the logic state of the third digital signal.

12. The system of claim 11, wherein the output latch comprises: An output inverter configured to invert the third digital signal to generate the output signal; as well as A feedback inverter is configured to invert the output signal in response to different logic states of the first digital signal and the second digital signal to control the logic state of the third digital signal.

13. The system of claim 12, wherein the feedback inverter includes a first transistor configured to conduct current from a high voltage rail or to a low voltage rail to set the logic state of the third digital signal at the control node, wherein the C element includes a second transistor configured to conduct current from the high voltage rail or to the low voltage rail to set the logic state of the third digital signal at the control node, wherein the first transistor is larger than the second transistor.

14. The system of claim 12, wherein the feedback inverter comprises: A first inverter transistor pair, which is controlled by the first digital signal and has an output terminal at the control node; as well as The second inverter transistor pair is controlled by the second digital signal and has an output coupled at the control node.

15. The system of claim 14, wherein the feedback inverter further comprises: The first transistor interconnects the high voltage rail with the first inverter transistor pair and the second inverter transistor pair, and is activated by the logic low state of the output signal. as well as The second transistor interconnects the first inverter transistor pair and the second inverter transistor pair with a low voltage rail and is activated by the logic low state of the output signal.

16. An integrated circuit, i.e., an IC, including a clock system, said clock system comprising: An oscillator circuit configured to generate an input signal; as well as A glitch filter system, the glitch filter system comprising: An input stage having an input terminal for receiving the input signal, a first output terminal for providing a first digital signal, and a second output terminal for providing a second digital signal, wherein the first digital signal and the second digital signal are separate, corresponding delayed versions of the input signal; A C-element has a first input terminal for receiving the first digital signal and a second input terminal for receiving the second digital signal. The C-element further has an output terminal for providing a third digital signal, wherein the third digital signal is provided in the first logic state in response to each of the first digital signal and the second digital signal having a second logic state opposite to the first logic state. as well as An output latch has a first input coupled to the output of the C element and an output for providing an output clock signal in the second logic state in response to the first logic state of the third digital signal. The output latch further has a second input for receiving the first digital signal and a third input for receiving the second digital signal, so as to maintain the first logic state of the third digital signal in response to one of the first digital signal and the second digital signal changing from the second logic state to the first logic state.

17. The IC of claim 16, wherein the output latch comprises: An output inverter is configured to invert the third digital signal to generate the output clock signal; as well as A feedback inverter is configured to invert the output clock signal in response to different logic states of the first digital signal and the second digital signal to control the logic state of the third digital signal.

18. The IC of claim 17, wherein the feedback inverter includes a first transistor configured to conduct current from a high voltage rail or to a low voltage rail to set the logic state of the third digital signal at the control node, wherein the C element includes a second transistor configured to conduct current from the high voltage rail or to the low voltage rail to set the logic state of the third digital signal at the control node, wherein the first transistor is larger than the second transistor.

19. The IC of claim 17, wherein the feedback inverter comprises: The first inverter transistor pair is controlled by the first digital signal and has an output at the control node; as well as The second inverter transistor pair is controlled by the second digital signal and has an output terminal at the control node.

20. The IC of claim 19, wherein the feedback inverter further comprises: The first transistor interconnects the high voltage rail with the first inverter transistor pair and the second inverter transistor pair, and is activated by the logic low state of the output clock signal. as well as The second transistor interconnects the first inverter transistor pair and the second inverter transistor pair with a low voltage rail and is activated by the logic low state of the output clock signal.

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