Phase detection method and apparatus

Abstract

This invention discloses a phase detection method applied in the field of field-programmable gate array (FPGA) technology. The method includes: receiving an input pulse signal; acquiring the main sampling point of the input pulse signal; calculating a first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time interval of the main sampling point; calculating a second area formed by the waveform curve of the input pulse signal and the time axis in the subsequent unit time interval of the main sampling point; comparing the first area and the second area using a comparator to obtain a first comparison result; processing the input pulse signal through a data sampling circuit to obtain first phase information; processing the first comparison result through an error sampling circuit to obtain first error information; and calculating the first phase information and the first error information using a preset truth rule of the phase detection circuit to obtain a phase detection result.

Description

Technical Field

[0001] This invention relates to the field of field-programmable gate array technology, and more particularly to a phase detection method and apparatus. Background Technology

[0002] In the existing clock data recovery circuit structure, the phase detector obtains lag or lead information based on the equalized input signal and clock phase. The existing phase detector uses a method of directly sampling the input signal to obtain direct sampling data information, and then comparing the input signal with a reference level (including high level and low level) to obtain first sampling output error information and second sampling output error information. Based on the direct sampling data information, the first sampling output error information, the second sampling output error information, and a pre-set lead or lag calculation method, the lead or lag information of the input signal is calculated.

[0003] However, the phase detection method used in traditional phase detectors is not accurate in outputting the leading or lagging information of the phase of the input signal after detecting the input signal. Summary of the Invention

[0004] This invention provides a phase detection method and apparatus to solve the technical problem that the phase detection of input signals by phase detectors in traditional technologies is inaccurate, resulting in either leading or lagging information.

[0005] A phase detection method, comprising:

[0006] Receive input pulse signals;

[0007] Obtain the main sampling point of the input pulse signal;

[0008] Calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point;

[0009] Calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time interval after the main sampling point;

[0010] The size of the first area and the second area are compared to obtain a first comparison result. The phase detection result of the input pulse signal is output according to the first comparison result and the preset truth value rule.

[0011] A phase detection device, comprising:

[0012] The first integrating circuit is used to receive the input pulse signal, calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point of the input pulse signal, and send the first area to the comparator.

[0013] The second integrator circuit is used to receive the input pulse signal, calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time after the main sampling point of the input pulse signal, and send the second area to the comparator.

[0014] The comparator is used to receive the first area and the second area, compare the size of the first area and the second area, obtain a first comparison result, and send the first comparison result to the error sampling circuit.

[0015] An error sampling circuit is used to receive the first comparison result, process the first comparison result to obtain first error information, and send the first error information to the phase detection logic circuit.

[0016] The data sampling circuit is used to receive the input pulse signal, process the input pulse signal to obtain first phase information, and send the first phase information to the phase detection logic circuit.

[0017] A phase detection logic circuit is used to receive the first error information and the first phase information, and calculate the first phase information and the first error information according to a preset truth rule to obtain the phase detection result of the input pulse signal.

[0018] The aforementioned phase detection method and apparatus, after receiving an input pulse signal, sets a main sampling point on the phase curve of the input pulse signal, then calculates the first area formed by the waveform curve of the input pulse signal and the time axis in the unit time before the main sampling point, calculates the second area formed by the waveform curve of the input pulse signal and the time axis in the unit time after the main sampling point, compares the size of the first area and the second area to obtain a first comparison result, and outputs the detection result of whether the phase of the input pulse signal is ahead or behind based on the first comparison result and a preset truth rule. The obtained detection result is more accurate, and the phase sampling of the input pulse signal based on the detection result is also more accurate. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a phase detection method according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the phase detection device in one embodiment of the present invention;

[0022] Figure 3 This is a sampled phase curve of the input pulse signal in one embodiment of the present invention;

[0023] Figure 4 This is another sampling phase curve of the input pulse signal in one embodiment of the present invention;

[0024] Figure 5 This is a simulated eye diagram of the input pulse signal in one embodiment of the present invention;

[0025] Figure 6 This is another simulated eye diagram of the input pulse signal in one embodiment of the present invention;

[0026] Figure 7 This is a first error information judgment rule table in one embodiment of the present invention;

[0027] Figure 8 This is a truth value rule table for phase detection results in one embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] For ease of understanding, the technical terms involved in this invention are as follows:

[0030] 1. CTLE (Continuous Time Linear Equalization) can effectively improve the performance of the eye diagram at the receiving end in links with high transmission loss.

[0031] 2. DFE (Decision Feedback Equalization) can reduce the subsequent effects of the current symbol in sequence according to the decision result of the current symbol, and minimize or even eliminate the impact of the current symbol ISI.

[0032] 3. CDR (Clock and Data Recovery) circuit: First, it provides clock signals to various circuits at the receiver end; second, it makes decisions on the received signals to facilitate data signal recovery and subsequent processing.

[0033] 4. ISI (Inter-symbol Interference) is caused by problems with the overall transmission characteristics of the system, which leads to waveform distortion and broadening of consecutive symbols, and causes a long tail in the preceding waveform that extends to the sampling time of the current symbol, thus interfering with the decision of the current symbol.

[0034] 5. Symbol: The basic unit of signal that carries information. In digital communication, a binary number is represented by a symbol with the same time interval. The signal within this time interval is called a (binary) symbol.

[0035] 6. An eye diagram is formed by the persistence of light on an oscilloscope, which overlaps the waveforms of each symbol obtained during scanning, creating an eye diagram. An eye diagram is also a graphical representation observed on an oscilloscope when adjusting the performance of a transmission system.

[0036] 7. Eye width reflects the total jitter of the signal, i.e., the size of the eye diagram opening on the horizontal axis, which is the time difference between the intersection points of the two upper and lower edges. The time between intersection points is calculated based on the histogram average of the two zero-crossing points in the signal, and the standard deviation of each distribution is obtained by subtracting the difference between the two means.

[0037] In existing CDR structures, the phase detector obtains lag or lead information based on the equalized input signal and clock phase. The existing phase detector method involves directly sampling the input signal to obtain direct sampled data, then comparing the input signal with a reference level (including high and low levels) to obtain first and second sampling output error information. Based on the direct sampled data, the first and second sampling output error information, and a pre-set lead or lag calculation method, the lead or lag information of the input signal is calculated. However, observations have shown that the lead or lag information output by the phase detection method used in conventional phase detectors is inaccurate, leading to phase lead or lag in the final sampling of the input signal. Therefore, this application provides a phase detection method and apparatus to solve the problem of phase lead or lag in the sampling input signal of traditional CDRs.

[0038] In one embodiment, such as Figure 1 As shown, a phase detection method is provided, including the following steps S101 to S105:

[0039] S101, Receive input pulse signal.

[0040] Furthermore, the input pulse signal is processed by a continuous-time linear equalizer to obtain a second input pulse signal, which replaces the original input pulse signal. The continuous-time linear equalizer is used to enhance the high-frequency components of the input pulse signal to compensate for high-frequency channel loss.

[0041] Furthermore, a third input pulse signal is obtained by processing the second input pulse signal through a decision feedback equalizer, and the third input pulse signal replaces the original input pulse signal. The decision feedback equalizer is used to extract the digital signal after the decision point, eliminate ISI, and process the input pulse signal in the digital domain.

[0042] S102. Obtain the main sampling point of the input pulse signal.

[0043] The main sampling point is generally selected as the peak position of the phase of the input pulse signal.

[0044] S103. Calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point.

[0045] Furthermore, the calculation of the first area formed by the waveform curve of the input pulse signal and the time axis in the unit time preceding the main sampling point specifically includes:

[0046] The input pulse signal is received through a first integrator circuit.

[0047] The first integral structure circuit calculates the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point.

[0048] Specifically, such as Figure 4 As shown, point A is the specific main sampling point in this embodiment, point C is the first sampling point on the input pulse signal one unit time before the main sampling point A, point B is the point on the time axis corresponding to the main sampling point A, and point D is the point on the time axis corresponding to the first sampling point C. The straight lines between the main sampling point A and point B, the straight lines between point B and point D, the straight lines between point D and point C, and the curve between point C and the main sampling point A together form a closed figure ABCD, and the area of ​​the closed figure ABCD is the first area.

[0049] S104. Calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time of the main sampling point.

[0050] Furthermore, the calculation of the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time interval after the main sampling point specifically includes:

[0051] The input pulse signal is received through a second integrator circuit.

[0052] The second integral structure circuit calculates the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time of the main sampling point.

[0053] Specifically, such as Figure 4 As shown, point G is the second sampling point on the input pulse signal one unit time after the main sampling point A; point E is the third sampling point where the waveform curve of the input pulse signal changes significantly one unit time after the main sampling point A; and point F is the fourth sampling point where the waveform curve of the input pulse signal changes significantly one unit time after the main sampling point A. The straight line between the main sampling point A and point B, the straight line between point B and point G, the curve between point G and point F, the curve between point F and point E, and the curve between point E and the main sampling point A together form a closed figure ABBEF. The area of ​​the closed figure ABBEF is the second area.

[0054] S105. Compare the size of the first area and the second area to obtain a first comparison result, and output the phase detection result of the input pulse signal according to the first comparison result and the preset truth value rule.

[0055] Furthermore, the step of comparing the size of the first area and the second area to obtain the first comparison result specifically includes:

[0056] The comparator receives the first calculation result of the first area and the second calculation result of the second area.

[0057] The first comparison result is obtained by comparing the first area calculation result and the second area settlement result using the comparator.

[0058] Specifically, the first integrating circuit integrates the closed shape ABCD to obtain a first integrating result, and the second integrating circuit integrates the closed shape ABBEF to obtain a second integrating result. The first integrating result and the second integrating result are sent to the comparator, and the first comparison result is obtained after comparison by the comparator.

[0059] Further, the step of outputting the phase detection result of the input pulse signal based on the first comparison result and the preset truth rule includes:

[0060] The input pulse signal is processed by a data sampling circuit to obtain the first phase information;

[0061] The first comparison result is processed by an error sampling circuit to obtain the first error information;

[0062] The phase detection result of the input pulse signal is obtained by calculating the first phase information and the first error information using the preset truth rules of the phase detection circuit.

[0063] Specifically, the error sampling circuit receives the first comparison result and the clock signal to be divided, and after processing by the error sampling circuit, it calculates the result according to... Figure 7 The rules shown output the first error information. Here, k represents the current time, e(k) represents the first error information at the current time, k+1 represents the time after the current time plus one unit of time, and k-1 represents the time before the current time minus one unit of time. According to... Figure 7 According to the rules shown, e(k) is 1 when the output of the first integrator is greater than or equal to the output of the second integrator; and e(k) is 0 when the output of the first integrator is less than the output of the second integrator.

[0064] Further, the first error information e(k) is sent to the phase detection circuit. The data sampling circuit processes the input pulse signal to obtain the first phase information b(k). Here, k represents the current time, b(k) represents the first phase information at the current time, k+1 represents the time after the current time plus one unit of time, and k-1 represents the time before the current time minus one unit of time. The first phase information is sent to the phase detection circuit. The phase detection circuit receives the first error information and the first phase information, and according to... Figure 8 The truth rules shown are used to calculate the phase detection result of the input pulse signal, which includes information about the phase lead or lag of the input pulse signal. For example... Figure 8 As shown, b(k) represents the first phase information at the current time, b(k+1) represents the first phase information at the next time step after adding one unit of time to the current time, b(k-1) represents the first phase information at the previous time step after subtracting one unit of time from the current time, e(k) represents the first error information at the current time, early indicates that the phase of the input pulse signal is leading, and late indicates that the phase of the input pulse signal is lagging. For example, with Figure 8 For example, the first row indicates that the phase of the input pulse signal is ahead when b(k-1) = 0, b(k) = 1, b(k+1) = 0, and e(k) = 1.

[0065] In this embodiment, the curves of pulse response and sampling phase in the conventional scheme are as follows: Figure 3 As shown, the pulse response and sampling phase curves of the scheme in this application are as follows: Figure 4 As shown, h represents the sampling phase curve, t represents the time of the main sampling point, h(t) represents the point of the main sampling point on the sampling phase curve at the current time, h(t+1) represents the point of the sampling phase curve at the next unit time after the main sampling point, and h(t-1) represents the point of the sampling phase curve at the previous unit time before the main sampling point. By comparison, it is found that h(t) in the scheme of this application is shifted to the right. The optimal sampling phase of CDR should make the eye diagram symmetrical and the left and right eye widths consistent. If the left eye is smaller at the sampling point, it indicates that the sampling is ahead; if the right eye is smaller at the sampling point, it indicates that the sampling is behind. The traditional scheme and the scheme of this application are simulated according to the input pulse signal, respectively, and the results are obtained. Figure 5 and Figure 6 The eye diagram shown, Figure 5 The eye diagram is the simulation result of the traditional scheme. Figure 6 The simulation results of the proposed solution are shown in the eye diagram. A comparison reveals that... Figure 5 The eye diagram is asymmetrical, and Figure 5 The left eye is smaller, indicating that the traditional method's sampling is ahead of time. Figure 6 The eye diagram is basically symmetrical from left to right. Compared with the traditional scheme, the CDR sampling point is basically in the middle of the eye diagram. The width of the left eye is 0.1 units larger than that of the traditional scheme. That is, the scheme of this application solves the problem of large sampling phase advance and asymmetry of the eye diagram in the traditional technology.

[0066] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0067] In one embodiment, a phase detection device 100 is provided, which corresponds one-to-one with the phase detection method described in the above embodiments. For example... Figure 2 As shown, the phase detection device 100 includes a first integrating circuit 10, a second integrating circuit 20, a data sampling circuit 30, a comparator 40, an error sampling circuit 50, a phase detection logic circuit 60, a continuous-time linear equalizer 70, and a decision feedback equalizer 80. Detailed descriptions of each functional module are as follows:

[0068] The first integrating circuit 10 is used to receive the input pulse signal, calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point of the input pulse signal, and send the first area to the comparator.

[0069] The second integrator circuit 20 is used to receive the input pulse signal, calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time after the main sampling point of the input pulse signal, and send the second area to the comparator.

[0070] The data sampling circuit 30 is used to receive the input pulse signal, process the input pulse signal to obtain first phase information, and send the first phase information to the phase detection logic circuit.

[0071] Comparator 40 is used to receive the first area and the second area, compare the size of the first area and the second area, obtain a first comparison result, and send the first comparison result to the error sampling circuit.

[0072] Error sampling circuit 50 is used to receive the first comparison result, process the first comparison result to obtain first error information, and send the first error information to the phase detection logic circuit.

[0073] The phase detection logic circuit 60 is used to receive the first error information and the first phase information, and calculate the first phase information and the first error information according to the preset truth rules to obtain the phase detection result of the input pulse signal.

[0074] The continuous-time linear equalizer 70 is used to receive the input pulse signal, process the input pulse signal to obtain a second input pulse signal, replace the input pulse signal with the second input pulse signal, and send the second input pulse signal to the first integrator circuit, the second integrator circuit, and the data sampling circuit.

[0075] The decision feedback equalizer 80 is used to receive the second input pulse signal, process the second input pulse signal to obtain a third input pulse signal, replace the input pulse signal with the third input pulse signal, and send the third input pulse signal to the first integrator circuit, the second integrator circuit and the data sampling circuit.

[0076] The terms "first" and "second" in the above-mentioned modules / units are only used to distinguish different modules / units and are not intended to specify which module / unit has a higher priority or any other limiting meaning. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to these processes, methods, products, or devices. The module divisions appearing in this application are merely logical divisions; in actual applications, different division methods may be used.

[0077] Specific limitations regarding the phase detection device can be found in the limitations of the phase detection method described above, and will not be repeated here. Each module in the aforementioned phase detection device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the operations corresponding to each module.

[0078] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When executed by a processor, the computer program implements the steps of the phase detection method described in the above embodiments, for example... Figure 1 The steps S101 to S105 shown, as well as other extensions and related steps of the method, are shown.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0080] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A phase detection method applied to a clock data recovery circuit, characterized by, include: Receive input pulse signals; Obtain the main sampling point of the input pulse signal; Calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point; Calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time interval after the main sampling point; Compare the size of the first area and the second area to obtain a first comparison result, and output the phase detection result of the input pulse signal according to the first comparison result and the preset truth rule; The step of outputting the phase detection result of the input pulse signal according to the first comparison result and the preset truth rule includes processing the input pulse signal through a data sampling circuit to obtain first phase information; processing the first comparison result through an error sampling circuit to obtain first error information; and calculating the first phase information and the first error information through the preset truth rule of the phase detection circuit to obtain the phase detection result of the input pulse signal.

2. The phase detection method of claim 1, wherein, After receiving the input pulse signal, the method further includes: The input pulse signal is processed by a continuous-time linear equalizer to obtain a second input pulse signal, which is then used to replace the original input pulse signal.

3. The phase detection method according to claim 2, characterized in that, After processing the input pulse signal through a continuous-time linear equalizer to obtain the second input pulse signal, the process further includes: The second input pulse signal is processed by a decision feedback equalizer to obtain a third input pulse signal, and the third input pulse signal is used to replace the original input pulse signal.

4. The phase detection method according to claim 1, characterized in that, The calculation of the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point specifically includes: The input pulse signal is received through a first integrator circuit. The first integral structure circuit calculates the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point.

5. The phase detection method according to claim 4, characterized in that, The calculation of the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time interval after the main sampling point specifically includes: The input pulse signal is received through a second integrator circuit. The second integral structure circuit calculates the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time of the main sampling point.

6. The phase detection method according to claim 5, characterized in that, The comparison of the first area and the second area to obtain the first comparison result specifically includes: The first area and the second area, calculated by the comparator, are received. The first comparison result is obtained by comparing the size of the first area and the second area using the comparator.

7. A phase detection device, characterized in that, include: The first integrating circuit is used to receive the input pulse signal, calculate the first area formed by the waveform curve of the input pulse signal and the time axis in the previous unit time of the main sampling point of the input pulse signal, and send the first area to the comparator. The second integrator circuit is used to receive the input pulse signal, calculate the second area formed by the waveform curve of the input pulse signal and the time axis in the next unit time after the main sampling point of the input pulse signal, and send the second area to the comparator. The comparator is used to receive the first area and the second area, compare the size of the first area and the second area, obtain a first comparison result, and send the first comparison result to the error sampling circuit; An error sampling circuit is used to receive the first comparison result, process the first comparison result to obtain first error information, and send the first error information to the phase detection logic circuit. The data sampling circuit is used to receive the input pulse signal, process the input pulse signal to obtain first phase information, and send the first phase information to the phase detection logic circuit. A phase detection logic circuit is used to receive the first error information and the first phase information, and calculate the first phase information and the first error information according to a preset truth rule to obtain the phase detection result of the input pulse signal.

8. The phase detection device according to claim 7, characterized in that, Also includes: A continuous-time linear equalizer is used to receive the input pulse signal, process the input pulse signal to obtain a second input pulse signal, replace the input pulse signal with the second input pulse signal, and send the second input pulse signal to the first integrator circuit, the second integrator circuit, and the data sampling circuit.

9. The phase detection device according to claim 8, characterized in that, Also includes: The decision feedback equalizer is used to receive the second input pulse signal, process the second input pulse signal to obtain a third input pulse signal, replace the input pulse signal with the third input pulse signal, and send the third input pulse signal to the first integrator circuit, the second integrator circuit, and the data sampling circuit.

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