Mapping table management method and device based on large-capacity solid state disk and computer device
By introducing a system data area management LPA distribution with a large number of concurrent read units in a high-capacity SSD, combined with timestamps and ECC Parity error correction, the problems of mapping table maintenance complexity and bit width requirements are solved, achieving efficient 4KB-level random read/write performance and cost optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-05-31
- Publication Date
- 2026-07-31
AI Technical Summary
As the capacity of a single SSD increases, the maintenance complexity and space requirements of existing mapping tables cannot meet the demands, especially the excessive bit width requirement of L2P tables, which affects performance and cost.
The system data area manages LPA distribution using a system with a large concurrent read unit. LPA offset and data are obtained through two transmissions, reducing the bit width requirement of the L2P table and maintaining a mapping granularity of 4KB. Error correction and verification are performed using timestamps, Valid_bitmap, and ECC Parity.
Without significantly increasing time costs, it effectively reduces the bit width requirement of the L2P table, simplifies the maintenance complexity of the mapping table, ensures 4KB random read/write performance, and reduces design and cost.
Smart Images
Figure CN116540945B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to a mapping table management method, apparatus, computer device, and storage medium based on a large-capacity solid-state drive. Background Technology
[0002] SSDs (Solid State Drives) have been widely used in various applications and are gradually replacing traditional HDDs in the PC market, providing users with a better experience in terms of reliability and performance.
[0003] SSDs use NAND flash memory for data storage. Due to the special nature of NAND, data cannot be directly modified in-place after being written; the corresponding physical block must be erased before it can be rewritten. To address this, for newly written data, the SSD allocates new blank physical blocks / pages for writing and uses a mapping table, denoted as L2P, to track the mapping from host logical data to NAND physical addresses. Its index, LPA, is derived from the host's access to the disk's logical address (LBA); its value, GPPA, is the NAND physical address.
[0004] Typically, the logical address (LBA) granularity of a host access disk is 512 bits, with eight consecutive LBAs corresponding to one LPA (4KB, e.g., LBA 0-7 corresponds to LPA0). To track the storage location on the NAND, 4 bits are needed to represent the physical address where the LPA is stored, corresponding to an addressable physical space range of (4GB / 4)*4KB = 4TB. However, as the capacity of a single SSD disk increases, this space is insufficient, so the L2P value must exceed 32 bits. For 32-bit systems, both the maintenance complexity and space requirements of the mapping table become problematic. Summary of the Invention
[0005] Therefore, it is necessary to provide a mapping table management method, device, computer equipment, and storage medium based on a large-capacity solid-state drive to address the aforementioned technical problems.
[0006] A mapping table management method based on a large-capacity solid-state drive, the method comprising:
[0007] The operation request is submitted to the backend module, which then initiates a read operation request to the NAND based on the physical address.
[0008] Wait for the NAND read operation request to complete; at this time, the data will be loaded into the NAND Cache Register.
[0009] The system data area content of the physical page is transmitted to the SOC, and the data error correction verification is completed using the verification data contained in the system data area;
[0010] The SSD's internal logical-to-physical address mapping table only tracks the largest concurrent read units, and describes the stored LPA distribution in the system data area of the larger concurrent read units. The system data area contains N LPA indices stored in the current physical page, and the indices are matched with the LPA addresses of the current mapping unit.
[0011] Based on the offset of the matched LPA in the array, obtain the offset of the corresponding data in the physical page;
[0012] Transmit LPA data corresponding to the offset, and use the verification data in the system data area to complete data error correction verification.
[0013] In one embodiment, the system data area includes:
[0014] A timestamp is used to indicate whether data written to the same logical address multiple times is new or old.
[0015] LPA[N] is used to record the N LPA indexes stored in the current physical page memory;
[0016] Valid_bitmap[N] is used to mark whether each LBA within N LPAs is valid;
[0017] ECC Parity of system data is used to perform error correction and verification on system data.
[0018] In one embodiment, the step of submitting the operation request to the backend module and the backend module initiating a NAND read operation request based on the physical address further includes:
[0019] Obtain a read command issued by the host, wherein the read command carries the LBA access range;
[0020] The command LBA address is segmented into mapping units using the SSD front-end module;
[0021] Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer;
[0022] Submit the operation request for each mapping unit to the mapping table management module;
[0023] The mapping table management module converts logical addresses into physical addresses.
[0024] In one embodiment, after the step of transmitting LPA data corresponding to the offset and completing data error correction verification using the verification data of the system data area, the method further includes:
[0025] Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
[0026] A mapping table management device based on a large-capacity solid-state drive, the device comprising:
[0027] The request module is used to submit operation requests to the backend module, and the backend module initiates a read operation request to NAND based on the physical address.
[0028] The data loading module is used to wait for the NAND read operation request to complete, at which time the data will be loaded into the NAND Cache Register;
[0029] The first transmission module is used to transmit the system data area content of the physical page to the SOC, and to use the verification data contained in the system data area to complete the data error correction verification.
[0030] The matching module is used to track only the larger concurrent read units in the SSD's internal logical-to-physical address mapping table, and to describe the stored LPA distribution in the system data area of the larger concurrent read unit. The system data area contains N LPA indices stored in the current physical page, and the indexes are matched with the LPA addresses of the current mapping unit.
[0031] The acquisition module is used to obtain the offset of the corresponding data in the physical page based on the offset of the matched LPA in the array;
[0032] The second transmission module is used to transmit LPA data corresponding to the offset and to complete data error correction verification using the verification data in the system data area.
[0033] In one embodiment, the system data area includes:
[0034] A timestamp is used to indicate whether data written to the same logical address multiple times is new or old.
[0035] LPA[N] is used to record the N LPA indexes stored in the current physical page memory;
[0036] Valid_bitmap[N] is used to mark whether each LBA within N LPAs is valid;
[0037] ECC Parity of system data is used to perform error correction and verification on system data.
[0038] In one embodiment, the apparatus further includes a front-end execution module, the front-end execution module being configured to:
[0039] Obtain a read command issued by the host, wherein the read command carries the LBA access range;
[0040] The command LBA address is segmented into mapping units using the SSD front-end module;
[0041] Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer;
[0042] Submit the operation request for each mapping unit to the mapping table management module;
[0043] The mapping table management module converts logical addresses into physical addresses.
[0044] In one embodiment, the apparatus further includes a loop processing module, the loop processing module being used for:
[0045] Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
[0046] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0047] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0048] The aforementioned mapping table management method, device, computer equipment, and storage medium based on high-capacity solid-state drives (SSDs) maintain a granularity of 4KB for the logical-to-physical address mapping within the SSD to ensure the corresponding 4KB random read / write performance requirements. The SSD's internal logical-to-physical address mapping table only tracks larger concurrent read units, such as physical pages or sets of physical pages that can be read concurrently. The SSD internally describes the LPA distribution stored within the system data area of larger concurrent read units. Within a concurrent read unit, two transfers are performed: the first transfer acquires the LPA offset from system data, and the second transfer acquires the corresponding LPA data. This effectively reduces the bit width requirement of the L2P table without a significant increase in overall time. Attached Figure Description
[0049] Figure 1 A schematic diagram of a typical existing NAND page;
[0050] Figure 2 This is a schematic diagram of a typical existing SSD read process;
[0051] Figure 3 This is a flowchart illustrating a mapping table management method based on a large-capacity solid-state drive in one embodiment;
[0052] Figure 4This is a schematic diagram of the NAND Page composition in one embodiment;
[0053] Figure 5 This is a flowchart illustrating a mapping table management method based on a large-capacity solid-state drive in another embodiment;
[0054] Figure 6 This is a structural block diagram of a mapping table management device based on a large-capacity solid-state drive in one embodiment;
[0055] Figure 7 This is a structural block diagram of a mapping table management device based on a large-capacity solid-state drive in another embodiment;
[0056] Figure 8 This is a structural block diagram of a mapping table management device based on a large-capacity solid-state drive in another embodiment;
[0057] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0058] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0059] like Figure 1 The diagram illustrates a typical NAND page structure. For clarity, a 16KB physical page is used as an example: it is divided into four independent LPA storage areas, each storing relevant user / system data. Taking the first LPA A as an example, its data composition is as follows:
[0060] User data: Data written from the host, consisting of N consecutive LBAs (e.g., LBA 0-7 corresponds to LPA0; LBA8-15 corresponds to LPA1, etc.).
[0061] System Data: Internal SSD management data, including timestamps: timestamps of data writes, used to determine the age of the same LBA data written multiple times by the host. LPA: The index of the current LPA, such as A. Valid Bitmap: Used to represent which of the N LBAs within the LPA are valid. Validation Data: Protects user data and system data, typically using mature algorithms such as ECC.
[0062] The L2P table inside the SSD has an index called LPA, and the value (GPPA) is the 4KB address on the NAND where the data is stored. Therefore, the GPPA value needs to be accurately described to the 4KB level within the page.
[0063] like Figure 2 The typical SSD read process shown includes the following steps: the host submits a read command to the SSD's front-end module; the SSD front-end module divides the command LBA address into mapping units (LPAs, typically 4KB); it submits the operation request for each mapping unit to the buffer management module, allocating a read buffer; it submits the operation request for each mapping unit to the mapping table management module; the mapping table management module is responsible for converting the logical address (LPA) into a NAND physical address (GPPA); it submits the operation request to the back-end module, which initiates a NAND read request based on the physical address; it waits for the NAND read operation request to complete, at which point the data is loaded into the NAND Cache Register; once the data is ready, the corresponding 4KB GPPA data within the page is selected for transfer from the NAND Cache Register to the host.
[0064] During this process, the L2P table value (GPPA) describes the 4KB level within a page. The SSD reads the corresponding page and selectively transfers the corresponding 4KB of data within the page to the host.
[0065] Based on this, this solution proposes a mapping table management method based on large-capacity solid-state drives, which aims to solve the overhead of large-capacity SSD mapping tables and reduce the bit width requirement of L2P tables.
[0066] In one embodiment, such as Figure 3 As shown, a mapping table management method based on a large-capacity solid-state drive is provided, the method including:
[0067] Step 302: Submit the operation request to the backend module. The backend module initiates a read operation request for NAND based on the physical address.
[0068] Step 304: Wait for the NAND read operation request to complete. At this time, the data will be loaded into the NAND Cache Register.
[0069] Step 306: Transmit the system data area content of the physical page to the SOC, and use the verification data contained in the system data area to complete the data error correction verification.
[0070] Step 308: The SSD's internal logical-to-physical address mapping table only tracks the larger concurrent read units, and describes the stored LPA distribution in the system data area of the larger concurrent read units. The system data area contains N LPA indices stored in the current physical page, and matches the indices with the LPA addresses of the current mapping unit.
[0071] Step 310: Based on the offset of the matched LPA in the array, obtain the offset of the corresponding data in the physical page;
[0072] Step 312: Transmit the LPA data corresponding to the offset, and use the verification data in the system data area to complete the data error correction verification.
[0073] This embodiment provides a mapping table management method based on a large-capacity solid-state drive (SSD). In this method, the granularity of the logical-to-physical address mapping within the SSD is maintained at the 4KB level to ensure the corresponding 4KB random read / write performance requirements. The SSD's internal logical-to-physical address mapping table only tracks higher-concurrency read units (such as physical pages or sets of concurrently readable physical pages). The system data area within a higher-concurrency read unit describes the distribution of LPAs stored therein. When the host reads data, it queries the current read unit according to the logical-to-physical address mapping table, prioritizes loading / parsing its internal system data area, obtains the corresponding LPA information, and then loads the corresponding data and returns it to the host. This method effectively reduces the complexity of mapping table maintenance and capacity requirements for large-capacity SSDs while ensuring SSD performance, thus saving costs.
[0074] In one embodiment, the system data area includes: a timestamp, used to characterize the age of data written multiple times to the same logical address; LPA[N], used to record the N LPA indices stored in the current physical page memory; Valid_bitmap[N], used to mark whether each LBA in the N LPAs is valid; and verification data, the ECC Parity of the system data, used to perform error correction verification on the system data.
[0075] For specific details, please refer to Figure 4 The diagram shown illustrates the composition of NAND pages. This embodiment introduces a mapping table management method for large capacities. For ease of explanation, a single physical page (which can store 4 LPA user data) is used here for illustration. It should be noted that this can be extended to any concurrently readable unit, such as a set of pages (DIE 0 / 1 / 2…), which can complete data reading in parallel.
[0076] The organization within a physical page is as follows:
[0077] -System Data: System management data for each LPA within a physical page, including the following:
[0078] Timestamp: The timestamp of data being written, used to indicate whether data written to the same logical address multiple times is new or old.
[0079] LPA[N]: The N LPA indices stored in the current physical page memory, as shown in A / B / X / Y in the figure.
[0080] Valid_bitmap[N]: A flag indicating whether each LBA within N LPAs is valid.
[0081] Verification data: ECC Parity of system data, used to correct / verify system data.
[0082] -LPAA: Stores the user data and verification data for the first LPA.
[0083] -LPA B: Stores user data and verification data for the second LPA.
[0084] -LPAX: Stores user data and verification data for the third LPA.
[0085] -LPA Y: Stores the user data and verification data for the fourth LPA.
[0086] The value of the mapping table L2P points to the corresponding physical page, not the offset within the physical page.
[0087] NAND data reading is divided into two parts: one part is internal cell reading, which loads physical page data into the NAND Cache Register; the other part is transferring data from the Cache Register to the SSD controller buffer.
[0088] The most time-consuming operation is the internal cell read operation. Once the cell read is completed, the data of the entire physical page can be loaded into the NAND cache register, and then transferred to the SSD controller buffer as needed.
[0089] In this embodiment, system data is stored separately and verification data is protected. Therefore, after a single cell read is completed, the system data can be transmitted to the SSD controller for parsing and addressing the target LPA at the location of LPA[N]. Based on its location, its offset within the physical page / concurrent read unit can be determined. Since the data has already been loaded into the cache register, only the LPA data corresponding to the offset needs to be transmitted to the controller buffer for decoding before being transmitted to the host.
[0090] Therefore, it can be seen that within the concurrent read unit, by transmitting the system data to obtain the LPA offset in the first transmission and the corresponding LPA data in the second transmission, the bit width requirement of the L2P table is effectively reduced without a significant increase in the overall time.
[0091] In this embodiment, the granularity of the logical-to-physical address mapping within the SSD is maintained at the 4KB level to ensure the corresponding 4KB random read / write performance requirements. The SSD's internal logical-to-physical address mapping table only tracks larger concurrent read units, such as physical pages or sets of physical pages that can be read concurrently. The SSD internally describes the LPA distribution stored within the system data area of larger concurrent read units. Within a concurrent read unit, two transfers are performed: the first transfer acquires the LPA offset from system data, and the second transfer acquires the corresponding LPA data. This effectively reduces the bit width requirement of the L2P table without a significant increase in overall time.
[0092] In one embodiment, a mapping table management method based on a large-capacity solid-state drive is provided. This method further includes the following steps before the step of submitting an operation request to a backend module, and the backend module initiating a read operation request to the NAND based on the physical address:
[0093] Obtain a read command issued by the host, wherein the read command carries the LBA access range;
[0094] The command LBA address is segmented into mapping units using the SSD front-end module;
[0095] Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer;
[0096] Submit the operation request for each mapping unit to the mapping table management module;
[0097] The mapping table management module converts logical addresses into physical addresses.
[0098] In one embodiment, a mapping table management method based on a large-capacity solid-state drive is provided. After transmitting LPA data corresponding to the offset and performing data error correction verification using check data from the system data area, the method further includes:
[0099] Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
[0100] In this embodiment, a mapping table management method based on a large-capacity solid-state drive is provided, referring to... Figure 5 As shown, the specific execution steps are as follows:
[0101] Step 5.1: The host issues a read command, carrying the LBA access range [lba_start, lba_end].
[0102] Step 5.2: The SSD front-end module divides the command LBA address into mapping units [lpa_start, lpa_end]. Step 5.3: Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer. Step 5.4: Submit the operation request for each mapping unit to the mapping table management module.
[0103] Step 5.5: The mapping table management module is responsible for converting logical addresses (LPA) into NAND physical addresses (GPPA).
[0104] Step 5.6: Submit the operation request to the backend module. The backend module initiates a read request to the NAND based on the physical address.
[0105] Step 5.7: Wait for the NAND read operation request to complete. At this time, the data will be loaded into the NAND Cache Register.
[0106] Step 5.8: Transfer the system data area content of the corresponding physical page to the SOC, and use the check data within it to complete data error correction / verification.
[0107] Step 5.9: Match the LPA index recorded in the LPA[N] array with the LPA address of the current mapping unit.
[0108] Step 5.10: Based on the offset of the matched LPA within the array, obtain the offset of its data within the physical page.
[0109] Step 5.11: Transmit the LPA data corresponding to the offset and use the check data within it to complete data error correction / verification.
[0110] Step 5.12: Transmit data to the host and process it in a loop until all the read requests of the mapped units within [lpa_start, lpa_end] have been processed.
[0111] In this embodiment, the mapping table from the internal logic of the SSD to the physical address only tracks the larger concurrent read units, such as physical pages or sets of physical pages that can be read concurrently. The L2P value can be maintained at 32 bits, but the addressable physical space can be extended to at least 16TB. This effectively solves the overhead of the mapping table for large-capacity SSDs and reduces costs and design complexity.
[0112] It should be understood that, although Figures 1-5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-5At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0113] In one embodiment, such as Figure 6 As shown, a mapping table management device 600 based on a large-capacity solid-state drive is provided. The device includes:
[0114] Request module 601, the request module is used to submit an operation request to the backend module, and the backend module initiates a read operation request to NAND based on the physical address;
[0115] The data loading module 602 is used to wait for the NAND read operation request to complete, at which time the data will be loaded into the NAND Cache Register;
[0116] The first transmission module 603 is used to transmit the system data area content of the physical page to the SOC, and to use the verification data contained in the system data area to complete the data error correction verification.
[0117] The matching module 604 is used to track only the larger concurrent read units in the SSD's internal logical-to-physical address mapping table, and to describe the stored LPA distribution in the system data area of the larger concurrent read unit. The system data area contains N LPA indices stored in the current physical page, and the indexes are matched with the LPA addresses of the current mapping unit.
[0118] Acquisition module 605 is used to obtain the offset of the corresponding data in the physical page based on the offset of the matched LPA in the array;
[0119] The second transmission module 606 is used to transmit LPA data corresponding to the offset and to complete data error correction verification using the verification data in the system data area.
[0120] In one embodiment, the system data area includes:
[0121] A timestamp is used to indicate whether data written to the same logical address multiple times is new or old.
[0122] LPA[N] is used to record the N LPA indexes stored in the current physical page memory;
[0123] Valid_bitmap[N] is used to mark whether each LBA within N LPAs is valid;
[0124] ECC Parity of system data is used to perform error correction and verification on system data.
[0125] In one embodiment, such as Figure 7 As shown, a mapping table management device 600 based on a large-capacity solid-state drive is provided. This device further includes a front-end execution module 607, which is used for:
[0126] Obtain a read command issued by the host, wherein the read command carries the LBA access range;
[0127] The command LBA address is segmented into mapping units using the SSD front-end module;
[0128] Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer;
[0129] Submit the operation request for each mapping unit to the mapping table management module;
[0130] The mapping table management module converts logical addresses into physical addresses.
[0131] In one embodiment, such as Figure 8 As shown, a mapping table management device 600 based on a large-capacity solid-state drive is provided. This device further includes a loop processing module 608, which is used for:
[0132] Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
[0133] For specific limitations on mapping table management devices based on large-capacity solid-state drives, please refer to the limitations on mapping table management methods based on large-capacity solid-state drives mentioned above, which will not be repeated here.
[0134] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 9 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a mapping table management method based on a large-capacity solid-state drive.
[0135] Those skilled in the art will understand that Figure 9The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0136] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0137] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0138] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0140] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A mapping table management method based on a large-capacity solid-state drive, the method comprising: The operation request is submitted to the backend module, which then initiates a read operation request to the NAND based on the physical address. Wait for the NAND read operation request to complete; at this time, the data will be loaded into the NAND Cache Register. The system data area content of the physical page is transmitted to the SOC, and the data error correction verification is completed using the verification data contained in the system data area; The SSD's internal logical-to-physical address mapping table only tracks the largest concurrent read units, and describes the LPA distribution stored in the system data area of the larger concurrent read unit. The system data area contains N LPA indices stored in the current physical page, and the indices are matched with the LPA addresses of the current mapping unit. The larger concurrent read unit is a physical page or a set of physical pages that can be read concurrently. Based on the offset of the matched LPA in the array, obtain the offset of the corresponding data in the physical page; Transmit LPA data corresponding to the offset, and use the verification data in the system data area to complete data error correction verification.
2. The mapping table management method based on a large-capacity solid-state drive according to claim 1, characterized in that, The system data area includes: A timestamp is used to indicate whether data written to the same logical address multiple times is new or old. LPA[N] is used to record the N LPA indexes stored in the current physical page memory; Valid_bitmap[N] is used to mark whether each LBA within N LPAs is valid; ECC Parity of system data is used to perform error correction and verification on system data.
3. The mapping table management method based on a large-capacity solid-state drive according to claim 2, characterized in that, Before the step of submitting the operation request to the backend module, and the backend module initiating a NAND read operation request based on the physical address, the following steps are also included: Obtain a read command issued by the host, wherein the read command carries the LBA access range; The command LBA address is segmented into mapping units using the SSD front-end module; Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer; Submit the operation request for each mapping unit to the mapping table management module; The mapping table management module converts logical addresses into physical addresses.
4. The mapping table management method based on a large-capacity solid-state drive according to claim 3, characterized in that, After the steps of transmitting LPA data corresponding to the offset and completing data error correction verification using the verification data in the system data area, the method further includes: Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
5. A mapping table management device based on a large-capacity solid-state drive, characterized in that, The device includes: The request module is used to submit operation requests to the backend module, and the backend module initiates a read operation request to NAND based on the physical address. The data loading module is used to wait for the NAND read operation request to complete, at which time the data will be loaded into the NAND Cache Register; The first transmission module is used to transmit the system data area content of the physical page to the SOC, and to use the verification data contained in the system data area to complete the data error correction verification. The matching module tracks only the largest concurrent read units in the SSD's internal logical-to-physical address mapping table, and describes the LPA distribution stored in the system data area of the largest concurrent read unit. The matching module is used to match the N LPA indices stored in the current physical page within the system data area with the LPA address of the current mapping unit; the largest concurrent read unit is a physical page or a set of physical pages that can be read concurrently. The acquisition module is used to obtain the offset of the corresponding data in the physical page based on the offset of the matched LPA in the array; The second transmission module is used to transmit LPA data corresponding to the offset and to complete data error correction verification using the verification data in the system data area.
6. The mapping table management device based on a large-capacity solid-state drive according to claim 5, characterized in that, The system data area includes: A timestamp is used to indicate whether data written to the same logical address multiple times is new or old. LPA[N] is used to record the N LPA indexes stored in the current physical page memory; Valid_bitmap[N] is used to mark whether each LBA within N LPAs is valid; ECC Parity of system data is used to perform error correction and verification on system data.
7. The mapping table management device based on a large-capacity solid-state drive according to claim 6, characterized in that, The device further includes a front-end execution module, the front-end execution module being used for: Obtain a read command issued by the host, wherein the read command carries the LBA access range; The command LBA address is segmented into mapping units using the SSD front-end module; Submit the operation request for each mapping unit to the buffer management module and allocate a read buffer; Submit the operation request for each mapping unit to the mapping table management module; The mapping table management module converts logical addresses into physical addresses.
8. The mapping table management device based on a large-capacity solid-state drive according to claim 7, characterized in that, The device further includes a loop processing module, which is used for: Data is transmitted to the host and processed in a loop until all read requests from the mapped units have been processed.
9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 4.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.