A multi-bit signed full digital in-memory computing device based on Booth multiplication

Abstract

The application discloses a multi-bit signed full-digital in-memory calculation device based on Booth multiplication, comprising four basic SRAM units arranged from top to bottom and used for storing weights; a Booth multiplier comprising two Booth multiplication structures, namely a first Booth multiplication structure and a second Booth multiplication structure; and an adder structure connected with the first Booth multiplication structure and the second Booth multiplication structure, wherein the multiplication process of a 4-bit signed weight and a 4-bit signed input excitation is processed through the combination of the Booth multiplier and the adder structure, a 7-bit signed multiplication result is obtained after operation, and the output result is in the form of a complement, so that the multiplication result of two 4-bit signed numbers can be calculated in one clock cycle, and the operation efficiency can be significantly improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a multi-bit signed all-digital in-memory computing device based on Booz multiplication. Background Technology

[0002] Currently, due to the explosive growth of artificial intelligence, edge devices have increasingly higher requirements for power consumption and energy efficiency in data processing and data transfer. As a new type of structure, in-memory computing has fundamentally eliminated the "memory wall" and "power wall" problems caused by data transfer, thus attracting much attention.

[0003] However, because the in-memory computing circuitry of streams uses analog domain computation, the computational accuracy is affected by the low signal-to-noise ratio of analog computing, thus making it unsuitable for high-performance neural networks. While digital domain in-memory computing architectures can solve the accuracy problem, they require multiple clock cycles of shifting and addition when computing multi-bit data, resulting in lower computational efficiency. Summary of the Invention

[0004] This invention provides a multi-bit signed all-digital in-memory computing device based on Booz multiplication, which is used to process the multiplication of a 4-bit signed weight and a 4-bit signed input stimulus. It can calculate the multiplication result of the input stimulus and the signed weight within one clock cycle, thereby solving or partially solving the problem of low computational efficiency of digital domain in-memory computing architecture.

[0005] To address the aforementioned technical problems, a first aspect of the present invention discloses a multi-bit signed all-digital in-memory computing device based on Booz multiplication, comprising:

[0006] Four basic SRAM cells arranged from top to bottom are used to store weights; a 4-bit signed weight is stored in the four basic SRAM cells in two's complement order from top to bottom and from high bit to low bit, with each SRAM cell storing 1 bit of weight.

[0007] The Boehringer-Stokes multiplier includes two Boehringer-Stokes multiplier structures: a first Boehringer-Stokes multiplier structure and a second Boehringer-Stokes multiplier structure. The first Boehringer-Stokes multiplier structure connects to the first, second, and third SRAM units arranged from top to bottom among the four basic SRAM units. It receives a 3-bit weight output from the first, second, and third SRAM units as a selection control signal and inputs a 4-bit input stimulus to participate in the calculation, obtaining a first partial product. The second Boehringer-Stokes multiplier structure connects to the third and fourth SRAM units arranged from top to bottom among the four basic SRAM units. It has an input terminal concatenated to the least significant bit for weight input. It receives a 3-bit weight output from the third, fourth, and least significant bits of the SRAM units as a selection control signal and inputs the 4-bit input stimulus to participate in the calculation, obtaining a second partial product.

[0008] An adder structure is connected to the first Bos multiplication structure and the second Bos multiplication structure respectively, and the first partial product and the second partial product are added to obtain the final result.

[0009] Preferably, the bit lines of the four basic SRAM cells are interconnected, the word lines of the four basic SRAM cells are independent of each other, and each of the four basic SRAM cells outputs a 1-bit weight.

[0010] Preferably, the two Bos multiplication structures are identical, and each Bos multiplication structure includes: a selection module, four partial product generation modules, and four half-adder modules;

[0011] One end of the selection module inputs a 3-bit weight, and the other end of the selection module is connected to each partial product generation module via four wires. It is used to select the operation to be performed on each bit of the input stimulus according to the input 3-bit weight. Among them, 2X is a left shift operation with two bits, X is the original data, -X is a negation operation, and -2X is a left shift followed by negation and increment operation.

[0012] Each of the four partial product generation modules is connected to a half-adder module; the input of each partial product generation module is the input stimulus of the current bit and the input stimulus of the previous bit, and the input of the first partial product generation module is the input stimulus of the current bit and 0; the output of each partial product generation module is a 1-bit intermediate value before adding 1, which is used as the input of the corresponding half-adder module;

[0013] The input of the first half-adder module in the four half-adder modules is connected to an OR gate, the carry output of the previous half-adder module is connected to the input of the next half-adder module, and the sum bit of the four half-adder modules outputs the partial product; wherein, the four half-adder modules and the OR gate are combined to implement the addition function, and the OR gate is used to activate the addition function only in -X and -2X, and no addition is performed in other states, so that the four half-adder modules output the partial product.

[0014] Preferably, the selection module includes: a first inverter, a second inverter, and a third inverter, each used to invert a 1-bit weight arranged from high to low.

[0015] The first inverter is connected to a 1-bit first weight, the second inverter is connected to a 1-bit second weight, and the third inverter is connected to a 1-bit third weight.

[0016] Preferably, the first inverter, the second inverter, and the third inverter are all NOT gates.

[0017] Preferably, the selection module further includes:

[0018] The first NAND gate combination structure includes a first NAND gate, a second NAND gate, and a third NAND gate; wherein, the input terminal of the first NAND gate is connected to the output terminal of the first inverter, the second weight, and the output terminal of the third inverter; the input terminal of the second NAND gate is connected to the output terminal of the first inverter, the output terminal of the second inverter, and the third weight; the output terminals of the first NAND gate and the second NAND gate are jointly connected to the input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs X;

[0019] The second NAND gate combination structure includes a fourth NAND gate and a first NOT gate connected in series; wherein, the input terminal of the fourth NAND gate is connected to the output terminal of the first inverter, the second weight and the third weight, and the output terminal of the first NOT gate outputs 2X;

[0020] The third NAND gate combination structure includes a fifth NAND gate and a second NOT gate connected in series; wherein, the input terminal of the fifth NAND gate is connected to the first weight, the output terminal of the second inverter and the output terminal of the third inverter, and the output terminal of the first NOT gate outputs -2X;

[0021] The fourth NAND gate combination structure includes a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; wherein, the input terminal of the sixth NAND gate is connected to the first weight, the second weight, and the output terminal of the third inverter; the input terminal of the seventh NAND gate is connected to the first weight, the output terminal of the second inverter, and the third weight; the output terminals of the sixth and seventh NAND gates are jointly connected to the input terminal of the eighth NAND gate, and the output terminal of the eighth NAND gate outputs -X.

[0022] Preferably, the partial product generation module includes:

[0023] A fourth inverter and a fifth inverter; wherein the fourth inverter is connected to the current input stimulus for inversion, and the fifth inverter is connected to the previous input stimulus for inversion;

[0024] The ninth NAND gate has its input terminal connected to -X and the output terminal of the fourth inverter.

[0025] The tenth NAND gate has X and the local input stimulus connected to its input terminal;

[0026] The eleventh NAND gate has its input connected to -2X and the output of the fifth inverter.

[0027] The twelfth NAND gate has 2X and the previous bit input stimulus connected to its input terminal;

[0028] The thirteenth NAND gate has its input terminals connected to the ninth, tenth, eleventh, and twelfth NAND gates, and its output terminal outputs 1 bit of the intermediate value.

[0029] Preferably, both the fourth inverter and the fifth inverter are NOT gates.

[0030] A second aspect of the present invention discloses an in-memory computing architecture based on a convolutional neural network, including a multi-bit signed all-digital in-memory computing device based on Boss multiplication as described above.

[0031] A third aspect of the present invention discloses a computer device comprising the aforementioned multi-bit signed all-digital in-memory computing device based on Booz multiplication.

[0032] Through one or more technical solutions of the present invention, the present invention has the following beneficial effects or advantages:

[0033] This invention discloses a multi-bit signed all-digital in-memory computing device based on Booz multiplication. This device is applied to an in-memory computing architecture based on convolutional neural networks. It stores a 4-bit weight using four basic SRAM cells. A Booz multiplier and adder structure is combined to process the multiplication of a 4-bit signed weight and a 4-bit signed input stimulus. During the calculation, voltage VDD represents "+1" and voltage VSS represents "-1". After bitwise multiplication using Booz multiplication, a 7-bit signed multiplication result is obtained, and the output is in two's complement form. This allows for the calculation of the multiplication result of the two 4-bit signed numbers (input stimulus and weight) within one clock cycle, significantly improving computational efficiency.

[0034] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings.

[0036] In the attached diagram:

[0037] Figure 1 A schematic diagram of the structure of a multi-bit signed all-digital in-memory computing device based on Bos multiplication according to an embodiment of the present invention is shown.

[0038] Figure 2 A schematic diagram of the Bos multiplication structure according to an embodiment of the present invention is shown;

[0039] Figure 3 A schematic diagram of the control signal generation circuit structure of a selection module according to an embodiment of the present invention is shown;

[0040] Figure 4 A schematic diagram of the circuit structure of a partial product generation module according to an embodiment of the present invention is shown. Detailed Implementation

[0041] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0042] This invention discloses a multi-bit signed all-digital in-memory computing device based on Booz multiplication. This device is applied to an in-memory computing architecture based on convolutional neural networks. It stores a 4-bit weight using four basic SRAM cells. A Booz multiplier and adder structure is combined to process the multiplication of a 4-bit signed weight and a 4-bit signed input stimulus. During the calculation, voltage VDD represents "+1" and voltage VSS represents "-1". After bitwise multiplication using Booz multiplication, a 7-bit signed multiplication result is obtained, and the output is in two's complement form. This allows for the calculation of the multiplication result of the two 4-bit signed numbers (input stimulus and weight) within one clock cycle, significantly improving computational efficiency.

[0043] See Figure 1 This is a schematic diagram of a multi-bit signed all-digital in-memory computing device based on Bos multiplication, including: four basic SRAM cells, a Bos multiplier, and an adder structure 31.

[0044] Four basic SRAM cells, arranged from top to bottom, are used to store weights. The four basic SRAM cells are located in the same column, and each SRAM cell consists of six transistors. The bit line pairs of the four basic SRAM cells are interconnected. Specifically, the bit line pairs include bit line BL and bit line BLB. The bit lines BL of the four basic SRAM cells are connected sequentially, and the bit lines BLB of the four basic SRAM cells are connected sequentially. The word lines of the four basic SRAM cells are independent of each other, and the Q-terminal of each of the four basic SRAM cells outputs a 1-bit weight.

[0045] Among them, a 4-bit signed weight W[3:0] is stored in the four basic SRAM units in the order of high bit to low bit from top to bottom according to the two's complement method. Each SRAM unit stores 1 bit weight, and the order from top to bottom is: the first SRAM unit 11 stores W[3], the second SRAM unit 12 stores W[2], the third SRAM unit 13 stores W[1], and the fourth SRAM unit 14 stores W[0].

[0046] The Bos multiplier consists of two Bos multiplier structures, namely the first Bos multiplier structure 21 and the second Bos multiplier structure 22; the input of each Bos multiplier structure is a 3-bit weight and a 4-bit input stimulus. The input stimulus is stored in two's complement form.

[0047] The first Bos multiplication structure 21 connects the first SRAM unit 11, the second SRAM unit 12, and the third SRAM unit 13 arranged from top to bottom among the four basic SRAM units. It is used to receive the 3-bit weights jointly output by the first SRAM unit 11, the second SRAM unit 12, and the third SRAM unit 13 as a selection control signal, and input 4-bit input excitation to participate in the calculation to obtain the first partial product. Specifically, the input of the first Bos multiplication structure 21 is a 3-bit weight W[3:1], including W[3], W[2], W[1]; a 4-bit input excitation IN[3:0], including IN[3], IN[2], IN[1], IN[0]; and the output is the first partial product PH[3:0], including: PH[3], PH[2], PH[1], PH[0].

[0048] The second Bos multiplication structure 22 connects the third SRAM unit 13 and the fourth SRAM unit 14 arranged from top to bottom among the four basic SRAM units, and sets an input terminal to be concatenated in the least significant bit for weight input. It is used to take the 3-bit weights received from the third SRAM unit 13, the fourth SRAM unit 14 and the least significant bit as the selection control signal, and input the 4-bit input stimulus to participate in the calculation to obtain the second partial product. Specifically, the input of the second Bos multiplication structure 22 is a 3-bit weight {W[1:0], 0}, including W[1], W[0], 0, with weight 0 concatenated in the least significant bit for input; the 4-bit input stimulus IN[3:0], and the output is the second partial product PL[3:0], including: PL[3], PL[2], PL[1], PL[0].

[0049] Adder structure 31 is connected to the first Bos multiplication structure 21 and the second Bos multiplication structure 22 respectively, and adds the first partial product and the second partial product to obtain the final result. Specifically, the input of adder structure 31 is two partial products PH[3:0] and PL[3:0], and the output is the final multiplication result OUT[6:0].

[0050] In this embodiment, by combining the Bos multiplier and adder structure 31 to process the multiplication process of a 4-bit signed weight and a 4-bit signed input stimulus, the multiplication result of a 4-bit signed weight and a 4-bit signed input stimulus can be calculated within one clock cycle, which can significantly improve the computational efficiency.

[0051] See Figure 2 This is a schematic diagram of the Boehringer-Stokes multiplication structure. The first Boehringer-Stokes multiplication structure 21 and the second Boehringer-Stokes multiplication structure 22 are identical. Each Boehringer-Stokes multiplication structure includes: a selection module 211, four partial product generation modules 212, and four half-adder modules 213. Figure 2 In the middle, the four partial product generation modules 212 and the four half-adder modules 213 are arranged in the same order from left to right according to the input excitation from low bit to high bit.

[0052] One end of the selection module 211 inputs 3-bit weights: W[i+1], W[i], W[i-1]. Among them, for the first Boss multiplication structure 21 that generates the partial product PH[3:0], it is the 3-bit input of W[3:1], and for the second Boss multiplication structure 22 that generates the partial product PL[3:0], it is the 3-bit input of {W[1:0], 0}.

[0053] The other end of the selection module 211 is connected to each partial product generation module 212 via four wires, and is used to select the operation to be performed on each input stimulus according to the 3-bit weight of the input; wherein, the other end of the selection module 211 selectively outputs the following via four wires: left shift by two bits operation 2X, original data X, inversion operation -X, left shift followed by inversion and increment operation -2X to the partial product generation module 212.

[0054] Each of the four partial product generation modules 212 is connected to a half-adder module 213. The input of the first partial product generation module is the input stimulus of the current bit and 0. The input stimulus 0 is obtained by padding the least significant bit with 0, specifically: {IN[0], 0}. The inputs of the other partial product generation modules are the input stimulus of the current bit and the input stimulus of the previous bit, in the following order: IN[1:0], IN[2:1], IN[3:2]. Each partial product generation module 212 selects the output result of each bit according to the input 2X, X, -X, -2X. Since the addition operation of -X and -2X is not performed, the output of each partial product generation module 212 is a 1-bit intermediate value that has not been added, which is used as the input of the corresponding half-adder module. The four partial product generation modules 212 jointly output a 4-bit intermediate value XO[3:0].

[0055] The input of the first half-adder module in the four half-adder modules 213 is connected to an OR gate, the carry output of the previous half-adder module 213 is connected to the input of the next half-adder module 213, and the sum of the four half-adder modules 213 outputs a partial product. The four half-adder modules 213 and the OR gate together implement the addition function. The OR gate activates the addition function only in -X and -2X, and no addition is performed in other states, so that the four half-adder modules 213 jointly output a partial product.

[0056] In some alternative implementations, see Figure 3 This is a schematic diagram of the control signal generation circuit structure of the selection module 211. The selection module 211 includes: multiple inverters, a first NAND gate combination structure, a second NAND gate combination structure, a third NAND gate combination structure, and a fourth NAND gate combination structure.

[0057] Specifically, the selection module 211 includes a first inverter L1, a second inverter L2, and a third inverter L3, each used to invert a 1-bit weight arranged from the most significant bit to the least significant bit. Specifically, the first inverter L1 receives a 1-bit first weight W[i+1], the second inverter L2 receives a 1-bit second weight W[i], and the third inverter L3 receives a 1-bit third weight W[i-1]. In this embodiment, the first inverter L1, the second inverter L2, and the third inverter L3 are all NOT gates.

[0058] The first NAND gate combination structure includes a first NAND gate 2111, a second NAND gate 2112, and a third NAND gate 2113; wherein, the input terminal of the first NAND gate 2111 is connected to the output terminal of the first inverter L1, the second weight, and the output terminal of the third inverter L3; the input terminal of the second NAND gate 2112 is connected to the output terminal of the first inverter L1, the output terminal of the second inverter L2, and the third weight; the output terminals of the first NAND gate 2111 and the second NAND gate 2112 are jointly connected to the input terminal of the third NAND gate 2113, and the output terminal of the third NAND gate 2113 outputs X;

[0059] The second NAND gate 2112 combination structure includes a fourth NAND gate 2114 and a first NOT gate 2119 connected in series; wherein, the input terminal of the fourth NAND gate 2114 is connected to the output terminal of the first inverter L1, the second weight and the third weight, and the output terminal of the first NOT gate 2119 outputs 2X;

[0060] The third NAND gate 2113 combination structure includes a fifth NAND gate 2115 and a second NOT gate 2120 connected in series; wherein, the input terminal of the fifth NAND gate 2115 is connected to the first weight, the output terminal of the second inverter L2 and the output terminal of the third inverter L3, and the output terminal of the first NOT gate 2119 outputs -2X;

[0061] The fourth NAND gate 2114 combination structure includes a sixth NAND gate 2116, a seventh NAND gate 2117, and an eighth NAND gate 2118; wherein, the input terminal of the sixth NAND gate 2116 is connected to the first weight, the second weight, and the output terminal of the third inverter L3; the input terminal of the seventh NAND gate 2117 is connected to the first weight, the output terminal of the second inverter L2, and the third weight; the output terminals of the sixth NAND gate 2116 and the seventh NAND gate 2117 are jointly connected to the input terminal of the eighth NAND gate 2118, and the output terminal of the eighth NAND gate 2118 outputs -X.

[0062] In some alternative implementations, see Figure 4 This is a circuit diagram of the partial product generation module 212, including a selection circuit composed of two NAND gates, which selects different outputs based on 2X, X, -X, and -2X. Specifically, the partial product generation module 212 includes:

[0063] The fourth inverter L4 and the fifth inverter L5 are both NOT gates. The fourth inverter L4 is inverted by the current input stimulus IN[i], and the fifth inverter L5 is inverted by the previous input stimulus IN[i-1]. IN[i] and IN[i-1] are the current input stimulus and the previous input stimulus, respectively. Depending on the signal, a shift or inversion operation is performed. A shift operates on the previous input stimulus, while an inversion operates on the current input stimulus.

[0064] The ninth NAND gate 2121 has -X at its input and the inverse signal of the local input excitation IN[i] output from the output of the fourth inverter L4.

[0065] The tenth NAND gate 2122 has X and the local input stimulus IN[i] connected to its input terminal;

[0066] The eleventh NAND gate 2123 is connected to -2X at its input and to the inverse signal of the previous bit input excitation IN[i-1] output from the output of the fifth inverter L5;

[0067] The twelfth NAND gate 2124 has 2X and the previous bit input stimulus IN[i-1] connected to its input terminal;

[0068] The thirteenth NAND gate 2125 has its input terminals connected to the ninth NAND gate 2121, the tenth NAND gate 2122, the eleventh NAND gate 2123, and the twelfth NAND gate 2114, and its output terminal outputs 1 bit of the intermediate value XO[i].

[0069] The above describes the specific structure of a multi-bit signed all-digital in-memory computing device based on Boehringer's Law (BPS) multiplication. Operations based on this structure are divided into two modes: storage mode and computation mode. In storage mode, write operations are performed similarly to a normal SRAM. When a word line is pulled high, the weight data of the bit line is written into the SRAM cell. The weight data is stored in high-to-low bit order, and each group (four SRAM cells) stores a 4-bit signed weight using two's complement.

[0070] In computation mode, the word lines of the SRAM cells are turned off, weight writing stops, input stimulus enters and activates the Bos multiplication structure, and computation mode begins. In computation mode, the intermediate value of the partial product is first obtained, and then, depending on the requirements, 1 is added to generate the partial product. The partial products are then added together to obtain the final multiplication result. Of course, both the input stimulus and the computation result are presented in two's complement form.

[0071] The advantage of the Bos multiplication structure in this embodiment is that, instead of producing four partial products for the multiplication of two 4-bit numbers, the Bos multiplication structure constructed in this embodiment can reduce this to two, thereby saving resources during the partial accumulation process. The multiplication result of the two 4-bit signed numbers, the input stimulus and the weight, can be calculated in one clock cycle.

[0072] To illustrate and explain the present invention, specific examples are used below to derive and prove the Boss multiplication structure.

[0073] Suppose we have two 4-bit numbers X and Y, where [Y] 补 =y3y2y1y0, according to the definition of two's complement:

[0074] Y = -y³ * 2 3 +y2*2 2 +y1*2 1 +y0*2 0

[0075] Based on the above results, [X*Y] 补 By derivation, we obtain:

[0076] [X*Y] 补 =[X*(-y3*2)] 3 +y2*2 2 +y1*2 1 +y0*2 0 )] 补 =[X*(-y3)*2 3 +X*y2*22+X*y1*2 1 +X*y0*2 0 ] 补 =[X]补 *(-y3)*2 3 +[X] 补 *y2*2 2 +[X] 补 *y1*2 1 +[X] 补 *y0*2 0 =[X] 补 *[-y3*2 3 +y2*2 2 +y1*2 1 +y0*2 0 ]

[0077] The above expression contains four partial product results. For the two-digit Boehs multiplication structure, the main purpose is to reduce the number of addition terms. Therefore, using Boehs multiplication simplifies the above expression to:

[0078] [X*Y] 补 =[X] 补 *[(-2*y3+y2+y1)*2 2 +(-2*y1+y0+y -1 )*2 0 ]

[0079] Where y -1 =0. Based on the above formula, the partial product can be reduced to two, by observing the two-digit multiplier each time to reduce the partial product. The rules for generating the partial product are shown in Table 1 below:

[0080] Table 1

[0081]

[0082]

[0083] Based on the results in Table 1, the circuit is constructed. 2X, X, -X, and -2X in the circuit indicate different operations. Based on the logic generated by the partial product, the Boolean logic for generating the selection signal is as follows:

[0084]

[0085]

[0086]

[0087] This leads to the circuit structure for the selection signal, namely selection module 211. Then, based on different selection signals, the result of each bit of the partial product is determined, resulting in the following Boolean logic:

[0088] x i= (+X)*x i +(-X)*(-x i )+(+2X)*x i-1 +(-2X)*(-x i-1 )

[0089] The circuit structure for partial product generation, module 212, is obtained through the Boolean logic described above. Here, -xi represents bitwise inversion and increment. The half-adder in the circuit uses an AND gate to generate a carry to determine whether to perform an increment operation.

[0090] Compared to existing in-memory computing units, this invention has two advantages:

[0091] 1. Compared with the charge and discharge characterization values ​​of analog in-memory computing units, the results of the all-digital in-memory computing device of the present invention are more robust.

[0092] 2. Since the fully digital in-memory computing device disclosed in this invention simplifies the number of partial product generation through the Booz multiplication structure, compared with the shortcomings of other digital in-memory computing units that still require multiple clock cycles for shifting and adding when calculating multi-bit data, this invention can complete the multiplication of two 4-bit signed data in one clock cycle, which greatly improves the computational efficiency.

[0093] Based on the same inventive concept as in the foregoing embodiments, this embodiment of the invention also discloses an in-memory computing architecture based on convolutional neural networks, including the multi-bit signed all-digital in-memory computing device based on Bos multiplication described in the foregoing embodiments.

[0094] Based on the same inventive concept as in the foregoing embodiments, this invention also discloses a computer device, including the multi-bit signed all-digital in-memory computing device based on Bos multiplication described in the foregoing embodiments.

[0095] Through one or more embodiments of the present invention, the present invention has the following beneficial effects or advantages:

[0096] This invention discloses a multi-bit signed all-digital in-memory computing device based on Booz multiplication. This device is applied to an in-memory computing architecture based on convolutional neural networks. It stores a 4-bit weight using four basic SRAM cells. A Booz multiplier and adder structure is combined to process the multiplication of a 4-bit signed weight and a 4-bit signed input stimulus. During the calculation, voltage VDD represents "+1" and voltage VSS represents "-1". After bitwise multiplication using Booz multiplication, a 7-bit signed multiplication result is obtained, and the output is in two's complement form. This allows for the calculation of the multiplication result of the two 4-bit signed numbers (input stimulus and weight) within one clock cycle, significantly improving computational efficiency.

[0097] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0098] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A multi-bit signed all-digital in-memory computing device based on Booz multiplication, characterized in that, include: Four basic SRAM cells arranged from top to bottom are used to store weights; A 4-bit signed weight is stored sequentially in the four basic SRAM cells in two's complement form, from top to bottom and from high to low bits, with each SRAM cell storing 1 bit of weight. The Bos multiplier includes two Bos multiplication structures: a first Bos multiplication structure and a second Bos multiplication structure. These two structures are identical. Each Bos multiplication structure includes: a selection module, four partial product generation modules, and four half-adder modules. One end of the selection module receives a 3-bit weight, and the other end is connected to each partial product generation module via four wires. This selection module selects the operation to be performed on each input stimulus based on the input 3-bit weight. Here, 2X represents a left shift operation by two bits, X represents the original data, -X represents a negation operation, and -2... X represents a left shift followed by inversion and increment; each of the four partial product generation modules is connected to a half-adder module; the input of each partial product generation module is the current input stimulus and the input stimulus of the previous bit, and the input of the first partial product generation module is the current input stimulus and 0; the output of each partial product generation module is a 1-bit intermediate value before incrementing, which serves as the input of the corresponding half-adder module; the input of the first half-adder module is connected to an OR gate, and the carry output of the previous half-adder module is connected to the input of the next half-adder module. The block outputs the partial product; wherein, the four half-adder modules and the OR gate are combined to implement the addition function, and the OR gate is used to activate the addition function only in -X and -2X, and no addition is performed in other states, so that the four half-adder modules output the partial product; wherein, the first Boss multiplication structure is connected to the first SRAM unit, the second SRAM unit, and the third SRAM unit arranged from top to bottom in the four basic SRAM units, and is used to receive the 3-bit weight jointly output by the first SRAM unit, the second SRAM unit, and the third SRAM unit as a selection control signal, and input 4-bit input stimulus to participate in the calculation to obtain the first partial product; the second Boss multiplication structure is connected to the third SRAM unit and the fourth SRAM unit arranged from top to bottom in the four basic SRAM units, and sets an input terminal to be concatenated in the least significant bit for weight input, and is used to receive the 3-bit weight jointly output by the third SRAM unit, the fourth SRAM unit, and the least significant bit as a selection control signal, and input the 4-bit input stimulus to participate in the calculation to obtain the second partial product; An adder structure is connected to the first Bos multiplication structure and the second Bos multiplication structure respectively, and the first partial product and the second partial product are added together to obtain the final result.

2. The apparatus as claimed in claim 1, characterized in that, The bit lines of the four basic SRAM cells are interconnected, the word lines of the four basic SRAM cells are independent of each other, and each of the four basic SRAM cells outputs a 1-bit weight.

3. The apparatus as described in claim 1, characterized in that, The selection module includes: a first inverter, a second inverter, and a third inverter, each used to invert a 1-bit weight arranged from high to low. The first inverter is connected to a 1-bit first weight, the second inverter is connected to a 1-bit second weight, and the third inverter is connected to a 1-bit third weight.

4. The apparatus as described in claim 3, characterized in that, The first inverter, the second inverter, and the third inverter are all NOT gates.

5. The apparatus as described in claim 3, characterized in that, The selection module further includes: The first NAND gate combination structure includes a first NAND gate, a second NAND gate, and a third NAND gate; wherein, the input terminal of the first NAND gate is connected to the output terminal of the first inverter, the second weight, and the output terminal of the third inverter; the input terminal of the second NAND gate is connected to the output terminal of the first inverter, the output terminal of the second inverter, and the third weight; the output terminals of the first NAND gate and the second NAND gate are jointly connected to the input terminal of the third NAND gate, and the output terminal of the third NAND gate outputs X; The second NAND gate combination structure includes a fourth NAND gate and a first NOT gate connected in series; wherein, the input terminal of the fourth NAND gate is connected to the output terminal of the first inverter, the second weight and the third weight, and the output terminal of the first NOT gate outputs 2X; The third NAND gate combination structure includes a fifth NAND gate and a second NOT gate connected in series; wherein, the input terminal of the fifth NAND gate is connected to the first weight, the output terminal of the second inverter and the output terminal of the third inverter, and the output terminal of the first NOT gate outputs -2X; The fourth NAND gate combination structure includes a sixth NAND gate, a seventh NAND gate, and an eighth NAND gate; wherein, the input terminal of the sixth NAND gate is connected to the first weight, the second weight, and the output terminal of the third inverter; the input terminal of the seventh NAND gate is connected to the first weight, the output terminal of the second inverter, and the third weight; the output terminals of the sixth and seventh NAND gates are jointly connected to the input terminal of the eighth NAND gate, and the output terminal of the eighth NAND gate outputs -X.

6. The apparatus as claimed in claim 1, characterized in that, The partial product generation module includes: A fourth inverter and a fifth inverter; wherein the fourth inverter is connected to the current input stimulus for inversion, and the fifth inverter is connected to the previous input stimulus for inversion; The ninth NAND gate has its input terminal connected to -X and the output terminal of the fourth inverter. The tenth NAND gate has X and the local input stimulus connected to its input terminal; The eleventh NAND gate has its input connected to -2X and the output of the fifth inverter. The twelfth NAND gate has 2X and the previous bit input stimulus connected to its input terminal; The thirteenth NAND gate has its input terminals connected to the ninth, tenth, eleventh, and twelfth NAND gates, and its output terminal outputs 1 bit of the intermediate value.

7. The apparatus as claimed in claim 6, characterized in that, Both the fourth inverter and the fifth inverter are NOT gates.

8. An in-memory computing architecture based on convolutional neural networks, characterized in that, Includes a multi-bit signed all-digital in-memory computing device based on Bos multiplication as described in any one of claims 1-7.

9. A computer device, characterized in that, Includes a multi-bit signed all-digital in-memory computing device based on Bos multiplication as described in any one of claims 1-7.

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